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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 Øyvind Harboe                                      *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "imp.h"
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34 #include <target/armv7m.h>
  35
  36 /* Regarding performance:
  37  *
  38  * Short story - it might be best to leave the performance at
  39  * current levels.
  40  *
  41  * You may see a jump in speed if you change to using
  42  * 32bit words for the block programming.
  43  *
  44  * Its a shame you cannot use the double word as its
  45  * even faster - but you require external VPP for that mode.
  46  *
  47  * Having said all that 16bit writes give us the widest vdd
  48  * operating range, so may be worth adding a note to that effect.
  49  *
  50  */
  51
  52 /* Danger!!!! The STM32F1x and STM32F2x series actually have
  53  * quite different flash controllers.
  54  *
  55  * What's more scary is that the names of the registers and their
  56  * addresses are the same, but the actual bits and what they do are
  57  * can be very different.
  58  *
  59  * To reduce testing complexity and dangers of regressions,
  60  * a seperate file is used for stm32fx2x.
  61  *
  62  * 1mByte part with 4 x 16, 1 x 64, 7 x 128kBytes sectors
  63  *
  64  * What's the protection page size???
  65  *
  66  * Tested with STM3220F-EVAL board.
  67  *
  68  * STM32F21xx series for reference.
  69  *
  70  * RM0033
  71  * http://www.st.com/internet/mcu/product/250192.jsp
  72  *
  73  * PM0059
  74  * www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/
  75  * PROGRAMMING_MANUAL/CD00233952.pdf
  76  *
  77  * STM32F1x series - notice that this code was copy, pasted and knocked
  78  * into a stm32f2x driver, so in case something has been converted or
  79  * bugs haven't been fixed, here are the original manuals:
  80  *
  81  * RM0008 - Reference manual
  82  *
  83  * RM0042, the Flash programming manual for low-, medium- high-density and
  84  * connectivity line STM32F10x devices
  85  *
  86  * PM0068, the Flash programming manual for XL-density STM32F10x devices.
  87  *
  88  */
  89
  90 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
  91 #define FLASH_ERASE_TIMEOUT 10000
  92 #define FLASH_WRITE_TIMEOUT 5
  93
  94 #define STM32_FLASH_BASE        0x40023c00
  95 #define STM32_FLASH_ACR         0x40023c00
  96 #define STM32_FLASH_KEYR        0x40023c04
  97 #define STM32_FLASH_OPTKEYR     0x40023c08
  98 #define STM32_FLASH_SR          0x40023c0C
  99 #define STM32_FLASH_CR          0x40023c10
 100 #define STM32_FLASH_OPTCR       0x40023c14
 101 #define STM32_FLASH_OBR         0x40023c1C
 102
 103 /* option byte location */
 104
 105 #define STM32_OB_RDP            0x1FFFF800
 106 #define STM32_OB_USER           0x1FFFF802
 107 #define STM32_OB_DATA0          0x1FFFF804
 108 #define STM32_OB_DATA1          0x1FFFF806
 109 #define STM32_OB_WRP0           0x1FFFF808
 110 #define STM32_OB_WRP1           0x1FFFF80A
 111 #define STM32_OB_WRP2           0x1FFFF80C
 112 #define STM32_OB_WRP3           0x1FFFF80E
 113
 114 /* FLASH_CR register bits */
 115
 116 #define FLASH_PG                (1 << 0)
 117 #define FLASH_SER               (1 << 1)
 118 #define FLASH_MER               (1 << 2)
 119 #define FLASH_STRT              (1 << 16)
 120 #define FLASH_PSIZE_8   (0 << 8)
 121 #define FLASH_PSIZE_16  (1 << 8)
 122 #define FLASH_PSIZE_32  (2 << 8)
 123 #define FLASH_PSIZE_64  (3 << 8)
 124 #define FLASH_SNB(a)    ((a) << 3)
 125 #define FLASH_LOCK              (1 << 31)
 126
 127 /* FLASH_SR register bits */
 128
 129 #define FLASH_BSY               (1 << 16)
 130 #define FLASH_PGSERR    (1 << 7) /* Programming sequence error */
 131 #define FLASH_PGPERR    (1 << 6) /* Programming parallelism error */
 132 #define FLASH_PGAERR    (1 << 5) /* Programming alignment error */
 133 #define FLASH_WRPERR    (1 << 4) /* Write protection error */
 134 #define FLASH_OPERR             (1 << 1) /* Operation error */
 135
 136 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
 137
 138 /* STM32_FLASH_OBR bit definitions (reading) */
 139
 140 #define OPT_ERROR               0
 141 #define OPT_READOUT             1
 142 #define OPT_RDWDGSW             2
 143 #define OPT_RDRSTSTOP   3
 144 #define OPT_RDRSTSTDBY  4
 145 #define OPT_BFB2                5       /* dual flash bank only */
 146
 147 /* register unlock keys */
 148
 149 #define KEY1                    0x45670123
 150 #define KEY2                    0xCDEF89AB
 151
 152 struct stm32x_flash_bank {
 153         struct working_area *write_algorithm;
 154         int probed;
 155 };
 156
 157
 158 /* flash bank stm32x <base> <size> 0 0 <target#>
 159  */
 160 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 161 {
 162         struct stm32x_flash_bank *stm32x_info;
 163
 164         if (CMD_ARGC < 6)
 165                 return ERROR_COMMAND_SYNTAX_ERROR;
 166
 167         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 168         bank->driver_priv = stm32x_info;
 169
 170         stm32x_info->write_algorithm = NULL;
 171         stm32x_info->probed = 0;
 172
 173         return ERROR_OK;
 174 }
 175
 176 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 177 {
 178         return reg;
 179 }
 180
 181 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 182 {
 183         struct target *target = bank->target;
 184         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 185 }
 186
 187 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 188 {
 189         struct target *target = bank->target;
 190         uint32_t status;
 191         int retval = ERROR_OK;
 192
 193         /* wait for busy to clear */
 194         for (;;) {
 195                 retval = stm32x_get_flash_status(bank, &status);
 196                 if (retval != ERROR_OK)
 197                         return retval;
 198                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 199                 if ((status & FLASH_BSY) == 0)
 200                         break;
 201                 if (timeout-- <= 0) {
 202                         LOG_ERROR("timed out waiting for flash");
 203                         return ERROR_FAIL;
 204                 }
 205                 alive_sleep(1);
 206         }
 207
 208
 209         if (status & FLASH_WRPERR) {
 210                 LOG_ERROR("stm32x device protected");
 211                 retval = ERROR_FAIL;
 212         }
 213
 214         /* Clear but report errors */
 215         if (status & FLASH_ERROR) {
 216                 /* If this operation fails, we ignore it and report the original
 217                  * retval
 218                  */
 219                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 220                                 status & FLASH_ERROR);
 221         }
 222         return retval;
 223 }
 224
 225 static int stm32x_unlock_reg(struct target *target)
 226 {
 227         uint32_t ctrl;
 228
 229         /* first check if not already unlocked
 230          * otherwise writing on STM32_FLASH_KEYR will fail
 231          */
 232         int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
 233         if (retval != ERROR_OK)
 234                 return retval;
 235
 236         if ((ctrl & FLASH_LOCK) == 0)
 237                 return ERROR_OK;
 238
 239         /* unlock flash registers */
 240         retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 241         if (retval != ERROR_OK)
 242                 return retval;
 243
 244         retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 245         if (retval != ERROR_OK)
 246                 return retval;
 247
 248         retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
 249         if (retval != ERROR_OK)
 250                 return retval;
 251
 252         if (ctrl & FLASH_LOCK) {
 253                 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %x", ctrl);
 254                 return ERROR_TARGET_FAILURE;
 255         }
 256
 257         return ERROR_OK;
 258 }
 259
 260 static int stm32x_protect_check(struct flash_bank *bank)
 261 {
 262         return ERROR_OK;
 263 }
 264
 265 static int stm32x_erase(struct flash_bank *bank, int first, int last)
 266 {
 267         struct target *target = bank->target;
 268         int i;
 269
 270         if (bank->target->state != TARGET_HALTED) {
 271                 LOG_ERROR("Target not halted");
 272                 return ERROR_TARGET_NOT_HALTED;
 273         }
 274
 275         int retval;
 276         retval = stm32x_unlock_reg(target);
 277         if (retval != ERROR_OK)
 278                 return retval;
 279
 280         /*
 281         Sector Erase
 282         To erase a sector, follow the procedure below:
 283         1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
 284           FLASH_SR register
 285         2. Set the SER bit and select the sector (out of the 12 sectors in the main memory block)
 286           you wish to erase (SNB) in the FLASH_CR register
 287         3. Set the STRT bit in the FLASH_CR register
 288         4. Wait for the BSY bit to be cleared
 289          */
 290
 291         for (i = first; i <= last; i++) {
 292                 retval = target_write_u32(target,
 293                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_SER | FLASH_SNB(i) | FLASH_STRT);
 294                 if (retval != ERROR_OK)
 295                         return retval;
 296
 297                 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 298                 if (retval != ERROR_OK)
 299                         return retval;
 300
 301                 bank->sectors[i].is_erased = 1;
 302         }
 303
 304         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 305         if (retval != ERROR_OK)
 306                 return retval;
 307
 308         return ERROR_OK;
 309 }
 310
 311 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
 312 {
 313         return ERROR_OK;
 314 }
 315
 316 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 317                 uint32_t offset, uint32_t count)
 318 {
 319         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 320         struct target *target = bank->target;
 321         uint32_t buffer_size = 16384;
 322         struct working_area *source;
 323         uint32_t address = bank->base + offset;
 324         struct reg_param reg_params[5];
 325         struct armv7m_algorithm armv7m_info;
 326         int retval = ERROR_OK;
 327
 328         /* see contrib/loaders/flash/stm32f2x.S for src */
 329
 330         static const uint16_t stm32x_flash_write_code_16[] = {
 331                 /* 00000000 <write>: */
 332                 0x4b07,                         /* ldr          r3, [pc, #28] (20 <STM32_PROG16>) */
 333                 0x6123,                         /* str          r3, [r4, #16] */
 334                 0xf830, 0x3b02,         /* ldrh.w       r3, [r0], #2 */
 335                 0xf821, 0x3b02,         /* strh.w       r3, [r1], #2 */
 336
 337                 /* 0000000c <busy>: */
 338                 0x68e3,                         /* ldr          r3, [r4, #12] */
 339                 0xf413, 0x3f80,         /* tst.w        r3, #65536      ; 0x10000 */
 340                 0xd0fb,                         /* beq.n        c <busy> */
 341                 0xf013, 0x0ff0,         /* tst.w        r3, #240        ; 0xf0 */
 342                 0xd101,                         /* bne.n        1e <exit> */
 343                 0x3a01,                         /* subs         r2, #1 */
 344                 0xd1f0,                         /* bne.n        0 <write> */
 345                                                         /* 0000001e <exit>: */
 346                 0xbe00,                         /* bkpt         0x0000 */
 347
 348                 /* 00000020 <STM32_PROG16>: */
 349                 0x0101, 0x0000,         /* .word        0x00000101 */
 350         };
 351
 352         /* Flip endian */
 353         uint8_t stm32x_flash_write_code[sizeof(stm32x_flash_write_code_16)*2];
 354         for (unsigned i = 0; i < sizeof(stm32x_flash_write_code_16) / 2; i++) {
 355                 stm32x_flash_write_code[i*2 + 0] = stm32x_flash_write_code_16[i] & 0xff;
 356                 stm32x_flash_write_code[i*2 + 1] = (stm32x_flash_write_code_16[i] >> 8) & 0xff;
 357         }
 358
 359         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 360                         &stm32x_info->write_algorithm) != ERROR_OK) {
 361                 LOG_WARNING("no working area available, can't do block memory writes");
 362                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 363         };
 364
 365         retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
 366                         sizeof(stm32x_flash_write_code),
 367                         (uint8_t *)stm32x_flash_write_code);
 368         if (retval != ERROR_OK)
 369                 return retval;
 370
 371         /* memory buffer */
 372         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 373                 buffer_size /= 2;
 374                 if (buffer_size <= 256) {
 375                         /* if we already allocated the writing code, but failed to get a
 376                          * buffer, free the algorithm */
 377                         if (stm32x_info->write_algorithm)
 378                                 target_free_working_area(target, stm32x_info->write_algorithm);
 379
 380                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 381                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 382                 }
 383         };
 384
 385         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 386         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 387
 388         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 389         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 390         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 391         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT);
 392         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
 393
 394         while (count > 0) {
 395                 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
 396                                 (buffer_size / 2) : count;
 397
 398                 retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer);
 399                 if (retval != ERROR_OK)
 400                         break;
 401
 402                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 403                 buf_set_u32(reg_params[1].value, 0, 32, address);
 404                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
 405                 /* R3 is a return value only */
 406                 buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
 407
 408                 retval = target_run_algorithm(target, 0, NULL,
 409                                 sizeof(reg_params) / sizeof(*reg_params),
 410                                 reg_params,
 411                                 stm32x_info->write_algorithm->address,
 412                                 0,
 413                                 10000, &armv7m_info);
 414                 if (retval != ERROR_OK) {
 415                         LOG_ERROR("error executing stm32x flash write algorithm");
 416                         break;
 417                 }
 418
 419                 uint32_t error = buf_get_u32(reg_params[3].value, 0, 32) & FLASH_ERROR;
 420
 421                 if (error & FLASH_WRPERR)
 422                         LOG_ERROR("flash memory write protected");
 423
 424                 if (error != 0) {
 425                         LOG_ERROR("flash write failed = %08x", error);
 426                         /* Clear but report errors */
 427                         target_write_u32(target, STM32_FLASH_SR, error);
 428                         retval = ERROR_FAIL;
 429                         break;
 430                 }
 431
 432                 buffer += thisrun_count * 2;
 433                 address += thisrun_count * 2;
 434                 count -= thisrun_count;
 435         }
 436
 437         target_free_working_area(target, source);
 438         target_free_working_area(target, stm32x_info->write_algorithm);
 439
 440         destroy_reg_param(&reg_params[0]);
 441         destroy_reg_param(&reg_params[1]);
 442         destroy_reg_param(&reg_params[2]);
 443         destroy_reg_param(&reg_params[3]);
 444         destroy_reg_param(&reg_params[4]);
 445
 446         return retval;
 447 }
 448
 449 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
 450                 uint32_t offset, uint32_t count)
 451 {
 452         struct target *target = bank->target;
 453         uint32_t words_remaining = (count / 2);
 454         uint32_t bytes_remaining = (count & 0x00000001);
 455         uint32_t address = bank->base + offset;
 456         uint32_t bytes_written = 0;
 457         int retval;
 458
 459         if (bank->target->state != TARGET_HALTED) {
 460                 LOG_ERROR("Target not halted");
 461                 return ERROR_TARGET_NOT_HALTED;
 462         }
 463
 464         if (offset & 0x1) {
 465                 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 466                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 467         }
 468
 469         retval = stm32x_unlock_reg(target);
 470         if (retval != ERROR_OK)
 471                 return retval;
 472
 473         /* multiple half words (2-byte) to be programmed? */
 474         if (words_remaining > 0) {
 475                 /* try using a block write */
 476                 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
 477                 if (retval != ERROR_OK) {
 478                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 479                                 /* if block write failed (no sufficient working area),
 480                                  * we use normal (slow) single dword accesses */
 481                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 482                         }
 483                 } else {
 484                         buffer += words_remaining * 2;
 485                         address += words_remaining * 2;
 486                         words_remaining = 0;
 487                 }
 488         }
 489
 490         if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
 491                 return retval;
 492
 493         /*
 494         Standard programming
 495         The Flash memory programming sequence is as follows:
 496         1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
 497           FLASH_SR register.
 498         2. Set the PG bit in the FLASH_CR register
 499         3. Perform the data write operation(s) to the desired memory address (inside main
 500           memory block or OTP area):
 501         – – Half-word access in case of x16 parallelism
 502         – Word access in case of x32 parallelism
 503         –
 504         4.
 505         Byte access in case of x8 parallelism
 506         Double word access in case of x64 parallelism
 507         Wait for the BSY bit to be cleared
 508         */
 509         while (words_remaining > 0) {
 510                 uint16_t value;
 511                 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
 512
 513                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
 514                                 FLASH_PG | FLASH_PSIZE_16);
 515                 if (retval != ERROR_OK)
 516                         return retval;
 517
 518                 retval = target_write_u16(target, address, value);
 519                 if (retval != ERROR_OK)
 520                         return retval;
 521
 522                 retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
 523                 if (retval != ERROR_OK)
 524                         return retval;
 525
 526                 bytes_written += 2;
 527                 words_remaining--;
 528                 address += 2;
 529         }
 530
 531         if (bytes_remaining) {
 532                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
 533                                 FLASH_PG | FLASH_PSIZE_8);
 534                 if (retval != ERROR_OK)
 535                         return retval;
 536                 retval = target_write_u8(target, address, buffer[bytes_written]);
 537                 if (retval != ERROR_OK)
 538                         return retval;
 539
 540                 retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
 541                 if (retval != ERROR_OK)
 542                         return retval;
 543         }
 544
 545         return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 546 }
 547
 548 static void setup_sector(struct flash_bank *bank, int start, int num, int size)
 549 {
 550         for (int i = start; i < (start + num) ; i++) {
 551                 bank->sectors[i].offset = bank->size;
 552                 bank->sectors[i].size = size;
 553                 bank->size += bank->sectors[i].size;
 554         }
 555 }
 556
 557 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 558 {
 559         /* this checks for a stm32f4x errata issue where a
 560          * stm32f2x DBGMCU_IDCODE is incorrectly returned.
 561          * If the issue is detected target is forced to stm32f4x Rev A.
 562          * Only effects Rev A silicon */
 563
 564         struct target *target = bank->target;
 565         uint32_t cpuid;
 566
 567         /* read stm32 device id register */
 568         int retval = target_read_u32(target, 0xE0042000, device_id);
 569         if (retval != ERROR_OK)
 570                 return retval;
 571
 572         if ((*device_id & 0xfff) == 0x411) {
 573                 /* read CPUID reg to check core type */
 574                 retval = target_read_u32(target, 0xE000ED00, &cpuid);
 575                 if (retval != ERROR_OK)
 576                         return retval;
 577
 578                 /* check for cortex_m4 */
 579                 if (((cpuid >> 4) & 0xFFF) == 0xC24) {
 580                         *device_id &= ~((0xFFFF << 16) | 0xfff);
 581                         *device_id |= (0x1000 << 16) | 0x413;
 582                         LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
 583                 }
 584         }
 585         return retval;
 586 }
 587
 588 static int stm32x_probe(struct flash_bank *bank)
 589 {
 590         struct target *target = bank->target;
 591         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 592         int i;
 593         uint16_t flash_size_in_kb;
 594         uint32_t device_id;
 595         uint32_t base_address = 0x08000000;
 596
 597         stm32x_info->probed = 0;
 598
 599         /* read stm32 device id register */
 600         int retval = stm32x_get_device_id(bank, &device_id);
 601         if (retval != ERROR_OK)
 602                 return retval;
 603         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 604
 605         /* get flash size from target. */
 606         retval = target_read_u16(target, 0x1FFF7A10, &flash_size_in_kb);
 607         if (retval != ERROR_OK) {
 608                 LOG_WARNING("failed reading flash size, default to max target family");
 609                 /* failed reading flash size, default to max target family */
 610                 flash_size_in_kb = 0xffff;
 611         }
 612
 613         if ((device_id & 0xfff) == 0x411) {
 614                 /* check for early silicon */
 615                 if (flash_size_in_kb == 0xffff) {
 616                         /* number of sectors may be incorrrect on early silicon */
 617                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
 618                         flash_size_in_kb = 1024;
 619                 }
 620         } else if ((device_id & 0xfff) == 0x413) {
 621                 /* check for early silicon */
 622                 if (flash_size_in_kb == 0xffff) {
 623                         /* number of sectors may be incorrrect on early silicon */
 624                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
 625                         flash_size_in_kb = 1024;
 626                 }
 627         } else {
 628                 LOG_WARNING("Cannot identify target as a STM32 family.");
 629                 return ERROR_FAIL;
 630         }
 631
 632         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 633
 634         /* did we assign flash size? */
 635         assert(flash_size_in_kb != 0xffff);
 636
 637         /* calculate numbers of pages */
 638         int num_pages = (flash_size_in_kb / 128) + 4;
 639
 640         /* check that calculation result makes sense */
 641         assert(num_pages > 0);
 642
 643         if (bank->sectors) {
 644                 free(bank->sectors);
 645                 bank->sectors = NULL;
 646         }
 647
 648         bank->base = base_address;
 649         bank->num_sectors = num_pages;
 650         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
 651         bank->size = 0;
 652
 653         /* fixed memory */
 654         setup_sector(bank, 0, 4, 16 * 1024);
 655         setup_sector(bank, 4, 1, 64 * 1024);
 656
 657         /* dynamic memory */
 658         setup_sector(bank, 4 + 1, num_pages - 5, 128 * 1024);
 659
 660         for (i = 0; i < num_pages; i++) {
 661                 bank->sectors[i].is_erased = -1;
 662                 bank->sectors[i].is_protected = 0;
 663         }
 664
 665         stm32x_info->probed = 1;
 666
 667         return ERROR_OK;
 668 }
 669
 670 static int stm32x_auto_probe(struct flash_bank *bank)
 671 {
 672         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 673         if (stm32x_info->probed)
 674                 return ERROR_OK;
 675         return stm32x_probe(bank);
 676 }
 677
 678 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
 679 {
 680         uint32_t device_id;
 681         int printed;
 682
 683         /* read stm32 device id register */
 684         int retval = stm32x_get_device_id(bank, &device_id);
 685         if (retval != ERROR_OK)
 686                 return retval;
 687
 688         if ((device_id & 0xfff) == 0x411) {
 689                 printed = snprintf(buf, buf_size, "stm32f2x - Rev: ");
 690                 buf += printed;
 691                 buf_size -= printed;
 692
 693                 switch (device_id >> 16) {
 694                         case 0x1000:
 695                                 snprintf(buf, buf_size, "A");
 696                                 break;
 697
 698                         case 0x2000:
 699                                 snprintf(buf, buf_size, "B");
 700                                 break;
 701
 702                         case 0x1001:
 703                                 snprintf(buf, buf_size, "Z");
 704                                 break;
 705
 706                         case 0x2001:
 707                                 snprintf(buf, buf_size, "Y");
 708                                 break;
 709
 710                         default:
 711                                 snprintf(buf, buf_size, "unknown");
 712                                 break;
 713                 }
 714         } else if ((device_id & 0xfff) == 0x413) {
 715                 printed = snprintf(buf, buf_size, "stm32f4x - Rev: ");
 716                 buf += printed;
 717                 buf_size -= printed;
 718
 719                 switch (device_id >> 16) {
 720                         case 0x1000:
 721                                 snprintf(buf, buf_size, "A");
 722                                 break;
 723
 724                         case 0x1001:
 725                                 snprintf(buf, buf_size, "Z");
 726                                 break;
 727
 728                         default:
 729                                 snprintf(buf, buf_size, "unknown");
 730                                 break;
 731                 }
 732         } else {
 733                 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
 734                 return ERROR_FAIL;
 735         }
 736
 737         return ERROR_OK;
 738 }
 739
 740 static int stm32x_mass_erase(struct flash_bank *bank)
 741 {
 742         int retval;
 743         struct target *target = bank->target;
 744
 745         if (target->state != TARGET_HALTED) {
 746                 LOG_ERROR("Target not halted");
 747                 return ERROR_TARGET_NOT_HALTED;
 748         }
 749
 750         retval = stm32x_unlock_reg(target);
 751         if (retval != ERROR_OK)
 752                 return retval;
 753
 754         /* mass erase flash memory */
 755         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
 756         if (retval != ERROR_OK)
 757                 return retval;
 758         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
 759                 FLASH_MER | FLASH_STRT);
 760         if (retval != ERROR_OK)
 761                 return retval;
 762
 763         retval = stm32x_wait_status_busy(bank, 30000);
 764         if (retval != ERROR_OK)
 765                 return retval;
 766
 767         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 768         if (retval != ERROR_OK)
 769                 return retval;
 770
 771         return ERROR_OK;
 772 }
 773
 774 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
 775 {
 776         int i;
 777
 778         if (CMD_ARGC < 1) {
 779                 command_print(CMD_CTX, "stm32x mass_erase <bank>");
 780                 return ERROR_COMMAND_SYNTAX_ERROR;
 781         }
 782
 783         struct flash_bank *bank;
 784         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 785         if (ERROR_OK != retval)
 786                 return retval;
 787
 788         retval = stm32x_mass_erase(bank);
 789         if (retval == ERROR_OK) {
 790                 /* set all sectors as erased */
 791                 for (i = 0; i < bank->num_sectors; i++)
 792                         bank->sectors[i].is_erased = 1;
 793
 794                 command_print(CMD_CTX, "stm32x mass erase complete");
 795         } else {
 796                 command_print(CMD_CTX, "stm32x mass erase failed");
 797         }
 798
 799         return retval;
 800 }
 801
 802 static const struct command_registration stm32x_exec_command_handlers[] = {
 803         {
 804                 .name = "mass_erase",
 805                 .handler = stm32x_handle_mass_erase_command,
 806                 .mode = COMMAND_EXEC,
 807                 .usage = "bank_id",
 808                 .help = "Erase entire flash device.",
 809         },
 810         COMMAND_REGISTRATION_DONE
 811 };
 812
 813 static const struct command_registration stm32x_command_handlers[] = {
 814         {
 815                 .name = "stm32f2x",
 816                 .mode = COMMAND_ANY,
 817                 .help = "stm32f2x flash command group",
 818                 .usage = "",
 819                 .chain = stm32x_exec_command_handlers,
 820         },
 821         COMMAND_REGISTRATION_DONE
 822 };
 823
 824 struct flash_driver stm32f2x_flash = {
 825         .name = "stm32f2x",
 826         .commands = stm32x_command_handlers,
 827         .flash_bank_command = stm32x_flash_bank_command,
 828         .erase = stm32x_erase,
 829         .protect = stm32x_protect,
 830         .write = stm32x_write,
 831         .read = default_flash_read,
 832         .probe = stm32x_probe,
 833         .auto_probe = stm32x_auto_probe,
 834         .erase_check = default_flash_mem_blank_check,
 835         .protect_check = stm32x_protect_check,
 836         .info = get_stm32x_info,
 837 };