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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "imp.h"
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34 #include <target/armv7m.h>
  35
  36 /* stm32x register locations */
  37
  38 #define FLASH_REG_BASE_B0 0x40022000
  39 #define FLASH_REG_BASE_B1 0x40022040
  40
  41 #define STM32_FLASH_ACR     0x00
  42 #define STM32_FLASH_KEYR    0x04
  43 #define STM32_FLASH_OPTKEYR 0x08
  44 #define STM32_FLASH_SR      0x0C
  45 #define STM32_FLASH_CR      0x10
  46 #define STM32_FLASH_AR      0x14
  47 #define STM32_FLASH_OBR     0x1C
  48 #define STM32_FLASH_WRPR    0x20
  49
  50 /* TODO: Check if code using these really should be hard coded to bank 0.
  51  * There are valid cases, on dual flash devices the protection of the
  52  * second bank is done on the bank0 reg's. */
  53 #define STM32_FLASH_ACR_B0     0x40022000
  54 #define STM32_FLASH_KEYR_B0    0x40022004
  55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  56 #define STM32_FLASH_SR_B0      0x4002200C
  57 #define STM32_FLASH_CR_B0      0x40022010
  58 #define STM32_FLASH_AR_B0      0x40022014
  59 #define STM32_FLASH_OBR_B0     0x4002201C
  60 #define STM32_FLASH_WRPR_B0    0x40022020
  61
  62 /* option byte location */
  63
  64 #define STM32_OB_RDP            0x1FFFF800
  65 #define STM32_OB_USER           0x1FFFF802
  66 #define STM32_OB_DATA0          0x1FFFF804
  67 #define STM32_OB_DATA1          0x1FFFF806
  68 #define STM32_OB_WRP0           0x1FFFF808
  69 #define STM32_OB_WRP1           0x1FFFF80A
  70 #define STM32_OB_WRP2           0x1FFFF80C
  71 #define STM32_OB_WRP3           0x1FFFF80E
  72
  73 /* FLASH_CR register bits */
  74
  75 #define FLASH_PG                (1 << 0)
  76 #define FLASH_PER               (1 << 1)
  77 #define FLASH_MER               (1 << 2)
  78 #define FLASH_OPTPG             (1 << 4)
  79 #define FLASH_OPTER             (1 << 5)
  80 #define FLASH_STRT              (1 << 6)
  81 #define FLASH_LOCK              (1 << 7)
  82 #define FLASH_OPTWRE    (1 << 9)
  83
  84 /* FLASH_SR register bits */
  85
  86 #define FLASH_BSY               (1 << 0)
  87 #define FLASH_PGERR             (1 << 2)
  88 #define FLASH_WRPRTERR  (1 << 4)
  89 #define FLASH_EOP               (1 << 5)
  90
  91 /* STM32_FLASH_OBR bit definitions (reading) */
  92
  93 #define OPT_ERROR               0
  94 #define OPT_READOUT             1
  95 #define OPT_RDWDGSW             2
  96 #define OPT_RDRSTSTOP   3
  97 #define OPT_RDRSTSTDBY  4
  98 #define OPT_BFB2                5       /* dual flash bank only */
  99
 100 /* register unlock keys */
 101
 102 #define KEY1                    0x45670123
 103 #define KEY2                    0xCDEF89AB
 104
 105 struct stm32x_options {
 106         uint16_t RDP;
 107         uint16_t user_options;
 108         uint16_t protection[4];
 109 };
 110
 111 struct stm32x_flash_bank {
 112         struct stm32x_options option_bytes;
 113         struct working_area *write_algorithm;
 114         int ppage_size;
 115         int probed;
 116
 117         bool has_dual_banks;
 118         /* used to access dual flash bank stm32xl */
 119         uint32_t register_base;
 120 };
 121
 122 static int stm32x_mass_erase(struct flash_bank *bank);
 123 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
 124
 125 /* flash bank stm32x <base> <size> 0 0 <target#>
 126  */
 127 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 128 {
 129         struct stm32x_flash_bank *stm32x_info;
 130
 131         if (CMD_ARGC < 6)
 132                 return ERROR_COMMAND_SYNTAX_ERROR;
 133
 134         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 135
 136         bank->driver_priv = stm32x_info;
 137         stm32x_info->write_algorithm = NULL;
 138         stm32x_info->probed = 0;
 139         stm32x_info->has_dual_banks = false;
 140         stm32x_info->register_base = FLASH_REG_BASE_B0;
 141
 142         return ERROR_OK;
 143 }
 144
 145 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 146 {
 147         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 148         return reg + stm32x_info->register_base;
 149 }
 150
 151 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 152 {
 153         struct target *target = bank->target;
 154         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 155 }
 156
 157 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 158 {
 159         struct target *target = bank->target;
 160         uint32_t status;
 161         int retval = ERROR_OK;
 162
 163         /* wait for busy to clear */
 164         for (;;) {
 165                 retval = stm32x_get_flash_status(bank, &status);
 166                 if (retval != ERROR_OK)
 167                         return retval;
 168                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 169                 if ((status & FLASH_BSY) == 0)
 170                         break;
 171                 if (timeout-- <= 0) {
 172                         LOG_ERROR("timed out waiting for flash");
 173                         return ERROR_FAIL;
 174                 }
 175                 alive_sleep(1);
 176         }
 177
 178         if (status & FLASH_WRPRTERR) {
 179                 LOG_ERROR("stm32x device protected");
 180                 retval = ERROR_FAIL;
 181         }
 182
 183         if (status & FLASH_PGERR) {
 184                 LOG_ERROR("stm32x device programming failed");
 185                 retval = ERROR_FAIL;
 186         }
 187
 188         /* Clear but report errors */
 189         if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
 190                 /* If this operation fails, we ignore it and report the original
 191                  * retval
 192                  */
 193                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 194                                 FLASH_WRPRTERR | FLASH_PGERR);
 195         }
 196         return retval;
 197 }
 198
 199 int stm32x_check_operation_supported(struct flash_bank *bank)
 200 {
 201         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 202
 203         /* if we have a dual flash bank device then
 204          * we need to perform option byte stuff on bank0 only */
 205         if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
 206                 LOG_ERROR("Option Byte Operation's must use bank0");
 207                 return ERROR_FLASH_OPERATION_FAILED;
 208         }
 209
 210         return ERROR_OK;
 211 }
 212
 213 static int stm32x_read_options(struct flash_bank *bank)
 214 {
 215         uint32_t optiondata;
 216         struct stm32x_flash_bank *stm32x_info = NULL;
 217         struct target *target = bank->target;
 218
 219         stm32x_info = bank->driver_priv;
 220
 221         /* read current option bytes */
 222         int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
 223         if (retval != ERROR_OK)
 224                 return retval;
 225
 226         stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
 227         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 228
 229         if (optiondata & (1 << OPT_READOUT))
 230                 LOG_INFO("Device Security Bit Set");
 231
 232         /* each bit refers to a 4bank protection */
 233         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
 234         if (retval != ERROR_OK)
 235                 return retval;
 236
 237         stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
 238         stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
 239         stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
 240         stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
 241
 242         return ERROR_OK;
 243 }
 244
 245 static int stm32x_erase_options(struct flash_bank *bank)
 246 {
 247         struct stm32x_flash_bank *stm32x_info = NULL;
 248         struct target *target = bank->target;
 249
 250         stm32x_info = bank->driver_priv;
 251
 252         /* read current options */
 253         stm32x_read_options(bank);
 254
 255         /* unlock flash registers */
 256         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 257         if (retval != ERROR_OK)
 258                 return retval;
 259
 260         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 261         if (retval != ERROR_OK)
 262                 return retval;
 263
 264         /* unlock option flash registers */
 265         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 266         if (retval != ERROR_OK)
 267                 return retval;
 268         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 269         if (retval != ERROR_OK)
 270                 return retval;
 271
 272         /* erase option bytes */
 273         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 274         if (retval != ERROR_OK)
 275                 return retval;
 276         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 277         if (retval != ERROR_OK)
 278                 return retval;
 279
 280         retval = stm32x_wait_status_busy(bank, 10);
 281         if (retval != ERROR_OK)
 282                 return retval;
 283
 284         /* clear readout protection and complementary option bytes
 285          * this will also force a device unlock if set */
 286         stm32x_info->option_bytes.RDP = 0x5AA5;
 287
 288         return ERROR_OK;
 289 }
 290
 291 static int stm32x_write_options(struct flash_bank *bank)
 292 {
 293         struct stm32x_flash_bank *stm32x_info = NULL;
 294         struct target *target = bank->target;
 295
 296         stm32x_info = bank->driver_priv;
 297
 298         /* unlock flash registers */
 299         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 300         if (retval != ERROR_OK)
 301                 return retval;
 302         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 303         if (retval != ERROR_OK)
 304                 return retval;
 305
 306         /* unlock option flash registers */
 307         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 308         if (retval != ERROR_OK)
 309                 return retval;
 310         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 311         if (retval != ERROR_OK)
 312                 return retval;
 313
 314         /* program option bytes */
 315         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 316         if (retval != ERROR_OK)
 317                 return retval;
 318
 319         /* write user option byte */
 320         retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
 321         if (retval != ERROR_OK)
 322                 return retval;
 323
 324         retval = stm32x_wait_status_busy(bank, 10);
 325         if (retval != ERROR_OK)
 326                 return retval;
 327
 328         /* write protection byte 1 */
 329         retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
 330         if (retval != ERROR_OK)
 331                 return retval;
 332
 333         retval = stm32x_wait_status_busy(bank, 10);
 334         if (retval != ERROR_OK)
 335                 return retval;
 336
 337         /* write protection byte 2 */
 338         retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
 339         if (retval != ERROR_OK)
 340                 return retval;
 341
 342         retval = stm32x_wait_status_busy(bank, 10);
 343         if (retval != ERROR_OK)
 344                 return retval;
 345
 346         /* write protection byte 3 */
 347         retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
 348         if (retval != ERROR_OK)
 349                 return retval;
 350
 351         retval = stm32x_wait_status_busy(bank, 10);
 352         if (retval != ERROR_OK)
 353                 return retval;
 354
 355         /* write protection byte 4 */
 356         retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
 357         if (retval != ERROR_OK)
 358                 return retval;
 359
 360         retval = stm32x_wait_status_busy(bank, 10);
 361         if (retval != ERROR_OK)
 362                 return retval;
 363
 364         /* write readout protection bit */
 365         retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
 366         if (retval != ERROR_OK)
 367                 return retval;
 368
 369         retval = stm32x_wait_status_busy(bank, 10);
 370         if (retval != ERROR_OK)
 371                 return retval;
 372
 373         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 374         if (retval != ERROR_OK)
 375                 return retval;
 376
 377         return ERROR_OK;
 378 }
 379
 380 static int stm32x_protect_check(struct flash_bank *bank)
 381 {
 382         struct target *target = bank->target;
 383         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 384
 385         uint32_t protection;
 386         int i, s;
 387         int num_bits;
 388         int set;
 389
 390         if (target->state != TARGET_HALTED) {
 391                 LOG_ERROR("Target not halted");
 392                 return ERROR_TARGET_NOT_HALTED;
 393         }
 394
 395         int retval = stm32x_check_operation_supported(bank);
 396         if (ERROR_OK != retval)
 397                 return retval;
 398
 399         /* medium density - each bit refers to a 4bank protection
 400          * high density - each bit refers to a 2bank protection */
 401         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 402         if (retval != ERROR_OK)
 403                 return retval;
 404
 405         /* medium density - each protection bit is for 4 * 1K pages
 406          * high density - each protection bit is for 2 * 2K pages */
 407         num_bits = (bank->num_sectors / stm32x_info->ppage_size);
 408
 409         if (stm32x_info->ppage_size == 2) {
 410                 /* high density flash/connectivity line protection */
 411
 412                 set = 1;
 413
 414                 if (protection & (1 << 31))
 415                         set = 0;
 416
 417                 /* bit 31 controls sector 62 - 255 protection for high density
 418                  * bit 31 controls sector 62 - 127 protection for connectivity line */
 419                 for (s = 62; s < bank->num_sectors; s++)
 420                         bank->sectors[s].is_protected = set;
 421
 422                 if (bank->num_sectors > 61)
 423                         num_bits = 31;
 424
 425                 for (i = 0; i < num_bits; i++) {
 426                         set = 1;
 427
 428                         if (protection & (1 << i))
 429                                 set = 0;
 430
 431                         for (s = 0; s < stm32x_info->ppage_size; s++)
 432                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 433                 }
 434         } else {
 435                 /* low/medium density flash protection */
 436                 for (i = 0; i < num_bits; i++) {
 437                         set = 1;
 438
 439                         if (protection & (1 << i))
 440                                 set = 0;
 441
 442                         for (s = 0; s < stm32x_info->ppage_size; s++)
 443                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 444                 }
 445         }
 446
 447         return ERROR_OK;
 448 }
 449
 450 static int stm32x_erase(struct flash_bank *bank, int first, int last)
 451 {
 452         struct target *target = bank->target;
 453         int i;
 454
 455         if (bank->target->state != TARGET_HALTED) {
 456                 LOG_ERROR("Target not halted");
 457                 return ERROR_TARGET_NOT_HALTED;
 458         }
 459
 460         if ((first == 0) && (last == (bank->num_sectors - 1)))
 461                 return stm32x_mass_erase(bank);
 462
 463         /* unlock flash registers */
 464         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 465         if (retval != ERROR_OK)
 466                 return retval;
 467         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 468         if (retval != ERROR_OK)
 469                 return retval;
 470
 471         for (i = first; i <= last; i++) {
 472                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 473                 if (retval != ERROR_OK)
 474                         return retval;
 475                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 476                                 bank->base + bank->sectors[i].offset);
 477                 if (retval != ERROR_OK)
 478                         return retval;
 479                 retval = target_write_u32(target,
 480                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 481                 if (retval != ERROR_OK)
 482                         return retval;
 483
 484                 retval = stm32x_wait_status_busy(bank, 100);
 485                 if (retval != ERROR_OK)
 486                         return retval;
 487
 488                 bank->sectors[i].is_erased = 1;
 489         }
 490
 491         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 492         if (retval != ERROR_OK)
 493                 return retval;
 494
 495         return ERROR_OK;
 496 }
 497
 498 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
 499 {
 500         struct stm32x_flash_bank *stm32x_info = NULL;
 501         struct target *target = bank->target;
 502         uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 503         int i, reg, bit;
 504         int status;
 505         uint32_t protection;
 506
 507         stm32x_info = bank->driver_priv;
 508
 509         if (target->state != TARGET_HALTED) {
 510                 LOG_ERROR("Target not halted");
 511                 return ERROR_TARGET_NOT_HALTED;
 512         }
 513
 514         int retval = stm32x_check_operation_supported(bank);
 515         if (ERROR_OK != retval)
 516                 return retval;
 517
 518         if ((first % stm32x_info->ppage_size) != 0) {
 519                 LOG_WARNING("aligned start protect sector to a %d sector boundary",
 520                                 stm32x_info->ppage_size);
 521                 first = first - (first % stm32x_info->ppage_size);
 522         }
 523         if (((last + 1) % stm32x_info->ppage_size) != 0) {
 524                 LOG_WARNING("aligned end protect sector to a %d sector boundary",
 525                                 stm32x_info->ppage_size);
 526                 last++;
 527                 last = last - (last % stm32x_info->ppage_size);
 528                 last--;
 529         }
 530
 531         /* medium density - each bit refers to a 4bank protection
 532          * high density - each bit refers to a 2bank protection */
 533         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 534         if (retval != ERROR_OK)
 535                 return retval;
 536
 537         prot_reg[0] = (uint16_t)protection;
 538         prot_reg[1] = (uint16_t)(protection >> 8);
 539         prot_reg[2] = (uint16_t)(protection >> 16);
 540         prot_reg[3] = (uint16_t)(protection >> 24);
 541
 542         if (stm32x_info->ppage_size == 2) {
 543                 /* high density flash */
 544
 545                 /* bit 7 controls sector 62 - 255 protection */
 546                 if (last > 61) {
 547                         if (set)
 548                                 prot_reg[3] &= ~(1 << 7);
 549                         else
 550                                 prot_reg[3] |= (1 << 7);
 551                 }
 552
 553                 if (first > 61)
 554                         first = 62;
 555                 if (last > 61)
 556                         last = 61;
 557
 558                 for (i = first; i <= last; i++) {
 559                         reg = (i / stm32x_info->ppage_size) / 8;
 560                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 561
 562                         if (set)
 563                                 prot_reg[reg] &= ~(1 << bit);
 564                         else
 565                                 prot_reg[reg] |= (1 << bit);
 566                 }
 567         } else {
 568                 /* medium density flash */
 569                 for (i = first; i <= last; i++) {
 570                         reg = (i / stm32x_info->ppage_size) / 8;
 571                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 572
 573                         if (set)
 574                                 prot_reg[reg] &= ~(1 << bit);
 575                         else
 576                                 prot_reg[reg] |= (1 << bit);
 577                 }
 578         }
 579
 580         status = stm32x_erase_options(bank);
 581         if (status != ERROR_OK)
 582                 return status;
 583
 584         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 585         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 586         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 587         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 588
 589         return stm32x_write_options(bank);
 590 }
 591
 592 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 593                 uint32_t offset, uint32_t count)
 594 {
 595         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 596         struct target *target = bank->target;
 597         uint32_t buffer_size = 16384;
 598         struct working_area *source;
 599         uint32_t address = bank->base + offset;
 600         struct reg_param reg_params[5];
 601         struct armv7m_algorithm armv7m_info;
 602         int retval = ERROR_OK;
 603
 604         /* see contrib/loaders/flash/stm32f1x.S for src */
 605
 606         static const uint8_t stm32x_flash_write_code[] = {
 607                 /* #define STM32_FLASH_SR_OFFSET 0x0C */
 608                 /* wait_fifo: */
 609                         0x16, 0x68,   /* ldr   r6, [r2, #0] */
 610                         0x00, 0x2e,   /* cmp   r6, #0 */
 611                         0x18, 0xd0,   /* beq   exit */
 612                         0x55, 0x68,   /* ldr   r5, [r2, #4] */
 613                         0xb5, 0x42,   /* cmp   r5, r6 */
 614                         0xf9, 0xd0,   /* beq   wait_fifo */
 615                         0x2e, 0x88,   /* ldrh  r6, [r5, #0] */
 616                         0x26, 0x80,   /* strh  r6, [r4, #0] */
 617                         0x02, 0x35,   /* adds  r5, #2 */
 618                         0x02, 0x34,   /* adds  r4, #2 */
 619                 /* busy: */
 620                         0xc6, 0x68,   /* ldr   r6, [r0, #STM32_FLASH_SR_OFFSET] */
 621                         0x01, 0x27,   /* movs  r7, #1 */
 622                         0x3e, 0x42,   /* tst   r6, r7 */
 623                         0xfb, 0xd1,   /* bne   busy */
 624                         0x14, 0x27,   /* movs  r7, #0x14 */
 625                         0x3e, 0x42,   /* tst   r6, r7 */
 626                         0x08, 0xd1,   /* bne   error */
 627                         0x9d, 0x42,   /* cmp   r5, r3 */
 628                         0x01, 0xd3,   /* bcc   no_wrap */
 629                         0x15, 0x46,   /* mov   r5, r2 */
 630                         0x08, 0x35,   /* adds  r5, #8 */
 631                 /* no_wrap: */
 632                         0x55, 0x60,   /* str   r5, [r2, #4] */
 633                         0x01, 0x39,   /* subs  r1, r1, #1 */
 634                         0x00, 0x29,   /* cmp   r1, #0 */
 635                         0x02, 0xd0,   /* beq   exit */
 636                         0xe5, 0xe7,   /* b     wait_fifo */
 637                 /* error: */
 638                         0x00, 0x20,   /* movs  r0, #0 */
 639                         0x50, 0x60,   /* str   r0, [r2, #4] */
 640                 /* exit: */
 641                         0x30, 0x46,   /* mov   r0, r6 */
 642                         0x00, 0xbe,   /* bkpt  #0 */
 643         };
 644
 645         /* flash write code */
 646         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 647                         &stm32x_info->write_algorithm) != ERROR_OK) {
 648                 LOG_WARNING("no working area available, can't do block memory writes");
 649                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 650         };
 651
 652         retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
 653                         sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
 654         if (retval != ERROR_OK)
 655                 return retval;
 656
 657         /* memory buffer */
 658         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 659                 buffer_size /= 2;
 660                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 661                 if (buffer_size <= 256) {
 662                         /* if we already allocated the writing code, but failed to get a
 663                          * buffer, free the algorithm */
 664                         if (stm32x_info->write_algorithm)
 665                                 target_free_working_area(target, stm32x_info->write_algorithm);
 666
 667                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 668                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 669                 }
 670         };
 671
 672         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 673         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 674         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 675         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 676         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 677
 678         buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
 679         buf_set_u32(reg_params[1].value, 0, 32, count);
 680         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 681         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 682         buf_set_u32(reg_params[4].value, 0, 32, address);
 683
 684         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 685         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 686
 687         retval = target_run_flash_async_algorithm(target, buffer, count, 2,
 688                         0, NULL,
 689                         5, reg_params,
 690                         source->address, source->size,
 691                         stm32x_info->write_algorithm->address, 0,
 692                         &armv7m_info);
 693
 694         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 695                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 696                                 buf_get_u32(reg_params[4].value, 0, 32));
 697
 698                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
 699                         LOG_ERROR("flash memory not erased before writing");
 700                         /* Clear but report errors */
 701                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
 702                 }
 703
 704                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
 705                         LOG_ERROR("flash memory write protected");
 706                         /* Clear but report errors */
 707                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
 708                 }
 709         }
 710
 711         target_free_working_area(target, source);
 712         target_free_working_area(target, stm32x_info->write_algorithm);
 713
 714         destroy_reg_param(&reg_params[0]);
 715         destroy_reg_param(&reg_params[1]);
 716         destroy_reg_param(&reg_params[2]);
 717         destroy_reg_param(&reg_params[3]);
 718         destroy_reg_param(&reg_params[4]);
 719
 720         return retval;
 721 }
 722
 723 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
 724                 uint32_t offset, uint32_t count)
 725 {
 726         struct target *target = bank->target;
 727         uint8_t *new_buffer = NULL;
 728
 729         if (bank->target->state != TARGET_HALTED) {
 730                 LOG_ERROR("Target not halted");
 731                 return ERROR_TARGET_NOT_HALTED;
 732         }
 733
 734         if (offset & 0x1) {
 735                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 736                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 737         }
 738
 739         /* If there's an odd number of bytes, the data has to be padded. Duplicate
 740          * the buffer and use the normal code path with a single block write since
 741          * it's probably cheaper than to special case the last odd write using
 742          * discrete accesses. */
 743         if (count & 1) {
 744                 new_buffer = malloc(count + 1);
 745                 if (new_buffer == NULL) {
 746                         LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
 747                         return ERROR_FAIL;
 748                 }
 749                 LOG_INFO("odd number of bytes to write, padding with 0xff");
 750                 buffer = memcpy(new_buffer, buffer, count);
 751                 buffer[count++] = 0xff;
 752         }
 753
 754         uint32_t words_remaining = count / 2;
 755         int retval, retval2;
 756
 757         /* unlock flash registers */
 758         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 759         if (retval != ERROR_OK)
 760                 goto cleanup;
 761         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 762         if (retval != ERROR_OK)
 763                 goto cleanup;
 764
 765         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 766         if (retval != ERROR_OK)
 767                 goto cleanup;
 768
 769         /* try using a block write */
 770         retval = stm32x_write_block(bank, buffer, offset, words_remaining);
 771
 772         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 773                 /* if block write failed (no sufficient working area),
 774                  * we use normal (slow) single halfword accesses */
 775                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 776
 777                 while (words_remaining > 0) {
 778                         uint16_t value;
 779                         memcpy(&value, buffer, sizeof(uint16_t));
 780
 781                         retval = target_write_u16(target, bank->base + offset, value);
 782                         if (retval != ERROR_OK)
 783                                 goto reset_pg_and_lock;
 784
 785                         retval = stm32x_wait_status_busy(bank, 5);
 786                         if (retval != ERROR_OK)
 787                                 goto reset_pg_and_lock;
 788
 789                         words_remaining--;
 790                         buffer += 2;
 791                         offset += 2;
 792                 }
 793         }
 794
 795 reset_pg_and_lock:
 796         retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 797         if (retval == ERROR_OK)
 798                 retval = retval2;
 799
 800 cleanup:
 801         if (new_buffer)
 802                 free(new_buffer);
 803
 804         return retval;
 805 }
 806
 807 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 808 {
 809         /* This check the device CPUID core register to detect
 810          * the M0 from the M3 devices. */
 811
 812         struct target *target = bank->target;
 813         uint32_t cpuid, device_id_register = 0;
 814
 815         /* Get the CPUID from the ARM Core
 816          * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
 817         int retval = target_read_u32(target, 0xE000ED00, &cpuid);
 818         if (retval != ERROR_OK)
 819                 return retval;
 820
 821         if (((cpuid >> 4) & 0xFFF) == 0xC20) {
 822                 /* 0xC20 is M0 devices */
 823                 device_id_register = 0x40015800;
 824         } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
 825                 /* 0xC23 is M3 devices */
 826                 device_id_register = 0xE0042000;
 827         } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
 828                 /* 0xC24 is M4 devices */
 829                 device_id_register = 0xE0042000;
 830         } else {
 831                 LOG_ERROR("Cannot identify target as a stm32x");
 832                 return ERROR_FAIL;
 833         }
 834
 835         /* read stm32 device id register */
 836         retval = target_read_u32(target, device_id_register, device_id);
 837         if (retval != ERROR_OK)
 838                 return retval;
 839
 840         return retval;
 841 }
 842
 843 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
 844 {
 845         struct target *target = bank->target;
 846         uint32_t cpuid, flash_size_reg;
 847
 848         int retval = target_read_u32(target, 0xE000ED00, &cpuid);
 849         if (retval != ERROR_OK)
 850                 return retval;
 851
 852         if (((cpuid >> 4) & 0xFFF) == 0xC20) {
 853                 /* 0xC20 is M0 devices */
 854                 flash_size_reg = 0x1FFFF7CC;
 855         } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
 856                 /* 0xC23 is M3 devices */
 857                 flash_size_reg = 0x1FFFF7E0;
 858         } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
 859                 /* 0xC24 is M4 devices */
 860                 flash_size_reg = 0x1FFFF7CC;
 861         } else {
 862                 LOG_ERROR("Cannot identify target as a stm32x");
 863                 return ERROR_FAIL;
 864         }
 865
 866         retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
 867         if (retval != ERROR_OK)
 868                 return retval;
 869
 870         return retval;
 871 }
 872
 873 static int stm32x_probe(struct flash_bank *bank)
 874 {
 875         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 876         int i;
 877         uint16_t flash_size_in_kb;
 878         uint16_t max_flash_size_in_kb;
 879         uint32_t device_id;
 880         int page_size;
 881         uint32_t base_address = 0x08000000;
 882
 883         stm32x_info->probed = 0;
 884         stm32x_info->register_base = FLASH_REG_BASE_B0;
 885
 886         /* read stm32 device id register */
 887         int retval = stm32x_get_device_id(bank, &device_id);
 888         if (retval != ERROR_OK)
 889                 return retval;
 890
 891         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 892
 893         /* set page size, protection granularity and max flash size depending on family */
 894         switch (device_id & 0xfff) {
 895         case 0x410: /* medium density */
 896                 page_size = 1024;
 897                 stm32x_info->ppage_size = 4;
 898                 max_flash_size_in_kb = 128;
 899                 break;
 900         case 0x412: /* low density */
 901                 page_size = 1024;
 902                 stm32x_info->ppage_size = 4;
 903                 max_flash_size_in_kb = 32;
 904                 break;
 905         case 0x414: /* high density */
 906                 page_size = 2048;
 907                 stm32x_info->ppage_size = 2;
 908                 max_flash_size_in_kb = 512;
 909                 break;
 910         case 0x418: /* connectivity line density */
 911                 page_size = 2048;
 912                 stm32x_info->ppage_size = 2;
 913                 max_flash_size_in_kb = 256;
 914                 break;
 915         case 0x420: /* value line density */
 916                 page_size = 1024;
 917                 stm32x_info->ppage_size = 4;
 918                 max_flash_size_in_kb = 128;
 919                 break;
 920         case 0x422: /* stm32f30x */
 921                 page_size = 2048;
 922                 stm32x_info->ppage_size = 2;
 923                 max_flash_size_in_kb = 256;
 924                 break;
 925         case 0x428: /* value line High density */
 926                 page_size = 2048;
 927                 stm32x_info->ppage_size = 4;
 928                 max_flash_size_in_kb = 128;
 929                 break;
 930         case 0x430: /* xl line density (dual flash banks) */
 931                 page_size = 2048;
 932                 stm32x_info->ppage_size = 2;
 933                 max_flash_size_in_kb = 1024;
 934                 stm32x_info->has_dual_banks = true;
 935                 break;
 936         case 0x432: /* stm32f37x */
 937                 page_size = 2048;
 938                 stm32x_info->ppage_size = 2;
 939                 max_flash_size_in_kb = 256;
 940                 break;
 941         case 0x440: /* stm32f0x */
 942                 page_size = 1024;
 943                 stm32x_info->ppage_size = 4;
 944                 max_flash_size_in_kb = 64;
 945                 break;
 946         default:
 947                 LOG_WARNING("Cannot identify target as a STM32 family.");
 948                 return ERROR_FAIL;
 949         }
 950
 951         /* get flash size from target. */
 952         retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
 953
 954         /* failed reading flash size or flash size invalid (early silicon),
 955          * default to max target family */
 956         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 957                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 958                         max_flash_size_in_kb);
 959                 flash_size_in_kb = max_flash_size_in_kb;
 960         }
 961
 962         if (stm32x_info->has_dual_banks) {
 963                 /* split reported size into matching bank */
 964                 if (bank->base != 0x08080000) {
 965                         /* bank 0 will be fixed 512k */
 966                         flash_size_in_kb = 512;
 967                 } else {
 968                         flash_size_in_kb -= 512;
 969                         /* bank1 also uses a register offset */
 970                         stm32x_info->register_base = FLASH_REG_BASE_B1;
 971                         base_address = 0x08080000;
 972                 }
 973         }
 974
 975         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 976
 977         /* did we assign flash size? */
 978         assert(flash_size_in_kb != 0xffff);
 979
 980         /* calculate numbers of pages */
 981         int num_pages = flash_size_in_kb * 1024 / page_size;
 982
 983         /* check that calculation result makes sense */
 984         assert(num_pages > 0);
 985
 986         if (bank->sectors) {
 987                 free(bank->sectors);
 988                 bank->sectors = NULL;
 989         }
 990
 991         bank->base = base_address;
 992         bank->size = (num_pages * page_size);
 993         bank->num_sectors = num_pages;
 994         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
 995
 996         for (i = 0; i < num_pages; i++) {
 997                 bank->sectors[i].offset = i * page_size;
 998                 bank->sectors[i].size = page_size;
 999                 bank->sectors[i].is_erased = -1;
1000                 bank->sectors[i].is_protected = 1;
1001         }
1002
1003         stm32x_info->probed = 1;
1004
1005         return ERROR_OK;
1006 }
1007
1008 static int stm32x_auto_probe(struct flash_bank *bank)
1009 {
1010         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1011         if (stm32x_info->probed)
1012                 return ERROR_OK;
1013         return stm32x_probe(bank);
1014 }
1015
1016 #if 0
1017 COMMAND_HANDLER(stm32x_handle_part_id_command)
1018 {
1019         return ERROR_OK;
1020 }
1021 #endif
1022
1023 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1024 {
1025         uint32_t device_id;
1026         int printed;
1027
1028                 /* read stm32 device id register */
1029         int retval = stm32x_get_device_id(bank, &device_id);
1030         if (retval != ERROR_OK)
1031                 return retval;
1032
1033         if ((device_id & 0xfff) == 0x410) {
1034                 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1035                 buf += printed;
1036                 buf_size -= printed;
1037
1038                 switch (device_id >> 16) {
1039                         case 0x0000:
1040                                 snprintf(buf, buf_size, "A");
1041                                 break;
1042
1043                         case 0x2000:
1044                                 snprintf(buf, buf_size, "B");
1045                                 break;
1046
1047                         case 0x2001:
1048                                 snprintf(buf, buf_size, "Z");
1049                                 break;
1050
1051                         case 0x2003:
1052                                 snprintf(buf, buf_size, "Y");
1053                                 break;
1054
1055                         default:
1056                                 snprintf(buf, buf_size, "unknown");
1057                                 break;
1058                 }
1059         } else if ((device_id & 0xfff) == 0x412) {
1060                 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1061                 buf += printed;
1062                 buf_size -= printed;
1063
1064                 switch (device_id >> 16) {
1065                         case 0x1000:
1066                                 snprintf(buf, buf_size, "A");
1067                                 break;
1068
1069                         default:
1070                                 snprintf(buf, buf_size, "unknown");
1071                                 break;
1072                 }
1073         } else if ((device_id & 0xfff) == 0x414) {
1074                 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1075                 buf += printed;
1076                 buf_size -= printed;
1077
1078                 switch (device_id >> 16) {
1079                         case 0x1000:
1080                                 snprintf(buf, buf_size, "A");
1081                                 break;
1082
1083                         case 0x1001:
1084                                 snprintf(buf, buf_size, "Z");
1085                                 break;
1086
1087                         default:
1088                                 snprintf(buf, buf_size, "unknown");
1089                                 break;
1090                 }
1091         } else if ((device_id & 0xfff) == 0x418) {
1092                 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1093                 buf += printed;
1094                 buf_size -= printed;
1095
1096                 switch (device_id >> 16) {
1097                         case 0x1000:
1098                                 snprintf(buf, buf_size, "A");
1099                                 break;
1100
1101                         case 0x1001:
1102                                 snprintf(buf, buf_size, "Z");
1103                                 break;
1104
1105                         default:
1106                                 snprintf(buf, buf_size, "unknown");
1107                                 break;
1108                 }
1109         } else if ((device_id & 0xfff) == 0x420) {
1110                 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1111                 buf += printed;
1112                 buf_size -= printed;
1113
1114                 switch (device_id >> 16) {
1115                         case 0x1000:
1116                                 snprintf(buf, buf_size, "A");
1117                                 break;
1118
1119                         case 0x1001:
1120                                 snprintf(buf, buf_size, "Z");
1121                                 break;
1122
1123                         default:
1124                                 snprintf(buf, buf_size, "unknown");
1125                                 break;
1126                 }
1127         } else if ((device_id & 0xfff) == 0x422) {
1128                 printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
1129                 buf += printed;
1130                 buf_size -= printed;
1131
1132                 switch (device_id >> 16) {
1133                         case 0x1000:
1134                                 snprintf(buf, buf_size, "1.0");
1135                                 break;
1136
1137                         default:
1138                                 snprintf(buf, buf_size, "unknown");
1139                                 break;
1140                 }
1141         } else if ((device_id & 0xfff) == 0x428) {
1142                 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1143                 buf += printed;
1144                 buf_size -= printed;
1145
1146                 switch (device_id >> 16) {
1147                         case 0x1000:
1148                                 snprintf(buf, buf_size, "A");
1149                                 break;
1150
1151                         case 0x1001:
1152                                 snprintf(buf, buf_size, "Z");
1153                                 break;
1154
1155                         default:
1156                                 snprintf(buf, buf_size, "unknown");
1157                                 break;
1158                 }
1159         } else if ((device_id & 0xfff) == 0x430) {
1160                 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1161                 buf += printed;
1162                 buf_size -= printed;
1163
1164                 switch (device_id >> 16) {
1165                         case 0x1000:
1166                                 snprintf(buf, buf_size, "A");
1167                                 break;
1168
1169                         default:
1170                                 snprintf(buf, buf_size, "unknown");
1171                                 break;
1172                 }
1173         } else if ((device_id & 0xfff) == 0x432) {
1174                 printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
1175                 buf += printed;
1176                 buf_size -= printed;
1177
1178                 switch (device_id >> 16) {
1179                         case 0x1000:
1180                                 snprintf(buf, buf_size, "1.0");
1181                                 break;
1182
1183                         default:
1184                                 snprintf(buf, buf_size, "unknown");
1185                                 break;
1186                 }
1187         } else if ((device_id & 0xfff) == 0x440) {
1188                 printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
1189                 buf += printed;
1190                 buf_size -= printed;
1191
1192                 switch (device_id >> 16) {
1193                         case 0x1000:
1194                                 snprintf(buf, buf_size, "1.0");
1195                                 break;
1196
1197                         case 0x2000:
1198                                 snprintf(buf, buf_size, "2.0");
1199                                 break;
1200
1201                         default:
1202                                 snprintf(buf, buf_size, "unknown");
1203                                 break;
1204                 }
1205         } else {
1206                 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1207                 return ERROR_FAIL;
1208         }
1209
1210         return ERROR_OK;
1211 }
1212
1213 COMMAND_HANDLER(stm32x_handle_lock_command)
1214 {
1215         struct target *target = NULL;
1216         struct stm32x_flash_bank *stm32x_info = NULL;
1217
1218         if (CMD_ARGC < 1)
1219                 return ERROR_COMMAND_SYNTAX_ERROR;
1220
1221         struct flash_bank *bank;
1222         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1223         if (ERROR_OK != retval)
1224                 return retval;
1225
1226         stm32x_info = bank->driver_priv;
1227
1228         target = bank->target;
1229
1230         if (target->state != TARGET_HALTED) {
1231                 LOG_ERROR("Target not halted");
1232                 return ERROR_TARGET_NOT_HALTED;
1233         }
1234
1235         retval = stm32x_check_operation_supported(bank);
1236         if (ERROR_OK != retval)
1237                 return retval;
1238
1239         if (stm32x_erase_options(bank) != ERROR_OK) {
1240                 command_print(CMD_CTX, "stm32x failed to erase options");
1241                 return ERROR_OK;
1242         }
1243
1244         /* set readout protection */
1245         stm32x_info->option_bytes.RDP = 0;
1246
1247         if (stm32x_write_options(bank) != ERROR_OK) {
1248                 command_print(CMD_CTX, "stm32x failed to lock device");
1249                 return ERROR_OK;
1250         }
1251
1252         command_print(CMD_CTX, "stm32x locked");
1253
1254         return ERROR_OK;
1255 }
1256
1257 COMMAND_HANDLER(stm32x_handle_unlock_command)
1258 {
1259         struct target *target = NULL;
1260
1261         if (CMD_ARGC < 1)
1262                 return ERROR_COMMAND_SYNTAX_ERROR;
1263
1264         struct flash_bank *bank;
1265         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1266         if (ERROR_OK != retval)
1267                 return retval;
1268
1269         target = bank->target;
1270
1271         if (target->state != TARGET_HALTED) {
1272                 LOG_ERROR("Target not halted");
1273                 return ERROR_TARGET_NOT_HALTED;
1274         }
1275
1276         retval = stm32x_check_operation_supported(bank);
1277         if (ERROR_OK != retval)
1278                 return retval;
1279
1280         if (stm32x_erase_options(bank) != ERROR_OK) {
1281                 command_print(CMD_CTX, "stm32x failed to unlock device");
1282                 return ERROR_OK;
1283         }
1284
1285         if (stm32x_write_options(bank) != ERROR_OK) {
1286                 command_print(CMD_CTX, "stm32x failed to lock device");
1287                 return ERROR_OK;
1288         }
1289
1290         command_print(CMD_CTX, "stm32x unlocked.\n"
1291                         "INFO: a reset or power cycle is required "
1292                         "for the new settings to take effect.");
1293
1294         return ERROR_OK;
1295 }
1296
1297 COMMAND_HANDLER(stm32x_handle_options_read_command)
1298 {
1299         uint32_t optionbyte;
1300         struct target *target = NULL;
1301         struct stm32x_flash_bank *stm32x_info = NULL;
1302
1303         if (CMD_ARGC < 1)
1304                 return ERROR_COMMAND_SYNTAX_ERROR;
1305
1306         struct flash_bank *bank;
1307         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1308         if (ERROR_OK != retval)
1309                 return retval;
1310
1311         stm32x_info = bank->driver_priv;
1312
1313         target = bank->target;
1314
1315         if (target->state != TARGET_HALTED) {
1316                 LOG_ERROR("Target not halted");
1317                 return ERROR_TARGET_NOT_HALTED;
1318         }
1319
1320         retval = stm32x_check_operation_supported(bank);
1321         if (ERROR_OK != retval)
1322                 return retval;
1323
1324         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1325         if (retval != ERROR_OK)
1326                 return retval;
1327         command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1328
1329         if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
1330                 command_print(CMD_CTX, "Option Byte Complement Error");
1331
1332         if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
1333                 command_print(CMD_CTX, "Readout Protection On");
1334         else
1335                 command_print(CMD_CTX, "Readout Protection Off");
1336
1337         if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
1338                 command_print(CMD_CTX, "Software Watchdog");
1339         else
1340                 command_print(CMD_CTX, "Hardware Watchdog");
1341
1342         if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
1343                 command_print(CMD_CTX, "Stop: No reset generated");
1344         else
1345                 command_print(CMD_CTX, "Stop: Reset generated");
1346
1347         if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
1348                 command_print(CMD_CTX, "Standby: No reset generated");
1349         else
1350                 command_print(CMD_CTX, "Standby: Reset generated");
1351
1352         if (stm32x_info->has_dual_banks) {
1353                 if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
1354                         command_print(CMD_CTX, "Boot: Bank 0");
1355                 else
1356                         command_print(CMD_CTX, "Boot: Bank 1");
1357         }
1358
1359         return ERROR_OK;
1360 }
1361
1362 COMMAND_HANDLER(stm32x_handle_options_write_command)
1363 {
1364         struct target *target = NULL;
1365         struct stm32x_flash_bank *stm32x_info = NULL;
1366         uint16_t optionbyte = 0xF8;
1367
1368         if (CMD_ARGC < 4)
1369                 return ERROR_COMMAND_SYNTAX_ERROR;
1370
1371         struct flash_bank *bank;
1372         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1373         if (ERROR_OK != retval)
1374                 return retval;
1375
1376         stm32x_info = bank->driver_priv;
1377
1378         target = bank->target;
1379
1380         if (target->state != TARGET_HALTED) {
1381                 LOG_ERROR("Target not halted");
1382                 return ERROR_TARGET_NOT_HALTED;
1383         }
1384
1385         retval = stm32x_check_operation_supported(bank);
1386         if (ERROR_OK != retval)
1387                 return retval;
1388
1389         /* REVISIT: ignores some options which we will display...
1390          * and doesn't insist on the specified syntax.
1391          */
1392
1393         /* OPT_RDWDGSW */
1394         if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1395                 optionbyte |= (1 << 0);
1396         else    /* REVISIT must be "HWWDG" then ... */
1397                 optionbyte &= ~(1 << 0);
1398
1399         /* OPT_RDRSTSTOP */
1400         if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
1401                 optionbyte |= (1 << 1);
1402         else    /* REVISIT must be "RSTSTNDBY" then ... */
1403                 optionbyte &= ~(1 << 1);
1404
1405         /* OPT_RDRSTSTDBY */
1406         if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
1407                 optionbyte |= (1 << 2);
1408         else    /* REVISIT must be "RSTSTOP" then ... */
1409                 optionbyte &= ~(1 << 2);
1410
1411         if (CMD_ARGC > 4 && stm32x_info->has_dual_banks) {
1412                 /* OPT_BFB2 */
1413                 if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
1414                         optionbyte |= (1 << 3);
1415                 else
1416                         optionbyte &= ~(1 << 3);
1417         }
1418
1419         if (stm32x_erase_options(bank) != ERROR_OK) {
1420                 command_print(CMD_CTX, "stm32x failed to erase options");
1421                 return ERROR_OK;
1422         }
1423
1424         stm32x_info->option_bytes.user_options = optionbyte;
1425
1426         if (stm32x_write_options(bank) != ERROR_OK) {
1427                 command_print(CMD_CTX, "stm32x failed to write options");
1428                 return ERROR_OK;
1429         }
1430
1431         command_print(CMD_CTX, "stm32x write options complete.\n"
1432                                 "INFO: a reset or power cycle is required "
1433                                 "for the new settings to take effect.");
1434
1435         return ERROR_OK;
1436 }
1437
1438 static int stm32x_mass_erase(struct flash_bank *bank)
1439 {
1440         struct target *target = bank->target;
1441
1442         if (target->state != TARGET_HALTED) {
1443                 LOG_ERROR("Target not halted");
1444                 return ERROR_TARGET_NOT_HALTED;
1445         }
1446
1447         /* unlock option flash registers */
1448         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1449         if (retval != ERROR_OK)
1450                 return retval;
1451         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1452         if (retval != ERROR_OK)
1453                 return retval;
1454
1455         /* mass erase flash memory */
1456         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1457         if (retval != ERROR_OK)
1458                 return retval;
1459         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1460                         FLASH_MER | FLASH_STRT);
1461         if (retval != ERROR_OK)
1462                 return retval;
1463
1464         retval = stm32x_wait_status_busy(bank, 100);
1465         if (retval != ERROR_OK)
1466                 return retval;
1467
1468         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1469         if (retval != ERROR_OK)
1470                 return retval;
1471
1472         return ERROR_OK;
1473 }
1474
1475 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1476 {
1477         int i;
1478
1479         if (CMD_ARGC < 1)
1480                 return ERROR_COMMAND_SYNTAX_ERROR;
1481
1482         struct flash_bank *bank;
1483         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1484         if (ERROR_OK != retval)
1485                 return retval;
1486
1487         retval = stm32x_mass_erase(bank);
1488         if (retval == ERROR_OK) {
1489                 /* set all sectors as erased */
1490                 for (i = 0; i < bank->num_sectors; i++)
1491                         bank->sectors[i].is_erased = 1;
1492
1493                 command_print(CMD_CTX, "stm32x mass erase complete");
1494         } else
1495                 command_print(CMD_CTX, "stm32x mass erase failed");
1496
1497         return retval;
1498 }
1499
1500 static const struct command_registration stm32x_exec_command_handlers[] = {
1501         {
1502                 .name = "lock",
1503                 .handler = stm32x_handle_lock_command,
1504                 .mode = COMMAND_EXEC,
1505                 .usage = "bank_id",
1506                 .help = "Lock entire flash device.",
1507         },
1508         {
1509                 .name = "unlock",
1510                 .handler = stm32x_handle_unlock_command,
1511                 .mode = COMMAND_EXEC,
1512                 .usage = "bank_id",
1513                 .help = "Unlock entire protected flash device.",
1514         },
1515         {
1516                 .name = "mass_erase",
1517                 .handler = stm32x_handle_mass_erase_command,
1518                 .mode = COMMAND_EXEC,
1519                 .usage = "bank_id",
1520                 .help = "Erase entire flash device.",
1521         },
1522         {
1523                 .name = "options_read",
1524                 .handler = stm32x_handle_options_read_command,
1525                 .mode = COMMAND_EXEC,
1526                 .usage = "bank_id",
1527                 .help = "Read and display device option byte.",
1528         },
1529         {
1530                 .name = "options_write",
1531                 .handler = stm32x_handle_options_write_command,
1532                 .mode = COMMAND_EXEC,
1533                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1534                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1535                         "('RSTSTOP'|'NORSTSTOP')",
1536                 .help = "Replace bits in device option byte.",
1537         },
1538         COMMAND_REGISTRATION_DONE
1539 };
1540
1541 static const struct command_registration stm32x_command_handlers[] = {
1542         {
1543                 .name = "stm32f1x",
1544                 .mode = COMMAND_ANY,
1545                 .help = "stm32f1x flash command group",
1546                 .usage = "",
1547                 .chain = stm32x_exec_command_handlers,
1548         },
1549         COMMAND_REGISTRATION_DONE
1550 };
1551
1552 struct flash_driver stm32f1x_flash = {
1553         .name = "stm32f1x",
1554         .commands = stm32x_command_handlers,
1555         .flash_bank_command = stm32x_flash_bank_command,
1556         .erase = stm32x_erase,
1557         .protect = stm32x_protect,
1558         .write = stm32x_write,
1559         .read = default_flash_read,
1560         .probe = stm32x_probe,
1561         .auto_probe = stm32x_auto_probe,
1562         .erase_check = default_flash_blank_check,
1563         .protect_check = stm32x_protect_check,
1564         .info = get_stm32x_info,
1565 };