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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "imp.h"
  30 #include <helper/binarybuffer.h>
  31 #include <target/algorithm.h>
  32 #include <target/cortex_m.h>
  33
  34 /* stm32x register locations */
  35
  36 #define FLASH_REG_BASE_B0 0x40022000
  37 #define FLASH_REG_BASE_B1 0x40022040
  38
  39 #define STM32_FLASH_ACR     0x00
  40 #define STM32_FLASH_KEYR    0x04
  41 #define STM32_FLASH_OPTKEYR 0x08
  42 #define STM32_FLASH_SR      0x0C
  43 #define STM32_FLASH_CR      0x10
  44 #define STM32_FLASH_AR      0x14
  45 #define STM32_FLASH_OBR     0x1C
  46 #define STM32_FLASH_WRPR    0x20
  47
  48 /* TODO: Check if code using these really should be hard coded to bank 0.
  49  * There are valid cases, on dual flash devices the protection of the
  50  * second bank is done on the bank0 reg's. */
  51 #define STM32_FLASH_ACR_B0     0x40022000
  52 #define STM32_FLASH_KEYR_B0    0x40022004
  53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  54 #define STM32_FLASH_SR_B0      0x4002200C
  55 #define STM32_FLASH_CR_B0      0x40022010
  56 #define STM32_FLASH_AR_B0      0x40022014
  57 #define STM32_FLASH_OBR_B0     0x4002201C
  58 #define STM32_FLASH_WRPR_B0    0x40022020
  59
  60 /* option byte location */
  61
  62 #define STM32_OB_RDP            0x1FFFF800
  63 #define STM32_OB_USER           0x1FFFF802
  64 #define STM32_OB_DATA0          0x1FFFF804
  65 #define STM32_OB_DATA1          0x1FFFF806
  66 #define STM32_OB_WRP0           0x1FFFF808
  67 #define STM32_OB_WRP1           0x1FFFF80A
  68 #define STM32_OB_WRP2           0x1FFFF80C
  69 #define STM32_OB_WRP3           0x1FFFF80E
  70
  71 /* FLASH_CR register bits */
  72
  73 #define FLASH_PG                        (1 << 0)
  74 #define FLASH_PER                       (1 << 1)
  75 #define FLASH_MER                       (1 << 2)
  76 #define FLASH_OPTPG                     (1 << 4)
  77 #define FLASH_OPTER                     (1 << 5)
  78 #define FLASH_STRT                      (1 << 6)
  79 #define FLASH_LOCK                      (1 << 7)
  80 #define FLASH_OPTWRE            (1 << 9)
  81 #define FLASH_OBL_LAUNCH        (1 << 13)       /* except stm32f1x series */
  82
  83 /* FLASH_SR register bits */
  84
  85 #define FLASH_BSY               (1 << 0)
  86 #define FLASH_PGERR             (1 << 2)
  87 #define FLASH_WRPRTERR  (1 << 4)
  88 #define FLASH_EOP               (1 << 5)
  89
  90 /* STM32_FLASH_OBR bit definitions (reading) */
  91
  92 #define OPT_ERROR               0
  93 #define OPT_READOUT             1
  94 #define OPT_RDWDGSW             2
  95 #define OPT_RDRSTSTOP   3
  96 #define OPT_RDRSTSTDBY  4
  97 #define OPT_BFB2                5       /* dual flash bank only */
  98
  99 /* register unlock keys */
 100
 101 #define KEY1                    0x45670123
 102 #define KEY2                    0xCDEF89AB
 103
 104 /* timeout values */
 105
 106 #define FLASH_WRITE_TIMEOUT 10
 107 #define FLASH_ERASE_TIMEOUT 100
 108
 109 struct stm32x_options {
 110         uint8_t rdp;
 111         uint8_t user;
 112         uint16_t data;
 113         uint32_t protection;
 114 };
 115
 116 struct stm32x_flash_bank {
 117         struct stm32x_options option_bytes;
 118         int ppage_size;
 119         bool probed;
 120
 121         bool has_dual_banks;
 122         /* used to access dual flash bank stm32xl */
 123         bool can_load_options;
 124         uint32_t register_base;
 125         uint8_t default_rdp;
 126         int user_data_offset;
 127         int option_offset;
 128         uint32_t user_bank_size;
 129 };
 130
 131 static int stm32x_mass_erase(struct flash_bank *bank);
 132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
 133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 134                 uint32_t address, uint32_t hwords_count);
 135
 136 /* flash bank stm32x <base> <size> 0 0 <target#>
 137  */
 138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 139 {
 140         struct stm32x_flash_bank *stm32x_info;
 141
 142         if (CMD_ARGC < 6)
 143                 return ERROR_COMMAND_SYNTAX_ERROR;
 144
 145         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 146
 147         bank->driver_priv = stm32x_info;
 148         stm32x_info->probed = false;
 149         stm32x_info->has_dual_banks = false;
 150         stm32x_info->can_load_options = false;
 151         stm32x_info->register_base = FLASH_REG_BASE_B0;
 152         stm32x_info->user_bank_size = bank->size;
 153
 154         /* The flash write must be aligned to a halfword boundary */
 155         bank->write_start_alignment = bank->write_end_alignment = 2;
 156
 157         return ERROR_OK;
 158 }
 159
 160 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 161 {
 162         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 163         return reg + stm32x_info->register_base;
 164 }
 165
 166 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 167 {
 168         struct target *target = bank->target;
 169         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 170 }
 171
 172 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 173 {
 174         struct target *target = bank->target;
 175         uint32_t status;
 176         int retval = ERROR_OK;
 177
 178         /* wait for busy to clear */
 179         for (;;) {
 180                 retval = stm32x_get_flash_status(bank, &status);
 181                 if (retval != ERROR_OK)
 182                         return retval;
 183                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 184                 if ((status & FLASH_BSY) == 0)
 185                         break;
 186                 if (timeout-- <= 0) {
 187                         LOG_ERROR("timed out waiting for flash");
 188                         return ERROR_FLASH_BUSY;
 189                 }
 190                 alive_sleep(1);
 191         }
 192
 193         if (status & FLASH_WRPRTERR) {
 194                 LOG_ERROR("stm32x device protected");
 195                 retval = ERROR_FLASH_PROTECTED;
 196         }
 197
 198         if (status & FLASH_PGERR) {
 199                 LOG_ERROR("stm32x device programming failed / flash not erased");
 200                 retval = ERROR_FLASH_OPERATION_FAILED;
 201         }
 202
 203         /* Clear but report errors */
 204         if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
 205                 /* If this operation fails, we ignore it and report the original
 206                  * retval
 207                  */
 208                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 209                                 FLASH_WRPRTERR | FLASH_PGERR);
 210         }
 211         return retval;
 212 }
 213
 214 static int stm32x_check_operation_supported(struct flash_bank *bank)
 215 {
 216         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 217
 218         /* if we have a dual flash bank device then
 219          * we need to perform option byte stuff on bank0 only */
 220         if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
 221                 LOG_ERROR("Option byte operations must use bank 0");
 222                 return ERROR_FLASH_OPERATION_FAILED;
 223         }
 224
 225         return ERROR_OK;
 226 }
 227
 228 static int stm32x_read_options(struct flash_bank *bank)
 229 {
 230         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 231         struct target *target = bank->target;
 232         uint32_t option_bytes;
 233         int retval;
 234
 235         /* read user and read protection option bytes, user data option bytes */
 236         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
 237         if (retval != ERROR_OK)
 238                 return retval;
 239
 240         stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
 241         stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
 242         stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
 243
 244         /* read write protection option bytes */
 245         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
 246         if (retval != ERROR_OK)
 247                 return retval;
 248
 249         return ERROR_OK;
 250 }
 251
 252 static int stm32x_erase_options(struct flash_bank *bank)
 253 {
 254         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 255         struct target *target = bank->target;
 256
 257         /* read current options */
 258         stm32x_read_options(bank);
 259
 260         /* unlock flash registers */
 261         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 262         if (retval != ERROR_OK)
 263                 return retval;
 264
 265         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 266         if (retval != ERROR_OK)
 267                 return retval;
 268
 269         /* unlock option flash registers */
 270         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 271         if (retval != ERROR_OK)
 272                 return retval;
 273         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 274         if (retval != ERROR_OK)
 275                 return retval;
 276
 277         /* erase option bytes */
 278         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 279         if (retval != ERROR_OK)
 280                 return retval;
 281         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 282         if (retval != ERROR_OK)
 283                 return retval;
 284
 285         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 286         if (retval != ERROR_OK)
 287                 return retval;
 288
 289         /* clear read protection option byte
 290          * this will also force a device unlock if set */
 291         stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
 292
 293         return ERROR_OK;
 294 }
 295
 296 static int stm32x_write_options(struct flash_bank *bank)
 297 {
 298         struct stm32x_flash_bank *stm32x_info = NULL;
 299         struct target *target = bank->target;
 300
 301         stm32x_info = bank->driver_priv;
 302
 303         /* unlock flash registers */
 304         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 305         if (retval != ERROR_OK)
 306                 return retval;
 307         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 308         if (retval != ERROR_OK)
 309                 return retval;
 310
 311         /* unlock option flash registers */
 312         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 313         if (retval != ERROR_OK)
 314                 return retval;
 315         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 316         if (retval != ERROR_OK)
 317                 return retval;
 318
 319         /* program option bytes */
 320         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 321         if (retval != ERROR_OK)
 322                 return retval;
 323
 324         uint8_t opt_bytes[16];
 325
 326         target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
 327         target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
 328         target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
 329         target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
 330         target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
 331         target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
 332         target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
 333         target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
 334
 335         /* Block write is preferred in favour of operation with ancient ST-Link
 336          * firmwares without 16-bit memory access. See
 337          * 480: flash: stm32f1x: write option bytes using the loader
 338          * https://review.openocd.org/c/openocd/+/480
 339          */
 340         retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
 341         if (retval != ERROR_OK)
 342                 return retval;
 343
 344         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 345         if (retval != ERROR_OK)
 346                 return retval;
 347
 348         return ERROR_OK;
 349 }
 350
 351 static int stm32x_protect_check(struct flash_bank *bank)
 352 {
 353         struct target *target = bank->target;
 354         uint32_t protection;
 355
 356         int retval = stm32x_check_operation_supported(bank);
 357         if (retval != ERROR_OK)
 358                 return retval;
 359
 360         /* medium density - each bit refers to a 4 sector protection block
 361          * high density - each bit refers to a 2 sector protection block
 362          * bit 31 refers to all remaining sectors in a bank */
 363         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 364         if (retval != ERROR_OK)
 365                 return retval;
 366
 367         for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
 368                 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
 369
 370         return ERROR_OK;
 371 }
 372
 373 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
 374                 unsigned int last)
 375 {
 376         struct target *target = bank->target;
 377
 378         if (bank->target->state != TARGET_HALTED) {
 379                 LOG_ERROR("Target not halted");
 380                 return ERROR_TARGET_NOT_HALTED;
 381         }
 382
 383         if ((first == 0) && (last == (bank->num_sectors - 1)))
 384                 return stm32x_mass_erase(bank);
 385
 386         /* unlock flash registers */
 387         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 388         if (retval != ERROR_OK)
 389                 return retval;
 390         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 391         if (retval != ERROR_OK)
 392                 return retval;
 393
 394         for (unsigned int i = first; i <= last; i++) {
 395                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 396                 if (retval != ERROR_OK)
 397                         return retval;
 398                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 399                                 bank->base + bank->sectors[i].offset);
 400                 if (retval != ERROR_OK)
 401                         return retval;
 402                 retval = target_write_u32(target,
 403                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 404                 if (retval != ERROR_OK)
 405                         return retval;
 406
 407                 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 408                 if (retval != ERROR_OK)
 409                         return retval;
 410         }
 411
 412         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 413         if (retval != ERROR_OK)
 414                 return retval;
 415
 416         return ERROR_OK;
 417 }
 418
 419 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 420                 unsigned int last)
 421 {
 422         struct target *target = bank->target;
 423         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 424
 425         if (target->state != TARGET_HALTED) {
 426                 LOG_ERROR("Target not halted");
 427                 return ERROR_TARGET_NOT_HALTED;
 428         }
 429
 430         int retval = stm32x_check_operation_supported(bank);
 431         if (retval != ERROR_OK)
 432                 return retval;
 433
 434         retval = stm32x_erase_options(bank);
 435         if (retval != ERROR_OK) {
 436                 LOG_ERROR("stm32x failed to erase options");
 437                 return retval;
 438         }
 439
 440         for (unsigned int i = first; i <= last; i++) {
 441                 if (set)
 442                         stm32x_info->option_bytes.protection &= ~(1 << i);
 443                 else
 444                         stm32x_info->option_bytes.protection |= (1 << i);
 445         }
 446
 447         return stm32x_write_options(bank);
 448 }
 449
 450 static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buffer,
 451                 uint32_t address, uint32_t hwords_count)
 452 {
 453         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 454         struct target *target = bank->target;
 455         uint32_t buffer_size;
 456         struct working_area *write_algorithm;
 457         struct working_area *source;
 458         struct armv7m_algorithm armv7m_info;
 459         int retval;
 460
 461         static const uint8_t stm32x_flash_write_code[] = {
 462 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
 463         };
 464
 465         /* flash write code */
 466         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 467                         &write_algorithm) != ERROR_OK) {
 468                 LOG_WARNING("no working area available, can't do block memory writes");
 469                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 470         }
 471
 472         retval = target_write_buffer(target, write_algorithm->address,
 473                         sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
 474         if (retval != ERROR_OK) {
 475                 target_free_working_area(target, write_algorithm);
 476                 return retval;
 477         }
 478
 479         /* memory buffer */
 480         buffer_size = target_get_working_area_avail(target);
 481         buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256));
 482         /* Normally we allocate all available working area.
 483          * MIN shrinks buffer_size if the size of the written block is smaller.
 484          * MAX prevents using async algo if the available working area is smaller
 485          * than 256, the following allocation fails with
 486          * ERROR_TARGET_RESOURCE_NOT_AVAILABLE and slow flashing takes place.
 487          */
 488
 489         retval = target_alloc_working_area(target, buffer_size, &source);
 490         /* Allocated size is always 32-bit word aligned */
 491         if (retval != ERROR_OK) {
 492                 target_free_working_area(target, write_algorithm);
 493                 LOG_WARNING("no large enough working area available, can't do block memory writes");
 494                 /* target_alloc_working_area() may return ERROR_FAIL if area backup fails:
 495                  * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE
 496                  */
 497                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 498         }
 499
 500         struct reg_param reg_params[5];
 501
 502         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 503         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 504         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 505         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 506         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 507
 508         buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
 509         buf_set_u32(reg_params[1].value, 0, 32, hwords_count);
 510         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 511         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 512         buf_set_u32(reg_params[4].value, 0, 32, address);
 513
 514         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 515         armv7m_info.core_mode = ARM_MODE_THREAD;
 516
 517         retval = target_run_flash_async_algorithm(target, buffer, hwords_count, 2,
 518                         0, NULL,
 519                         ARRAY_SIZE(reg_params), reg_params,
 520                         source->address, source->size,
 521                         write_algorithm->address, 0,
 522                         &armv7m_info);
 523
 524         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 525                 /* Actually we just need to check for programming errors
 526                  * stm32x_wait_status_busy also reports error and clears status bits.
 527                  *
 528                  * Target algo returns flash status in r0 only if properly finished.
 529                  * It is safer to re-read status register.
 530                  */
 531                 int retval2 = stm32x_wait_status_busy(bank, 5);
 532                 if (retval2 != ERROR_OK)
 533                         retval = retval2;
 534
 535                 LOG_ERROR("flash write failed just before address 0x%"PRIx32,
 536                                 buf_get_u32(reg_params[4].value, 0, 32));
 537         }
 538
 539         for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++)
 540                 destroy_reg_param(&reg_params[i]);
 541
 542         target_free_working_area(target, source);
 543         target_free_working_area(target, write_algorithm);
 544
 545         return retval;
 546 }
 547
 548 /** Writes a block to flash either using target algorithm
 549  *  or use fallback, host controlled halfword-by-halfword access.
 550  *  Flash controller must be unlocked before this call.
 551  */
 552 static int stm32x_write_block(struct flash_bank *bank,
 553                 const uint8_t *buffer, uint32_t address, uint32_t hwords_count)
 554 {
 555         struct target *target = bank->target;
 556
 557         /* The flash write must be aligned to a halfword boundary.
 558          * The flash infrastructure ensures it, do just a security check
 559          */
 560         assert(address % 2 == 0);
 561
 562         /* try using a block write - on ARM architecture or... */
 563         int retval = stm32x_write_block_async(bank, buffer, address, hwords_count);
 564
 565         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 566                 /* if block write failed (no sufficient working area),
 567                  * we use normal (slow) single halfword accesses */
 568                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 569
 570                 while (hwords_count > 0) {
 571                         retval = target_write_memory(target, address, 2, 1, buffer);
 572                         if (retval != ERROR_OK)
 573                                 return retval;
 574
 575                         retval = stm32x_wait_status_busy(bank, 5);
 576                         if (retval != ERROR_OK)
 577                                 return retval;
 578
 579                         hwords_count--;
 580                         buffer += 2;
 581                         address += 2;
 582                 }
 583         }
 584         return retval;
 585 }
 586
 587 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 588                 uint32_t offset, uint32_t count)
 589 {
 590         struct target *target = bank->target;
 591
 592         if (bank->target->state != TARGET_HALTED) {
 593                 LOG_ERROR("Target not halted");
 594                 return ERROR_TARGET_NOT_HALTED;
 595         }
 596
 597         /* The flash write must be aligned to a halfword boundary.
 598          * The flash infrastructure ensures it, do just a security check
 599          */
 600         assert(offset % 2 == 0);
 601         assert(count % 2 == 0);
 602
 603         int retval, retval2;
 604
 605         /* unlock flash registers */
 606         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 607         if (retval != ERROR_OK)
 608                 return retval;
 609         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 610         if (retval != ERROR_OK)
 611                 goto reset_pg_and_lock;
 612
 613         /* enable flash programming */
 614         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 615         if (retval != ERROR_OK)
 616                 goto reset_pg_and_lock;
 617
 618         /* write to flash */
 619         retval = stm32x_write_block(bank, buffer, bank->base + offset, count / 2);
 620
 621 reset_pg_and_lock:
 622         retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 623         if (retval == ERROR_OK)
 624                 retval = retval2;
 625
 626         return retval;
 627 }
 628
 629 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 630 {
 631         struct target *target = bank->target;
 632         uint32_t device_id_register = 0;
 633
 634         if (!target_was_examined(target)) {
 635                 LOG_ERROR("Target not examined yet");
 636                 return ERROR_TARGET_NOT_EXAMINED;
 637         }
 638
 639         switch (cortex_m_get_partno_safe(target)) {
 640         case CORTEX_M0_PARTNO: /* STM32F0x devices */
 641                 device_id_register = 0x40015800;
 642                 break;
 643         case CORTEX_M3_PARTNO: /* STM32F1x devices */
 644                 device_id_register = 0xE0042000;
 645                 break;
 646         case CORTEX_M4_PARTNO: /* STM32F3x devices */
 647                 device_id_register = 0xE0042000;
 648                 break;
 649         case CORTEX_M23_PARTNO: /* GD32E23x devices */
 650                 device_id_register = 0x40015800;
 651                 break;
 652         default:
 653                 LOG_ERROR("Cannot identify target as a stm32x");
 654                 return ERROR_FAIL;
 655         }
 656
 657         /* read stm32 device id register */
 658         int retval = target_read_u32(target, device_id_register, device_id);
 659         if (retval != ERROR_OK)
 660                 return retval;
 661
 662         return retval;
 663 }
 664
 665 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
 666 {
 667         struct target *target = bank->target;
 668         uint32_t flash_size_reg;
 669
 670         if (!target_was_examined(target)) {
 671                 LOG_ERROR("Target not examined yet");
 672                 return ERROR_TARGET_NOT_EXAMINED;
 673         }
 674
 675         switch (cortex_m_get_partno_safe(target)) {
 676         case CORTEX_M0_PARTNO: /* STM32F0x devices */
 677                 flash_size_reg = 0x1FFFF7CC;
 678                 break;
 679         case CORTEX_M3_PARTNO: /* STM32F1x devices */
 680                 flash_size_reg = 0x1FFFF7E0;
 681                 break;
 682         case CORTEX_M4_PARTNO: /* STM32F3x devices */
 683                 flash_size_reg = 0x1FFFF7CC;
 684                 break;
 685         case CORTEX_M23_PARTNO: /* GD32E23x devices */
 686                 flash_size_reg = 0x1FFFF7E0;
 687                 break;
 688         default:
 689                 LOG_ERROR("Cannot identify target as a stm32x");
 690                 return ERROR_FAIL;
 691         }
 692
 693         int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
 694         if (retval != ERROR_OK)
 695                 return retval;
 696
 697         return retval;
 698 }
 699
 700 static int stm32x_probe(struct flash_bank *bank)
 701 {
 702         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 703         uint16_t flash_size_in_kb;
 704         uint16_t max_flash_size_in_kb;
 705         uint32_t dbgmcu_idcode;
 706         int page_size;
 707         uint32_t base_address = 0x08000000;
 708
 709         stm32x_info->probed = false;
 710         stm32x_info->register_base = FLASH_REG_BASE_B0;
 711         stm32x_info->user_data_offset = 10;
 712         stm32x_info->option_offset = 0;
 713
 714         /* default factory read protection level 0 */
 715         stm32x_info->default_rdp = 0xA5;
 716
 717         /* read stm32 device id register */
 718         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 719         if (retval != ERROR_OK)
 720                 return retval;
 721
 722         LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
 723
 724         uint16_t device_id = dbgmcu_idcode & 0xfff;
 725         uint16_t rev_id = dbgmcu_idcode >> 16;
 726
 727         /* set page size, protection granularity and max flash size depending on family */
 728         switch (device_id) {
 729         case 0x440: /* stm32f05x */
 730                 page_size = 1024;
 731                 stm32x_info->ppage_size = 4;
 732                 max_flash_size_in_kb = 64;
 733                 stm32x_info->user_data_offset = 16;
 734                 stm32x_info->option_offset = 6;
 735                 stm32x_info->default_rdp = 0xAA;
 736                 stm32x_info->can_load_options = true;
 737                 break;
 738         case 0x444: /* stm32f03x */
 739         case 0x445: /* stm32f04x */
 740                 page_size = 1024;
 741                 stm32x_info->ppage_size = 4;
 742                 max_flash_size_in_kb = 32;
 743                 stm32x_info->user_data_offset = 16;
 744                 stm32x_info->option_offset = 6;
 745                 stm32x_info->default_rdp = 0xAA;
 746                 stm32x_info->can_load_options = true;
 747                 break;
 748         case 0x448: /* stm32f07x */
 749                 page_size = 2048;
 750                 stm32x_info->ppage_size = 4;
 751                 max_flash_size_in_kb = 128;
 752                 stm32x_info->user_data_offset = 16;
 753                 stm32x_info->option_offset = 6;
 754                 stm32x_info->default_rdp = 0xAA;
 755                 stm32x_info->can_load_options = true;
 756                 break;
 757         case 0x442: /* stm32f09x */
 758                 page_size = 2048;
 759                 stm32x_info->ppage_size = 4;
 760                 max_flash_size_in_kb = 256;
 761                 stm32x_info->user_data_offset = 16;
 762                 stm32x_info->option_offset = 6;
 763                 stm32x_info->default_rdp = 0xAA;
 764                 stm32x_info->can_load_options = true;
 765                 break;
 766         case 0x410: /* stm32f1x medium-density */
 767                 page_size = 1024;
 768                 stm32x_info->ppage_size = 4;
 769                 max_flash_size_in_kb = 128;
 770                 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
 771                    share DEV_ID with STM32F101/2/3 medium-density line,
 772                    however they use a REV_ID different from any STM32 device.
 773                    The main difference is another offset of user option bits
 774                    (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
 775                    (FLASH_OBR/FMC_OBSTAT 0x4002201C).
 776                    This caused problems e.g. during flash block programming
 777                    because of unexpected active hardware watchog. */
 778                 switch (rev_id) {
 779                 case 0x1303: /* gd32f1x0 */
 780                         stm32x_info->user_data_offset = 16;
 781                         stm32x_info->option_offset = 6;
 782                         max_flash_size_in_kb = 64;
 783                         break;
 784                 case 0x1704: /* gd32f3x0 */
 785                         stm32x_info->user_data_offset = 16;
 786                         stm32x_info->option_offset = 6;
 787                         break;
 788                 case 0x1909: /* gd32e23x */
 789                         stm32x_info->user_data_offset = 16;
 790                         stm32x_info->option_offset = 6;
 791                         max_flash_size_in_kb = 64;
 792                         break;
 793                 }
 794                 break;
 795         case 0x412: /* stm32f1x low-density */
 796                 page_size = 1024;
 797                 stm32x_info->ppage_size = 4;
 798                 max_flash_size_in_kb = 32;
 799                 break;
 800         case 0x414: /* stm32f1x high-density */
 801                 page_size = 2048;
 802                 stm32x_info->ppage_size = 2;
 803                 max_flash_size_in_kb = 512;
 804                 break;
 805         case 0x418: /* stm32f1x connectivity */
 806                 page_size = 2048;
 807                 stm32x_info->ppage_size = 2;
 808                 max_flash_size_in_kb = 256;
 809                 break;
 810         case 0x430: /* stm32f1 XL-density (dual flash banks) */
 811                 page_size = 2048;
 812                 stm32x_info->ppage_size = 2;
 813                 max_flash_size_in_kb = 1024;
 814                 stm32x_info->has_dual_banks = true;
 815                 break;
 816         case 0x420: /* stm32f100xx low- and medium-density value line */
 817                 page_size = 1024;
 818                 stm32x_info->ppage_size = 4;
 819                 max_flash_size_in_kb = 128;
 820                 break;
 821         case 0x428: /* stm32f100xx high-density value line */
 822                 page_size = 2048;
 823                 stm32x_info->ppage_size = 4;
 824                 max_flash_size_in_kb = 512;
 825                 break;
 826         case 0x422: /* stm32f302/3xb/c */
 827                 page_size = 2048;
 828                 stm32x_info->ppage_size = 2;
 829                 max_flash_size_in_kb = 256;
 830                 stm32x_info->user_data_offset = 16;
 831                 stm32x_info->option_offset = 6;
 832                 stm32x_info->default_rdp = 0xAA;
 833                 stm32x_info->can_load_options = true;
 834                 break;
 835         case 0x446: /* stm32f303xD/E */
 836                 page_size = 2048;
 837                 stm32x_info->ppage_size = 2;
 838                 max_flash_size_in_kb = 512;
 839                 stm32x_info->user_data_offset = 16;
 840                 stm32x_info->option_offset = 6;
 841                 stm32x_info->default_rdp = 0xAA;
 842                 stm32x_info->can_load_options = true;
 843                 break;
 844         case 0x432: /* stm32f37x */
 845                 page_size = 2048;
 846                 stm32x_info->ppage_size = 2;
 847                 max_flash_size_in_kb = 256;
 848                 stm32x_info->user_data_offset = 16;
 849                 stm32x_info->option_offset = 6;
 850                 stm32x_info->default_rdp = 0xAA;
 851                 stm32x_info->can_load_options = true;
 852                 break;
 853         case 0x438: /* stm32f33x */
 854         case 0x439: /* stm32f302x6/8 */
 855                 page_size = 2048;
 856                 stm32x_info->ppage_size = 2;
 857                 max_flash_size_in_kb = 64;
 858                 stm32x_info->user_data_offset = 16;
 859                 stm32x_info->option_offset = 6;
 860                 stm32x_info->default_rdp = 0xAA;
 861                 stm32x_info->can_load_options = true;
 862                 break;
 863         default:
 864                 LOG_WARNING("Cannot identify target as a STM32 family.");
 865                 return ERROR_FAIL;
 866         }
 867
 868         /* get flash size from target. */
 869         retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
 870
 871         /* failed reading flash size or flash size invalid (early silicon),
 872          * default to max target family */
 873         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 874                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 875                         max_flash_size_in_kb);
 876                 flash_size_in_kb = max_flash_size_in_kb;
 877         }
 878
 879         if (stm32x_info->has_dual_banks) {
 880                 /* split reported size into matching bank */
 881                 if (bank->base != 0x08080000) {
 882                         /* bank 0 will be fixed 512k */
 883                         flash_size_in_kb = 512;
 884                 } else {
 885                         flash_size_in_kb -= 512;
 886                         /* bank1 also uses a register offset */
 887                         stm32x_info->register_base = FLASH_REG_BASE_B1;
 888                         base_address = 0x08080000;
 889                 }
 890         }
 891
 892         /* if the user sets the size manually then ignore the probed value
 893          * this allows us to work around devices that have a invalid flash size register value */
 894         if (stm32x_info->user_bank_size) {
 895                 LOG_INFO("ignoring flash probed value, using configured bank size");
 896                 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
 897         }
 898
 899         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 900
 901         /* did we assign flash size? */
 902         assert(flash_size_in_kb != 0xffff);
 903
 904         /* calculate numbers of pages */
 905         int num_pages = flash_size_in_kb * 1024 / page_size;
 906
 907         /* check that calculation result makes sense */
 908         assert(num_pages > 0);
 909
 910         free(bank->sectors);
 911         bank->sectors = NULL;
 912
 913         free(bank->prot_blocks);
 914         bank->prot_blocks = NULL;
 915
 916         bank->base = base_address;
 917         bank->size = (num_pages * page_size);
 918
 919         bank->num_sectors = num_pages;
 920         bank->sectors = alloc_block_array(0, page_size, num_pages);
 921         if (!bank->sectors)
 922                 return ERROR_FAIL;
 923
 924         /* calculate number of write protection blocks */
 925         int num_prot_blocks = num_pages / stm32x_info->ppage_size;
 926         if (num_prot_blocks > 32)
 927                 num_prot_blocks = 32;
 928
 929         bank->num_prot_blocks = num_prot_blocks;
 930         bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
 931         if (!bank->prot_blocks)
 932                 return ERROR_FAIL;
 933
 934         if (num_prot_blocks == 32)
 935                 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
 936
 937         stm32x_info->probed = true;
 938
 939         return ERROR_OK;
 940 }
 941
 942 static int stm32x_auto_probe(struct flash_bank *bank)
 943 {
 944         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 945         if (stm32x_info->probed)
 946                 return ERROR_OK;
 947         return stm32x_probe(bank);
 948 }
 949
 950 #if 0
 951 COMMAND_HANDLER(stm32x_handle_part_id_command)
 952 {
 953         return ERROR_OK;
 954 }
 955 #endif
 956
 957 static const char *get_stm32f0_revision(uint16_t rev_id)
 958 {
 959         const char *rev_str = NULL;
 960
 961         switch (rev_id) {
 962         case 0x1000:
 963                 rev_str = "1.0";
 964                 break;
 965         case 0x2000:
 966                 rev_str = "2.0";
 967                 break;
 968         }
 969         return rev_str;
 970 }
 971
 972 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
 973 {
 974         uint32_t dbgmcu_idcode;
 975
 976         /* read stm32 device id register */
 977         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 978         if (retval != ERROR_OK)
 979                 return retval;
 980
 981         uint16_t device_id = dbgmcu_idcode & 0xfff;
 982         uint16_t rev_id = dbgmcu_idcode >> 16;
 983         const char *device_str;
 984         const char *rev_str = NULL;
 985
 986         switch (device_id) {
 987         case 0x410:
 988                 device_str = "STM32F10x (Medium Density)";
 989
 990                 switch (rev_id) {
 991                 case 0x0000:
 992                         rev_str = "A";
 993                         break;
 994
 995                 case 0x1303: /* gd32f1x0 */
 996                         device_str = "GD32F1x0";
 997                         break;
 998
 999                 case 0x1704: /* gd32f3x0 */
1000                         device_str = "GD32F3x0";
1001                         break;
1002
1003                 case 0x1909: /* gd32e23x */
1004                         device_str = "GD32E23x";
1005                         break;
1006
1007                 case 0x2000:
1008                         rev_str = "B";
1009                         break;
1010
1011                 case 0x2001:
1012                         rev_str = "Z";
1013                         break;
1014
1015                 case 0x2003:
1016                         rev_str = "Y";
1017                         break;
1018                 }
1019                 break;
1020
1021         case 0x412:
1022                 device_str = "STM32F10x (Low Density)";
1023
1024                 switch (rev_id) {
1025                 case 0x1000:
1026                         rev_str = "A";
1027                         break;
1028                 }
1029                 break;
1030
1031         case 0x414:
1032                 device_str = "STM32F10x (High Density)";
1033
1034                 switch (rev_id) {
1035                 case 0x1000:
1036                         rev_str = "A";
1037                         break;
1038
1039                 case 0x1001:
1040                         rev_str = "Z";
1041                         break;
1042
1043                 case 0x1003:
1044                         rev_str = "Y";
1045                         break;
1046                 }
1047                 break;
1048
1049         case 0x418:
1050                 device_str = "STM32F10x (Connectivity)";
1051
1052                 switch (rev_id) {
1053                 case 0x1000:
1054                         rev_str = "A";
1055                         break;
1056
1057                 case 0x1001:
1058                         rev_str = "Z";
1059                         break;
1060                 }
1061                 break;
1062
1063         case 0x420:
1064                 device_str = "STM32F100 (Low/Medium Density)";
1065
1066                 switch (rev_id) {
1067                 case 0x1000:
1068                         rev_str = "A";
1069                         break;
1070
1071                 case 0x1001:
1072                         rev_str = "Z";
1073                         break;
1074                 }
1075                 break;
1076
1077         case 0x422:
1078                 device_str = "STM32F302xB/C";
1079
1080                 switch (rev_id) {
1081                 case 0x1000:
1082                         rev_str = "A";
1083                         break;
1084
1085                 case 0x1001:
1086                         rev_str = "Z";
1087                         break;
1088
1089                 case 0x1003:
1090                         rev_str = "Y";
1091                         break;
1092
1093                 case 0x2000:
1094                         rev_str = "B";
1095                         break;
1096                 }
1097                 break;
1098
1099         case 0x428:
1100                 device_str = "STM32F100 (High Density)";
1101
1102                 switch (rev_id) {
1103                 case 0x1000:
1104                         rev_str = "A";
1105                         break;
1106
1107                 case 0x1001:
1108                         rev_str = "Z";
1109                         break;
1110                 }
1111                 break;
1112
1113         case 0x430:
1114                 device_str = "STM32F10x (XL Density)";
1115
1116                 switch (rev_id) {
1117                 case 0x1000:
1118                         rev_str = "A";
1119                         break;
1120                 }
1121                 break;
1122
1123         case 0x432:
1124                 device_str = "STM32F37x";
1125
1126                 switch (rev_id) {
1127                 case 0x1000:
1128                         rev_str = "A";
1129                         break;
1130
1131                 case 0x2000:
1132                         rev_str = "B";
1133                         break;
1134                 }
1135                 break;
1136
1137         case 0x438:
1138                 device_str = "STM32F33x";
1139
1140                 switch (rev_id) {
1141                 case 0x1000:
1142                         rev_str = "A";
1143                         break;
1144                 }
1145                 break;
1146
1147         case 0x439:
1148                 device_str = "STM32F302x6/8";
1149
1150                 switch (rev_id) {
1151                 case 0x1000:
1152                         rev_str = "A";
1153                         break;
1154
1155                 case 0x1001:
1156                         rev_str = "Z";
1157                         break;
1158                 }
1159                 break;
1160
1161         case 0x444:
1162                 device_str = "STM32F03x";
1163                 rev_str = get_stm32f0_revision(rev_id);
1164                 break;
1165
1166         case 0x440:
1167                 device_str = "STM32F05x";
1168                 rev_str = get_stm32f0_revision(rev_id);
1169                 break;
1170
1171         case 0x445:
1172                 device_str = "STM32F04x";
1173                 rev_str = get_stm32f0_revision(rev_id);
1174                 break;
1175
1176         case 0x446:
1177                 device_str = "STM32F303xD/E";
1178                 switch (rev_id) {
1179                 case 0x1000:
1180                         rev_str = "A";
1181                         break;
1182                 }
1183                 break;
1184
1185         case 0x448:
1186                 device_str = "STM32F07x";
1187                 rev_str = get_stm32f0_revision(rev_id);
1188                 break;
1189
1190         case 0x442:
1191                 device_str = "STM32F09x";
1192                 rev_str = get_stm32f0_revision(rev_id);
1193                 break;
1194
1195         default:
1196                 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1197                 return ERROR_FAIL;
1198         }
1199
1200         if (rev_str)
1201                 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1202         else
1203                 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1204
1205         return ERROR_OK;
1206 }
1207
1208 COMMAND_HANDLER(stm32x_handle_lock_command)
1209 {
1210         struct target *target = NULL;
1211         struct stm32x_flash_bank *stm32x_info = NULL;
1212
1213         if (CMD_ARGC < 1)
1214                 return ERROR_COMMAND_SYNTAX_ERROR;
1215
1216         struct flash_bank *bank;
1217         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1218         if (retval != ERROR_OK)
1219                 return retval;
1220
1221         stm32x_info = bank->driver_priv;
1222
1223         target = bank->target;
1224
1225         if (target->state != TARGET_HALTED) {
1226                 LOG_ERROR("Target not halted");
1227                 return ERROR_TARGET_NOT_HALTED;
1228         }
1229
1230         retval = stm32x_check_operation_supported(bank);
1231         if (retval != ERROR_OK)
1232                 return retval;
1233
1234         if (stm32x_erase_options(bank) != ERROR_OK) {
1235                 command_print(CMD, "stm32x failed to erase options");
1236                 return ERROR_OK;
1237         }
1238
1239         /* set readout protection */
1240         stm32x_info->option_bytes.rdp = 0;
1241
1242         if (stm32x_write_options(bank) != ERROR_OK) {
1243                 command_print(CMD, "stm32x failed to lock device");
1244                 return ERROR_OK;
1245         }
1246
1247         command_print(CMD, "stm32x locked");
1248
1249         return ERROR_OK;
1250 }
1251
1252 COMMAND_HANDLER(stm32x_handle_unlock_command)
1253 {
1254         struct target *target = NULL;
1255
1256         if (CMD_ARGC < 1)
1257                 return ERROR_COMMAND_SYNTAX_ERROR;
1258
1259         struct flash_bank *bank;
1260         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1261         if (retval != ERROR_OK)
1262                 return retval;
1263
1264         target = bank->target;
1265
1266         if (target->state != TARGET_HALTED) {
1267                 LOG_ERROR("Target not halted");
1268                 return ERROR_TARGET_NOT_HALTED;
1269         }
1270
1271         retval = stm32x_check_operation_supported(bank);
1272         if (retval != ERROR_OK)
1273                 return retval;
1274
1275         if (stm32x_erase_options(bank) != ERROR_OK) {
1276                 command_print(CMD, "stm32x failed to erase options");
1277                 return ERROR_OK;
1278         }
1279
1280         if (stm32x_write_options(bank) != ERROR_OK) {
1281                 command_print(CMD, "stm32x failed to unlock device");
1282                 return ERROR_OK;
1283         }
1284
1285         command_print(CMD, "stm32x unlocked.\n"
1286                         "INFO: a reset or power cycle is required "
1287                         "for the new settings to take effect.");
1288
1289         return ERROR_OK;
1290 }
1291
1292 COMMAND_HANDLER(stm32x_handle_options_read_command)
1293 {
1294         uint32_t optionbyte, protection;
1295         struct target *target = NULL;
1296         struct stm32x_flash_bank *stm32x_info = NULL;
1297
1298         if (CMD_ARGC < 1)
1299                 return ERROR_COMMAND_SYNTAX_ERROR;
1300
1301         struct flash_bank *bank;
1302         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1303         if (retval != ERROR_OK)
1304                 return retval;
1305
1306         stm32x_info = bank->driver_priv;
1307
1308         target = bank->target;
1309
1310         if (target->state != TARGET_HALTED) {
1311                 LOG_ERROR("Target not halted");
1312                 return ERROR_TARGET_NOT_HALTED;
1313         }
1314
1315         retval = stm32x_check_operation_supported(bank);
1316         if (retval != ERROR_OK)
1317                 return retval;
1318
1319         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1320         if (retval != ERROR_OK)
1321                 return retval;
1322
1323         uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1324
1325         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1326         if (retval != ERROR_OK)
1327                 return retval;
1328
1329         if (optionbyte & (1 << OPT_ERROR))
1330                 command_print(CMD, "option byte complement error");
1331
1332         command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1333         command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1334
1335         command_print(CMD, "read protection: %s",
1336                                 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1337
1338         /* user option bytes are offset depending on variant */
1339         optionbyte >>= stm32x_info->option_offset;
1340
1341         command_print(CMD, "watchdog: %sware",
1342                                 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1343
1344         command_print(CMD, "stop mode: %sreset generated upon entry",
1345                                 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1346
1347         command_print(CMD, "standby mode: %sreset generated upon entry",
1348                                 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1349
1350         if (stm32x_info->has_dual_banks)
1351                 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1352
1353         command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1354
1355         return ERROR_OK;
1356 }
1357
1358 COMMAND_HANDLER(stm32x_handle_options_write_command)
1359 {
1360         struct target *target = NULL;
1361         struct stm32x_flash_bank *stm32x_info = NULL;
1362         uint8_t optionbyte;
1363         uint16_t useropt;
1364
1365         if (CMD_ARGC < 2)
1366                 return ERROR_COMMAND_SYNTAX_ERROR;
1367
1368         struct flash_bank *bank;
1369         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1370         if (retval != ERROR_OK)
1371                 return retval;
1372
1373         stm32x_info = bank->driver_priv;
1374
1375         target = bank->target;
1376
1377         if (target->state != TARGET_HALTED) {
1378                 LOG_ERROR("Target not halted");
1379                 return ERROR_TARGET_NOT_HALTED;
1380         }
1381
1382         retval = stm32x_check_operation_supported(bank);
1383         if (retval != ERROR_OK)
1384                 return retval;
1385
1386         retval = stm32x_read_options(bank);
1387         if (retval != ERROR_OK)
1388                 return retval;
1389
1390         /* start with current options */
1391         optionbyte = stm32x_info->option_bytes.user;
1392         useropt = stm32x_info->option_bytes.data;
1393
1394         /* skip over flash bank */
1395         CMD_ARGC--;
1396         CMD_ARGV++;
1397
1398         while (CMD_ARGC) {
1399                 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1400                         optionbyte |= (1 << 0);
1401                 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1402                         optionbyte &= ~(1 << 0);
1403                 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1404                         optionbyte |= (1 << 1);
1405                 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1406                         optionbyte &= ~(1 << 1);
1407                 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1408                         optionbyte |= (1 << 2);
1409                 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1410                         optionbyte &= ~(1 << 2);
1411                 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1412                         if (CMD_ARGC < 2)
1413                                 return ERROR_COMMAND_SYNTAX_ERROR;
1414                         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1415                         CMD_ARGC--;
1416                         CMD_ARGV++;
1417                 } else if (stm32x_info->has_dual_banks) {
1418                         if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1419                                 optionbyte |= (1 << 3);
1420                         else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1421                                 optionbyte &= ~(1 << 3);
1422                         else
1423                                 return ERROR_COMMAND_SYNTAX_ERROR;
1424                 } else
1425                         return ERROR_COMMAND_SYNTAX_ERROR;
1426                 CMD_ARGC--;
1427                 CMD_ARGV++;
1428         }
1429
1430         if (stm32x_erase_options(bank) != ERROR_OK) {
1431                 command_print(CMD, "stm32x failed to erase options");
1432                 return ERROR_OK;
1433         }
1434
1435         stm32x_info->option_bytes.user = optionbyte;
1436         stm32x_info->option_bytes.data = useropt;
1437
1438         if (stm32x_write_options(bank) != ERROR_OK) {
1439                 command_print(CMD, "stm32x failed to write options");
1440                 return ERROR_OK;
1441         }
1442
1443         command_print(CMD, "stm32x write options complete.\n"
1444                                 "INFO: %spower cycle is required "
1445                                 "for the new settings to take effect.",
1446                                 stm32x_info->can_load_options
1447                                         ? "'stm32f1x options_load' command or " : "");
1448
1449         return ERROR_OK;
1450 }
1451
1452 COMMAND_HANDLER(stm32x_handle_options_load_command)
1453 {
1454         if (CMD_ARGC < 1)
1455                 return ERROR_COMMAND_SYNTAX_ERROR;
1456
1457         struct flash_bank *bank;
1458         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1459         if (retval != ERROR_OK)
1460                 return retval;
1461
1462         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1463
1464         if (!stm32x_info->can_load_options) {
1465                 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1466                         "required instead.");
1467                 return ERROR_FAIL;
1468         }
1469
1470         struct target *target = bank->target;
1471
1472         if (target->state != TARGET_HALTED) {
1473                 LOG_ERROR("Target not halted");
1474                 return ERROR_TARGET_NOT_HALTED;
1475         }
1476
1477         retval = stm32x_check_operation_supported(bank);
1478         if (retval != ERROR_OK)
1479                 return retval;
1480
1481         /* unlock option flash registers */
1482         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1483         if (retval != ERROR_OK)
1484                 return retval;
1485         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1486         if (retval != ERROR_OK)
1487                 return retval;
1488
1489         /* force re-load of option bytes - generates software reset */
1490         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1491         if (retval != ERROR_OK)
1492                 return retval;
1493
1494         return ERROR_OK;
1495 }
1496
1497 static int stm32x_mass_erase(struct flash_bank *bank)
1498 {
1499         struct target *target = bank->target;
1500
1501         if (target->state != TARGET_HALTED) {
1502                 LOG_ERROR("Target not halted");
1503                 return ERROR_TARGET_NOT_HALTED;
1504         }
1505
1506         /* unlock option flash registers */
1507         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1508         if (retval != ERROR_OK)
1509                 return retval;
1510         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1511         if (retval != ERROR_OK)
1512                 return retval;
1513
1514         /* mass erase flash memory */
1515         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1516         if (retval != ERROR_OK)
1517                 return retval;
1518         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1519                         FLASH_MER | FLASH_STRT);
1520         if (retval != ERROR_OK)
1521                 return retval;
1522
1523         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1524         if (retval != ERROR_OK)
1525                 return retval;
1526
1527         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1528         if (retval != ERROR_OK)
1529                 return retval;
1530
1531         return ERROR_OK;
1532 }
1533
1534 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1535 {
1536         if (CMD_ARGC < 1)
1537                 return ERROR_COMMAND_SYNTAX_ERROR;
1538
1539         struct flash_bank *bank;
1540         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1541         if (retval != ERROR_OK)
1542                 return retval;
1543
1544         retval = stm32x_mass_erase(bank);
1545         if (retval == ERROR_OK)
1546                 command_print(CMD, "stm32x mass erase complete");
1547         else
1548                 command_print(CMD, "stm32x mass erase failed");
1549
1550         return retval;
1551 }
1552
1553 static const struct command_registration stm32f1x_exec_command_handlers[] = {
1554         {
1555                 .name = "lock",
1556                 .handler = stm32x_handle_lock_command,
1557                 .mode = COMMAND_EXEC,
1558                 .usage = "bank_id",
1559                 .help = "Lock entire flash device.",
1560         },
1561         {
1562                 .name = "unlock",
1563                 .handler = stm32x_handle_unlock_command,
1564                 .mode = COMMAND_EXEC,
1565                 .usage = "bank_id",
1566                 .help = "Unlock entire protected flash device.",
1567         },
1568         {
1569                 .name = "mass_erase",
1570                 .handler = stm32x_handle_mass_erase_command,
1571                 .mode = COMMAND_EXEC,
1572                 .usage = "bank_id",
1573                 .help = "Erase entire flash device.",
1574         },
1575         {
1576                 .name = "options_read",
1577                 .handler = stm32x_handle_options_read_command,
1578                 .mode = COMMAND_EXEC,
1579                 .usage = "bank_id",
1580                 .help = "Read and display device option bytes.",
1581         },
1582         {
1583                 .name = "options_write",
1584                 .handler = stm32x_handle_options_write_command,
1585                 .mode = COMMAND_EXEC,
1586                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1587                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1588                         "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1589                 .help = "Replace bits in device option bytes.",
1590         },
1591         {
1592                 .name = "options_load",
1593                 .handler = stm32x_handle_options_load_command,
1594                 .mode = COMMAND_EXEC,
1595                 .usage = "bank_id",
1596                 .help = "Force re-load of device option bytes.",
1597         },
1598         COMMAND_REGISTRATION_DONE
1599 };
1600
1601 static const struct command_registration stm32f1x_command_handlers[] = {
1602         {
1603                 .name = "stm32f1x",
1604                 .mode = COMMAND_ANY,
1605                 .help = "stm32f1x flash command group",
1606                 .usage = "",
1607                 .chain = stm32f1x_exec_command_handlers,
1608         },
1609         COMMAND_REGISTRATION_DONE
1610 };
1611
1612 const struct flash_driver stm32f1x_flash = {
1613         .name = "stm32f1x",
1614         .commands = stm32f1x_command_handlers,
1615         .flash_bank_command = stm32x_flash_bank_command,
1616         .erase = stm32x_erase,
1617         .protect = stm32x_protect,
1618         .write = stm32x_write,
1619         .read = default_flash_read,
1620         .probe = stm32x_probe,
1621         .auto_probe = stm32x_auto_probe,
1622         .erase_check = default_flash_blank_check,
1623         .protect_check = stm32x_protect_check,
1624         .info = get_stm32x_info,
1625         .free_driver_priv = default_flash_free_driver_priv,
1626 };