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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "imp.h"
  28 #include <helper/binarybuffer.h>
  29 #include <target/algorithm.h>
  30 #include <target/armv7m.h>
  31
  32 /* stm32x register locations */
  33
  34 #define FLASH_REG_BASE_B0 0x40022000
  35 #define FLASH_REG_BASE_B1 0x40022040
  36
  37 #define STM32_FLASH_ACR     0x00
  38 #define STM32_FLASH_KEYR    0x04
  39 #define STM32_FLASH_OPTKEYR 0x08
  40 #define STM32_FLASH_SR      0x0C
  41 #define STM32_FLASH_CR      0x10
  42 #define STM32_FLASH_AR      0x14
  43 #define STM32_FLASH_OBR     0x1C
  44 #define STM32_FLASH_WRPR    0x20
  45
  46 /* TODO: Check if code using these really should be hard coded to bank 0.
  47  * There are valid cases, on dual flash devices the protection of the
  48  * second bank is done on the bank0 reg's. */
  49 #define STM32_FLASH_ACR_B0     0x40022000
  50 #define STM32_FLASH_KEYR_B0    0x40022004
  51 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  52 #define STM32_FLASH_SR_B0      0x4002200C
  53 #define STM32_FLASH_CR_B0      0x40022010
  54 #define STM32_FLASH_AR_B0      0x40022014
  55 #define STM32_FLASH_OBR_B0     0x4002201C
  56 #define STM32_FLASH_WRPR_B0    0x40022020
  57
  58 /* option byte location */
  59
  60 #define STM32_OB_RDP            0x1FFFF800
  61 #define STM32_OB_USER           0x1FFFF802
  62 #define STM32_OB_DATA0          0x1FFFF804
  63 #define STM32_OB_DATA1          0x1FFFF806
  64 #define STM32_OB_WRP0           0x1FFFF808
  65 #define STM32_OB_WRP1           0x1FFFF80A
  66 #define STM32_OB_WRP2           0x1FFFF80C
  67 #define STM32_OB_WRP3           0x1FFFF80E
  68
  69 /* FLASH_CR register bits */
  70
  71 #define FLASH_PG                (1 << 0)
  72 #define FLASH_PER               (1 << 1)
  73 #define FLASH_MER               (1 << 2)
  74 #define FLASH_OPTPG             (1 << 4)
  75 #define FLASH_OPTER             (1 << 5)
  76 #define FLASH_STRT              (1 << 6)
  77 #define FLASH_LOCK              (1 << 7)
  78 #define FLASH_OPTWRE    (1 << 9)
  79
  80 /* FLASH_SR register bits */
  81
  82 #define FLASH_BSY               (1 << 0)
  83 #define FLASH_PGERR             (1 << 2)
  84 #define FLASH_WRPRTERR  (1 << 4)
  85 #define FLASH_EOP               (1 << 5)
  86
  87 /* STM32_FLASH_OBR bit definitions (reading) */
  88
  89 #define OPT_ERROR               0
  90 #define OPT_READOUT             1
  91 #define OPT_RDWDGSW             2
  92 #define OPT_RDRSTSTOP   3
  93 #define OPT_RDRSTSTDBY  4
  94 #define OPT_BFB2                5       /* dual flash bank only */
  95
  96 /* register unlock keys */
  97
  98 #define KEY1                    0x45670123
  99 #define KEY2                    0xCDEF89AB
 100
 101 struct stm32x_options
 102 {
 103         uint16_t RDP;
 104         uint16_t user_options;
 105         uint16_t protection[4];
 106 };
 107
 108 struct stm32x_flash_bank
 109 {
 110         struct stm32x_options option_bytes;
 111         struct working_area *write_algorithm;
 112         int ppage_size;
 113         int probed;
 114
 115         bool has_dual_banks;
 116         /* used to access dual flash bank stm32xl */
 117         uint32_t register_base;
 118 };
 119
 120 static int stm32x_mass_erase(struct flash_bank *bank);
 121
 122 /* flash bank stm32x <base> <size> 0 0 <target#>
 123  */
 124 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 125 {
 126         struct stm32x_flash_bank *stm32x_info;
 127
 128         if (CMD_ARGC < 6)
 129         {
 130                 LOG_WARNING("incomplete flash_bank stm32x configuration");
 131                 return ERROR_FLASH_BANK_INVALID;
 132         }
 133
 134         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 135         bank->driver_priv = stm32x_info;
 136
 137         stm32x_info->write_algorithm = NULL;
 138         stm32x_info->probed = 0;
 139         stm32x_info->has_dual_banks = false;
 140         stm32x_info->register_base = FLASH_REG_BASE_B0;
 141
 142         return ERROR_OK;
 143 }
 144
 145 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 146 {
 147         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 148         return reg + stm32x_info->register_base;
 149 }
 150
 151 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 152 {
 153         struct target *target = bank->target;
 154         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 155 }
 156
 157 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 158 {
 159         struct target *target = bank->target;
 160         uint32_t status;
 161         int retval = ERROR_OK;
 162
 163         /* wait for busy to clear */
 164         for (;;)
 165         {
 166                 retval = stm32x_get_flash_status(bank, &status);
 167                 if (retval != ERROR_OK)
 168                         return retval;
 169                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 170                 if ((status & FLASH_BSY) == 0)
 171                         break;
 172                 if (timeout-- <= 0)
 173                 {
 174                         LOG_ERROR("timed out waiting for flash");
 175                         return ERROR_FAIL;
 176                 }
 177                 alive_sleep(1);
 178         }
 179
 180         if (status & FLASH_WRPRTERR)
 181         {
 182                 LOG_ERROR("stm32x device protected");
 183                 retval = ERROR_FAIL;
 184         }
 185
 186         if (status & FLASH_PGERR)
 187         {
 188                 LOG_ERROR("stm32x device programming failed");
 189                 retval = ERROR_FAIL;
 190         }
 191
 192         /* Clear but report errors */
 193         if (status & (FLASH_WRPRTERR | FLASH_PGERR))
 194         {
 195                 /* If this operation fails, we ignore it and report the original
 196                  * retval
 197                  */
 198                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 199                                 FLASH_WRPRTERR | FLASH_PGERR);
 200         }
 201         return retval;
 202 }
 203
 204 int stm32x_check_operation_supported(struct flash_bank *bank)
 205 {
 206         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 207
 208         /* if we have a dual flash bank device then
 209          * we need to perform option byte stuff on bank0 only */
 210         if (stm32x_info->register_base != FLASH_REG_BASE_B0)
 211         {
 212                 LOG_ERROR("Option Byte Operation's must use bank0");
 213                 return ERROR_FLASH_OPERATION_FAILED;
 214         }
 215
 216         return ERROR_OK;
 217 }
 218
 219 static int stm32x_read_options(struct flash_bank *bank)
 220 {
 221         uint32_t optiondata;
 222         struct stm32x_flash_bank *stm32x_info = NULL;
 223         struct target *target = bank->target;
 224
 225         stm32x_info = bank->driver_priv;
 226
 227         /* read current option bytes */
 228         int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
 229         if (retval != ERROR_OK)
 230                 return retval;
 231
 232         stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
 233         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 234
 235         if (optiondata & (1 << OPT_READOUT))
 236                 LOG_INFO("Device Security Bit Set");
 237
 238         /* each bit refers to a 4bank protection */
 239         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
 240         if (retval != ERROR_OK)
 241                 return retval;
 242
 243         stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
 244         stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
 245         stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
 246         stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
 247
 248         return ERROR_OK;
 249 }
 250
 251 static int stm32x_erase_options(struct flash_bank *bank)
 252 {
 253         struct stm32x_flash_bank *stm32x_info = NULL;
 254         struct target *target = bank->target;
 255
 256         stm32x_info = bank->driver_priv;
 257
 258         /* read current options */
 259         stm32x_read_options(bank);
 260
 261         /* unlock flash registers */
 262         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 263         if (retval != ERROR_OK)
 264                 return retval;
 265
 266         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 267         if (retval != ERROR_OK)
 268                 return retval;
 269
 270         /* unlock option flash registers */
 271         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 272         if (retval != ERROR_OK)
 273                 return retval;
 274         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 275         if (retval != ERROR_OK)
 276                 return retval;
 277
 278         /* erase option bytes */
 279         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 280         if (retval != ERROR_OK)
 281                 return retval;
 282         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 283         if (retval != ERROR_OK)
 284                 return retval;
 285
 286         retval = stm32x_wait_status_busy(bank, 10);
 287         if (retval != ERROR_OK)
 288                 return retval;
 289
 290         /* clear readout protection and complementary option bytes
 291          * this will also force a device unlock if set */
 292         stm32x_info->option_bytes.RDP = 0x5AA5;
 293
 294         return ERROR_OK;
 295 }
 296
 297 static int stm32x_write_options(struct flash_bank *bank)
 298 {
 299         struct stm32x_flash_bank *stm32x_info = NULL;
 300         struct target *target = bank->target;
 301
 302         stm32x_info = bank->driver_priv;
 303
 304         /* unlock flash registers */
 305         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 306         if (retval != ERROR_OK)
 307                 return retval;
 308         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 309         if (retval != ERROR_OK)
 310                 return retval;
 311
 312         /* unlock option flash registers */
 313         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 314         if (retval != ERROR_OK)
 315                 return retval;
 316         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 317         if (retval != ERROR_OK)
 318                 return retval;
 319
 320         /* program option bytes */
 321         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 322         if (retval != ERROR_OK)
 323                 return retval;
 324
 325         /* write user option byte */
 326         retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
 327         if (retval != ERROR_OK)
 328                 return retval;
 329
 330         retval = stm32x_wait_status_busy(bank, 10);
 331         if (retval != ERROR_OK)
 332                 return retval;
 333
 334         /* write protection byte 1 */
 335         retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
 336         if (retval != ERROR_OK)
 337                 return retval;
 338
 339         retval = stm32x_wait_status_busy(bank, 10);
 340         if (retval != ERROR_OK)
 341                 return retval;
 342
 343         /* write protection byte 2 */
 344         retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
 345         if (retval != ERROR_OK)
 346                 return retval;
 347
 348         retval = stm32x_wait_status_busy(bank, 10);
 349         if (retval != ERROR_OK)
 350                 return retval;
 351
 352         /* write protection byte 3 */
 353         retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
 354         if (retval != ERROR_OK)
 355                 return retval;
 356
 357         retval = stm32x_wait_status_busy(bank, 10);
 358         if (retval != ERROR_OK)
 359                 return retval;
 360
 361         /* write protection byte 4 */
 362         retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
 363         if (retval != ERROR_OK)
 364                 return retval;
 365
 366         retval = stm32x_wait_status_busy(bank, 10);
 367         if (retval != ERROR_OK)
 368                 return retval;
 369
 370         /* write readout protection bit */
 371         retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
 372         if (retval != ERROR_OK)
 373                 return retval;
 374
 375         retval = stm32x_wait_status_busy(bank, 10);
 376         if (retval != ERROR_OK)
 377                 return retval;
 378
 379         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 380         if (retval != ERROR_OK)
 381                 return retval;
 382
 383         return ERROR_OK;
 384 }
 385
 386 static int stm32x_protect_check(struct flash_bank *bank)
 387 {
 388         struct target *target = bank->target;
 389         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 390
 391         uint32_t protection;
 392         int i, s;
 393         int num_bits;
 394         int set;
 395
 396         if (target->state != TARGET_HALTED)
 397         {
 398                 LOG_ERROR("Target not halted");
 399                 return ERROR_TARGET_NOT_HALTED;
 400         }
 401
 402         int retval = stm32x_check_operation_supported(bank);
 403         if (ERROR_OK != retval)
 404                 return retval;
 405
 406         /* medium density - each bit refers to a 4bank protection
 407          * high density - each bit refers to a 2bank protection */
 408         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 409         if (retval != ERROR_OK)
 410                 return retval;
 411
 412         /* medium density - each protection bit is for 4 * 1K pages
 413          * high density - each protection bit is for 2 * 2K pages */
 414         num_bits = (bank->num_sectors / stm32x_info->ppage_size);
 415
 416         if (stm32x_info->ppage_size == 2)
 417         {
 418                 /* high density flash/connectivity line protection */
 419
 420                 set = 1;
 421
 422                 if (protection & (1 << 31))
 423                         set = 0;
 424
 425                 /* bit 31 controls sector 62 - 255 protection for high density
 426                  * bit 31 controls sector 62 - 127 protection for connectivity line */
 427                 for (s = 62; s < bank->num_sectors; s++)
 428                 {
 429                         bank->sectors[s].is_protected = set;
 430                 }
 431
 432                 if (bank->num_sectors > 61)
 433                         num_bits = 31;
 434
 435                 for (i = 0; i < num_bits; i++)
 436                 {
 437                         set = 1;
 438
 439                         if (protection & (1 << i))
 440                                 set = 0;
 441
 442                         for (s = 0; s < stm32x_info->ppage_size; s++)
 443                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 444                 }
 445         }
 446         else
 447         {
 448                 /* low/medium density flash protection */
 449                 for (i = 0; i < num_bits; i++)
 450                 {
 451                         set = 1;
 452
 453                         if (protection & (1 << i))
 454                                 set = 0;
 455
 456                         for (s = 0; s < stm32x_info->ppage_size; s++)
 457                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 458                 }
 459         }
 460
 461         return ERROR_OK;
 462 }
 463
 464 static int stm32x_erase(struct flash_bank *bank, int first, int last)
 465 {
 466         struct target *target = bank->target;
 467         int i;
 468
 469         if (bank->target->state != TARGET_HALTED)
 470         {
 471                 LOG_ERROR("Target not halted");
 472                 return ERROR_TARGET_NOT_HALTED;
 473         }
 474
 475         if ((first == 0) && (last == (bank->num_sectors - 1)))
 476         {
 477                 return stm32x_mass_erase(bank);
 478         }
 479
 480         /* unlock flash registers */
 481         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 482         if (retval != ERROR_OK)
 483                 return retval;
 484         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 485         if (retval != ERROR_OK)
 486                 return retval;
 487
 488         for (i = first; i <= last; i++)
 489         {
 490                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 491                 if (retval != ERROR_OK)
 492                         return retval;
 493                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 494                                 bank->base + bank->sectors[i].offset);
 495                 if (retval != ERROR_OK)
 496                         return retval;
 497                 retval = target_write_u32(target,
 498                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 499                 if (retval != ERROR_OK)
 500                         return retval;
 501
 502                 retval = stm32x_wait_status_busy(bank, 100);
 503                 if (retval != ERROR_OK)
 504                         return retval;
 505
 506                 bank->sectors[i].is_erased = 1;
 507         }
 508
 509         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 510         if (retval != ERROR_OK)
 511                 return retval;
 512
 513         return ERROR_OK;
 514 }
 515
 516 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
 517 {
 518         struct stm32x_flash_bank *stm32x_info = NULL;
 519         struct target *target = bank->target;
 520         uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 521         int i, reg, bit;
 522         int status;
 523         uint32_t protection;
 524
 525         stm32x_info = bank->driver_priv;
 526
 527         if (target->state != TARGET_HALTED)
 528         {
 529                 LOG_ERROR("Target not halted");
 530                 return ERROR_TARGET_NOT_HALTED;
 531         }
 532
 533         int retval = stm32x_check_operation_supported(bank);
 534         if (ERROR_OK != retval)
 535                 return retval;
 536
 537         if ((first % stm32x_info->ppage_size) != 0)
 538         {
 539                 LOG_WARNING("aligned start protect sector to a %d sector boundary",
 540                                 stm32x_info->ppage_size);
 541                 first = first - (first % stm32x_info->ppage_size);
 542         }
 543         if (((last + 1) % stm32x_info->ppage_size) != 0)
 544         {
 545                 LOG_WARNING("aligned end protect sector to a %d sector boundary",
 546                                 stm32x_info->ppage_size);
 547                 last++;
 548                 last = last - (last % stm32x_info->ppage_size);
 549                 last--;
 550         }
 551
 552         /* medium density - each bit refers to a 4bank protection
 553          * high density - each bit refers to a 2bank protection */
 554         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 555         if (retval != ERROR_OK)
 556                 return retval;
 557
 558         prot_reg[0] = (uint16_t)protection;
 559         prot_reg[1] = (uint16_t)(protection >> 8);
 560         prot_reg[2] = (uint16_t)(protection >> 16);
 561         prot_reg[3] = (uint16_t)(protection >> 24);
 562
 563         if (stm32x_info->ppage_size == 2)
 564         {
 565                 /* high density flash */
 566
 567                 /* bit 7 controls sector 62 - 255 protection */
 568                 if (last > 61)
 569                 {
 570                         if (set)
 571                                 prot_reg[3] &= ~(1 << 7);
 572                         else
 573                                 prot_reg[3] |= (1 << 7);
 574                 }
 575
 576                 if (first > 61)
 577                         first = 62;
 578                 if (last > 61)
 579                         last = 61;
 580
 581                 for (i = first; i <= last; i++)
 582                 {
 583                         reg = (i / stm32x_info->ppage_size) / 8;
 584                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 585
 586                         if (set)
 587                                 prot_reg[reg] &= ~(1 << bit);
 588                         else
 589                                 prot_reg[reg] |= (1 << bit);
 590                 }
 591         }
 592         else
 593         {
 594                 /* medium density flash */
 595                 for (i = first; i <= last; i++)
 596                 {
 597                         reg = (i / stm32x_info->ppage_size) / 8;
 598                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 599
 600                         if (set)
 601                                 prot_reg[reg] &= ~(1 << bit);
 602                         else
 603                                 prot_reg[reg] |= (1 << bit);
 604                 }
 605         }
 606
 607         if ((status = stm32x_erase_options(bank)) != ERROR_OK)
 608                 return status;
 609
 610         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 611         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 612         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 613         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 614
 615         return stm32x_write_options(bank);
 616 }
 617
 618 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 619                 uint32_t offset, uint32_t count)
 620 {
 621         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 622         struct target *target = bank->target;
 623         uint32_t buffer_size = 16384;
 624         struct working_area *source;
 625         uint32_t address = bank->base + offset;
 626         struct reg_param reg_params[4];
 627         struct armv7m_algorithm armv7m_info;
 628         int retval = ERROR_OK;
 629
 630         /* see contib/loaders/flash/stm32x.s for src */
 631
 632         static const uint8_t stm32x_flash_write_code[] = {
 633                                                                         /* #define STM32_FLASH_CR_OFFSET        0x10 */
 634                                                                         /* #define STM32_FLASH_SR_OFFSET        0x0C */
 635                                                                         /* write: */
 636                 0x08, 0x4c,                                     /* ldr  r4, STM32_FLASH_BASE */
 637                 0x1c, 0x44,                                     /* add  r4, r3 */
 638                                                                         /* write_half_word: */
 639                 0x01, 0x23,                                     /* movs r3, #0x01 */
 640                 0x23, 0x61,                                     /* str  r3, [r4, #STM32_FLASH_CR_OFFSET] */
 641                 0x30, 0xf8, 0x02, 0x3b,         /* ldrh r3, [r0], #0x02 */
 642                 0x21, 0xf8, 0x02, 0x3b,         /* strh r3, [r1], #0x02 */
 643                                                                         /* busy: */
 644                 0xe3, 0x68,                                     /* ldr  r3, [r4, #STM32_FLASH_SR_OFFSET] */
 645                 0x13, 0xf0, 0x01, 0x0f,         /* tst  r3, #0x01 */
 646                 0xfb, 0xd0,                                     /* beq  busy */
 647                 0x13, 0xf0, 0x14, 0x0f,         /* tst  r3, #0x14 */
 648                 0x01, 0xd1,                                     /* bne  exit */
 649                 0x01, 0x3a,                                     /* subs r2, r2, #0x01 */
 650                 0xf0, 0xd1,                                     /* bne  write_half_word */
 651                                                                         /* exit: */
 652                 0x00, 0xbe,                                     /* bkpt #0x00 */
 653                 0x00, 0x20, 0x02, 0x40,         /* STM32_FLASH_BASE: .word 0x40022000 */
 654         };
 655
 656         /* flash write code */
 657         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 658                         &stm32x_info->write_algorithm) != ERROR_OK)
 659         {
 660                 LOG_WARNING("no working area available, can't do block memory writes");
 661                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 662         };
 663
 664         if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
 665                         sizeof(stm32x_flash_write_code),
 666                         (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
 667                 return retval;
 668
 669         /* memory buffer */
 670         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
 671         {
 672                 buffer_size /= 2;
 673                 if (buffer_size <= 256)
 674                 {
 675                         /* if we already allocated the writing code, but failed to get a
 676                          * buffer, free the algorithm */
 677                         if (stm32x_info->write_algorithm)
 678                                 target_free_working_area(target, stm32x_info->write_algorithm);
 679
 680                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 681                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 682                 }
 683         };
 684
 685         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 686         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 687
 688         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 689         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 690         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 691         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT);
 692
 693         while (count > 0)
 694         {
 695                 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
 696                                 (buffer_size / 2) : count;
 697
 698                 if ((retval = target_write_buffer(target, source->address,
 699                                 thisrun_count * 2, buffer)) != ERROR_OK)
 700                         break;
 701
 702                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 703                 buf_set_u32(reg_params[1].value, 0, 32, address);
 704                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
 705                 buf_set_u32(reg_params[3].value, 0, 32, stm32x_info->register_base - FLASH_REG_BASE_B0);
 706
 707                 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
 708                                 stm32x_info->write_algorithm->address,
 709                                 0,
 710                                 10000, &armv7m_info)) != ERROR_OK)
 711                 {
 712                         LOG_ERROR("error executing stm32x flash write algorithm");
 713                         break;
 714                 }
 715
 716                 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
 717                 {
 718                         LOG_ERROR("flash memory not erased before writing");
 719                         /* Clear but report errors */
 720                         target_write_u32(target, STM32_FLASH_SR_B0, FLASH_PGERR);
 721                         retval = ERROR_FAIL;
 722                         break;
 723                 }
 724
 725                 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
 726                 {
 727                         LOG_ERROR("flash memory write protected");
 728                         /* Clear but report errors */
 729                         target_write_u32(target, STM32_FLASH_SR_B0, FLASH_WRPRTERR);
 730                         retval = ERROR_FAIL;
 731                         break;
 732                 }
 733
 734                 buffer += thisrun_count * 2;
 735                 address += thisrun_count * 2;
 736                 count -= thisrun_count;
 737         }
 738
 739         target_free_working_area(target, source);
 740         target_free_working_area(target, stm32x_info->write_algorithm);
 741
 742         destroy_reg_param(&reg_params[0]);
 743         destroy_reg_param(&reg_params[1]);
 744         destroy_reg_param(&reg_params[2]);
 745         destroy_reg_param(&reg_params[3]);
 746
 747         return retval;
 748 }
 749
 750 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
 751                 uint32_t offset, uint32_t count)
 752 {
 753         struct target *target = bank->target;
 754         uint32_t words_remaining = (count / 2);
 755         uint32_t bytes_remaining = (count & 0x00000001);
 756         uint32_t address = bank->base + offset;
 757         uint32_t bytes_written = 0;
 758         int retval;
 759
 760         if (bank->target->state != TARGET_HALTED)
 761         {
 762                 LOG_ERROR("Target not halted");
 763                 return ERROR_TARGET_NOT_HALTED;
 764         }
 765
 766         if (offset & 0x1)
 767         {
 768                 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 769                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 770         }
 771
 772         /* unlock flash registers */
 773         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 774         if (retval != ERROR_OK)
 775                 return retval;
 776         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 777         if (retval != ERROR_OK)
 778                 return retval;
 779
 780         /* multiple half words (2-byte) to be programmed? */
 781         if (words_remaining > 0)
 782         {
 783                 /* try using a block write */
 784                 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
 785                 {
 786                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 787                         {
 788                                 /* if block write failed (no sufficient working area),
 789                                  * we use normal (slow) single dword accesses */
 790                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 791                         }
 792                 }
 793                 else
 794                 {
 795                         buffer += words_remaining * 2;
 796                         address += words_remaining * 2;
 797                         words_remaining = 0;
 798                 }
 799         }
 800
 801         if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
 802                 return retval;
 803
 804         while (words_remaining > 0)
 805         {
 806                 uint16_t value;
 807                 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
 808
 809                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 810                 if (retval != ERROR_OK)
 811                         return retval;
 812                 retval = target_write_u16(target, address, value);
 813                 if (retval != ERROR_OK)
 814                         return retval;
 815
 816                 retval = stm32x_wait_status_busy(bank, 5);
 817                 if (retval != ERROR_OK)
 818                         return retval;
 819
 820                 bytes_written += 2;
 821                 words_remaining--;
 822                 address += 2;
 823         }
 824
 825         if (bytes_remaining)
 826         {
 827                 uint16_t value = 0xffff;
 828                 memcpy(&value, buffer + bytes_written, bytes_remaining);
 829
 830                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 831                 if (retval != ERROR_OK)
 832                         return retval;
 833                 retval = target_write_u16(target, address, value);
 834                 if (retval != ERROR_OK)
 835                         return retval;
 836
 837                 retval = stm32x_wait_status_busy(bank, 5);
 838                 if (retval != ERROR_OK)
 839                         return retval;
 840         }
 841
 842         return target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 843 }
 844
 845 static int stm32x_probe(struct flash_bank *bank)
 846 {
 847         struct target *target = bank->target;
 848         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 849         int i;
 850         uint16_t num_pages;
 851         uint32_t device_id;
 852         int page_size;
 853         uint32_t base_address = 0x08000000;
 854
 855         stm32x_info->probed = 0;
 856         stm32x_info->register_base = FLASH_REG_BASE_B0;
 857
 858         /* read stm32 device id register */
 859         int retval = target_read_u32(target, 0xE0042000, &device_id);
 860         if (retval != ERROR_OK)
 861                 return retval;
 862         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 863
 864         /* get flash size from target. */
 865         retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
 866         if (retval != ERROR_OK)
 867         {
 868                 LOG_WARNING("failed reading flash size, default to max target family");
 869                 /* failed reading flash size, default to max target family */
 870                 num_pages = 0xffff;
 871         }
 872
 873         if ((device_id & 0x7ff) == 0x410)
 874         {
 875                 /* medium density - we have 1k pages
 876                  * 4 pages for a protection area */
 877                 page_size = 1024;
 878                 stm32x_info->ppage_size = 4;
 879
 880                 /* check for early silicon */
 881                 if (num_pages == 0xffff)
 882                 {
 883                         /* number of sectors incorrect on revA */
 884                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
 885                         num_pages = 128;
 886                 }
 887         }
 888         else if ((device_id & 0x7ff) == 0x412)
 889         {
 890                 /* low density - we have 1k pages
 891                  * 4 pages for a protection area */
 892                 page_size = 1024;
 893                 stm32x_info->ppage_size = 4;
 894
 895                 /* check for early silicon */
 896                 if (num_pages == 0xffff)
 897                 {
 898                         /* number of sectors incorrect on revA */
 899                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
 900                         num_pages = 32;
 901                 }
 902         }
 903         else if ((device_id & 0x7ff) == 0x414)
 904         {
 905                 /* high density - we have 2k pages
 906                  * 2 pages for a protection area */
 907                 page_size = 2048;
 908                 stm32x_info->ppage_size = 2;
 909
 910                 /* check for early silicon */
 911                 if (num_pages == 0xffff)
 912                 {
 913                         /* number of sectors incorrect on revZ */
 914                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
 915                         num_pages = 512;
 916                 }
 917         }
 918         else if ((device_id & 0x7ff) == 0x418)
 919         {
 920                 /* connectivity line density - we have 2k pages
 921                  * 2 pages for a protection area */
 922                 page_size = 2048;
 923                 stm32x_info->ppage_size = 2;
 924
 925                 /* check for early silicon */
 926                 if (num_pages == 0xffff)
 927                 {
 928                         /* number of sectors incorrect on revZ */
 929                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
 930                         num_pages = 256;
 931                 }
 932         }
 933         else if ((device_id & 0x7ff) == 0x420)
 934         {
 935                 /* value line density - we have 1k pages
 936                  * 4 pages for a protection area */
 937                 page_size = 1024;
 938                 stm32x_info->ppage_size = 4;
 939
 940                 /* check for early silicon */
 941                 if (num_pages == 0xffff)
 942                 {
 943                         /* number of sectors may be incorrrect on early silicon */
 944                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
 945                         num_pages = 128;
 946                 }
 947         }
 948         else if ((device_id & 0x7ff) == 0x428)
 949         {
 950                 /* value line density - we have 1k pages
 951                  * 4 pages for a protection area */
 952                 page_size = 2048;
 953                 stm32x_info->ppage_size = 4;
 954
 955                 /* check for early silicon */
 956                 if (num_pages == 0xffff)
 957                 {
 958                         /* number of sectors may be incorrrect on early silicon */
 959                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
 960                         num_pages = 128;
 961                 }
 962         }
 963
 964         else if ((device_id & 0x7ff) == 0x430)
 965         {
 966                 /* xl line density - we have 2k pages
 967                  * 2 pages for a protection area */
 968                 page_size = 2048;
 969                 stm32x_info->ppage_size = 2;
 970                 stm32x_info->has_dual_banks = true;
 971
 972                 /* check for early silicon */
 973                 if (num_pages == 0xffff)
 974                 {
 975                         /* number of sectors may be incorrrect on early silicon */
 976                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
 977                         num_pages = 1024;
 978                 }
 979
 980                 /* split reported size into matching bank */
 981                 if (bank->base != 0x08080000)
 982                 {
 983                         /* bank 0 will be fixed 512k */
 984                         num_pages = 512;
 985                 }
 986                 else
 987                 {
 988                         num_pages -= 512;
 989                         /* bank1 also uses a register offset */
 990                         stm32x_info->register_base = FLASH_REG_BASE_B1;
 991                         base_address = 0x08080000;
 992                 }
 993         }
 994         else
 995         {
 996                 LOG_WARNING("Cannot identify target as a STM32 family.");
 997                 return ERROR_FAIL;
 998         }
 999
1000         LOG_INFO("flash size = %dkbytes", num_pages);
1001
1002         /* calculate numbers of pages */
1003         num_pages /= (page_size / 1024);
1004
1005         if (bank->sectors)
1006         {
1007                 free(bank->sectors);
1008                 bank->sectors = NULL;
1009         }
1010
1011         bank->base = base_address;
1012         bank->size = (num_pages * page_size);
1013         bank->num_sectors = num_pages;
1014         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1015
1016         for (i = 0; i < num_pages; i++)
1017         {
1018                 bank->sectors[i].offset = i * page_size;
1019                 bank->sectors[i].size = page_size;
1020                 bank->sectors[i].is_erased = -1;
1021                 bank->sectors[i].is_protected = 1;
1022         }
1023
1024         stm32x_info->probed = 1;
1025
1026         return ERROR_OK;
1027 }
1028
1029 static int stm32x_auto_probe(struct flash_bank *bank)
1030 {
1031         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1032         if (stm32x_info->probed)
1033                 return ERROR_OK;
1034         return stm32x_probe(bank);
1035 }
1036
1037 #if 0
1038 COMMAND_HANDLER(stm32x_handle_part_id_command)
1039 {
1040         return ERROR_OK;
1041 }
1042 #endif
1043
1044 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1045 {
1046         struct target *target = bank->target;
1047         uint32_t device_id;
1048         int printed;
1049
1050         /* read stm32 device id register */
1051         int retval = target_read_u32(target, 0xE0042000, &device_id);
1052         if (retval != ERROR_OK)
1053                 return retval;
1054
1055         if ((device_id & 0x7ff) == 0x410)
1056         {
1057                 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1058                 buf += printed;
1059                 buf_size -= printed;
1060
1061                 switch (device_id >> 16)
1062                 {
1063                         case 0x0000:
1064                                 snprintf(buf, buf_size, "A");
1065                                 break;
1066
1067                         case 0x2000:
1068                                 snprintf(buf, buf_size, "B");
1069                                 break;
1070
1071                         case 0x2001:
1072                                 snprintf(buf, buf_size, "Z");
1073                                 break;
1074
1075                         case 0x2003:
1076                                 snprintf(buf, buf_size, "Y");
1077                                 break;
1078
1079                         default:
1080                                 snprintf(buf, buf_size, "unknown");
1081                                 break;
1082                 }
1083         }
1084         else if ((device_id & 0x7ff) == 0x412)
1085         {
1086                 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1087                 buf += printed;
1088                 buf_size -= printed;
1089
1090                 switch (device_id >> 16)
1091                 {
1092                         case 0x1000:
1093                                 snprintf(buf, buf_size, "A");
1094                                 break;
1095
1096                         default:
1097                                 snprintf(buf, buf_size, "unknown");
1098                                 break;
1099                 }
1100         }
1101         else if ((device_id & 0x7ff) == 0x414)
1102         {
1103                 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1104                 buf += printed;
1105                 buf_size -= printed;
1106
1107                 switch (device_id >> 16)
1108                 {
1109                         case 0x1000:
1110                                 snprintf(buf, buf_size, "A");
1111                                 break;
1112
1113                         case 0x1001:
1114                                 snprintf(buf, buf_size, "Z");
1115                                 break;
1116
1117                         default:
1118                                 snprintf(buf, buf_size, "unknown");
1119                                 break;
1120                 }
1121         }
1122         else if ((device_id & 0x7ff) == 0x418)
1123         {
1124                 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1125                 buf += printed;
1126                 buf_size -= printed;
1127
1128                 switch (device_id >> 16)
1129                 {
1130                         case 0x1000:
1131                                 snprintf(buf, buf_size, "A");
1132                                 break;
1133
1134                         case 0x1001:
1135                                 snprintf(buf, buf_size, "Z");
1136                                 break;
1137
1138                         default:
1139                                 snprintf(buf, buf_size, "unknown");
1140                                 break;
1141                 }
1142         }
1143         else if ((device_id & 0x7ff) == 0x420)
1144         {
1145                 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1146                 buf += printed;
1147                 buf_size -= printed;
1148
1149                 switch (device_id >> 16)
1150                 {
1151                         case 0x1000:
1152                                 snprintf(buf, buf_size, "A");
1153                                 break;
1154
1155                         case 0x1001:
1156                                 snprintf(buf, buf_size, "Z");
1157                                 break;
1158
1159                         default:
1160                                 snprintf(buf, buf_size, "unknown");
1161                                 break;
1162                 }
1163         }
1164         else if ((device_id & 0x7ff) == 0x428)
1165         {
1166                 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1167                 buf += printed;
1168                 buf_size -= printed;
1169
1170                 switch (device_id >> 16)
1171                 {
1172                         case 0x1000:
1173                                 snprintf(buf, buf_size, "A");
1174                                 break;
1175
1176                         case 0x1001:
1177                                 snprintf(buf, buf_size, "Z");
1178                                 break;
1179
1180                         default:
1181                                 snprintf(buf, buf_size, "unknown");
1182                                 break;
1183                 }
1184         }
1185         else if ((device_id & 0x7ff) == 0x430)
1186         {
1187                 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1188                 buf += printed;
1189                 buf_size -= printed;
1190
1191                 switch (device_id >> 16)
1192                 {
1193                         case 0x1000:
1194                                 snprintf(buf, buf_size, "A");
1195                                 break;
1196
1197                         default:
1198                                 snprintf(buf, buf_size, "unknown");
1199                                 break;
1200                 }
1201         }
1202         else
1203         {
1204                 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1205                 return ERROR_FAIL;
1206         }
1207
1208         return ERROR_OK;
1209 }
1210
1211 COMMAND_HANDLER(stm32x_handle_lock_command)
1212 {
1213         struct target *target = NULL;
1214         struct stm32x_flash_bank *stm32x_info = NULL;
1215
1216         if (CMD_ARGC < 1)
1217         {
1218                 command_print(CMD_CTX, "stm32x lock <bank>");
1219                 return ERROR_OK;
1220         }
1221
1222         struct flash_bank *bank;
1223         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1224         if (ERROR_OK != retval)
1225                 return retval;
1226
1227         stm32x_info = bank->driver_priv;
1228
1229         target = bank->target;
1230
1231         if (target->state != TARGET_HALTED)
1232         {
1233                 LOG_ERROR("Target not halted");
1234                 return ERROR_TARGET_NOT_HALTED;
1235         }
1236
1237         retval = stm32x_check_operation_supported(bank);
1238         if (ERROR_OK != retval)
1239                 return retval;
1240
1241         if (stm32x_erase_options(bank) != ERROR_OK)
1242         {
1243                 command_print(CMD_CTX, "stm32x failed to erase options");
1244                 return ERROR_OK;
1245         }
1246
1247         /* set readout protection */
1248         stm32x_info->option_bytes.RDP = 0;
1249
1250         if (stm32x_write_options(bank) != ERROR_OK)
1251         {
1252                 command_print(CMD_CTX, "stm32x failed to lock device");
1253                 return ERROR_OK;
1254         }
1255
1256         command_print(CMD_CTX, "stm32x locked");
1257
1258         return ERROR_OK;
1259 }
1260
1261 COMMAND_HANDLER(stm32x_handle_unlock_command)
1262 {
1263         struct target *target = NULL;
1264
1265         if (CMD_ARGC < 1)
1266         {
1267                 command_print(CMD_CTX, "stm32x unlock <bank>");
1268                 return ERROR_OK;
1269         }
1270
1271         struct flash_bank *bank;
1272         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1273         if (ERROR_OK != retval)
1274                 return retval;
1275
1276         target = bank->target;
1277
1278         if (target->state != TARGET_HALTED)
1279         {
1280                 LOG_ERROR("Target not halted");
1281                 return ERROR_TARGET_NOT_HALTED;
1282         }
1283
1284         retval = stm32x_check_operation_supported(bank);
1285         if (ERROR_OK != retval)
1286                 return retval;
1287
1288         if (stm32x_erase_options(bank) != ERROR_OK)
1289         {
1290                 command_print(CMD_CTX, "stm32x failed to unlock device");
1291                 return ERROR_OK;
1292         }
1293
1294         if (stm32x_write_options(bank) != ERROR_OK)
1295         {
1296                 command_print(CMD_CTX, "stm32x failed to lock device");
1297                 return ERROR_OK;
1298         }
1299
1300         command_print(CMD_CTX, "stm32x unlocked.\n"
1301                         "INFO: a reset or power cycle is required "
1302                         "for the new settings to take effect.");
1303
1304         return ERROR_OK;
1305 }
1306
1307 COMMAND_HANDLER(stm32x_handle_options_read_command)
1308 {
1309         uint32_t optionbyte;
1310         struct target *target = NULL;
1311         struct stm32x_flash_bank *stm32x_info = NULL;
1312
1313         if (CMD_ARGC < 1)
1314         {
1315                 command_print(CMD_CTX, "stm32x options_read <bank>");
1316                 return ERROR_OK;
1317         }
1318
1319         struct flash_bank *bank;
1320         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1321         if (ERROR_OK != retval)
1322                 return retval;
1323
1324         stm32x_info = bank->driver_priv;
1325
1326         target = bank->target;
1327
1328         if (target->state != TARGET_HALTED)
1329         {
1330                 LOG_ERROR("Target not halted");
1331                 return ERROR_TARGET_NOT_HALTED;
1332         }
1333
1334         retval = stm32x_check_operation_supported(bank);
1335         if (ERROR_OK != retval)
1336                 return retval;
1337
1338         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1339         if (retval != ERROR_OK)
1340                 return retval;
1341         command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1342
1343         if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1344                 command_print(CMD_CTX, "Option Byte Complement Error");
1345
1346         if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1347                 command_print(CMD_CTX, "Readout Protection On");
1348         else
1349                 command_print(CMD_CTX, "Readout Protection Off");
1350
1351         if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1352                 command_print(CMD_CTX, "Software Watchdog");
1353         else
1354                 command_print(CMD_CTX, "Hardware Watchdog");
1355
1356         if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1357                 command_print(CMD_CTX, "Stop: No reset generated");
1358         else
1359                 command_print(CMD_CTX, "Stop: Reset generated");
1360
1361         if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1362                 command_print(CMD_CTX, "Standby: No reset generated");
1363         else
1364                 command_print(CMD_CTX, "Standby: Reset generated");
1365
1366         if (stm32x_info->has_dual_banks)
1367         {
1368                 if (buf_get_u32((uint8_t*)&optionbyte, OPT_BFB2, 1))
1369                         command_print(CMD_CTX, "Boot: Bank 0");
1370                 else
1371                         command_print(CMD_CTX, "Boot: Bank 1");
1372         }
1373
1374         return ERROR_OK;
1375 }
1376
1377 COMMAND_HANDLER(stm32x_handle_options_write_command)
1378 {
1379         struct target *target = NULL;
1380         struct stm32x_flash_bank *stm32x_info = NULL;
1381         uint16_t optionbyte = 0xF8;
1382
1383         if (CMD_ARGC < 4)
1384         {
1385                 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> "
1386                                 "<RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP> <BOOT0 | BOOT1>");
1387                 return ERROR_OK;
1388         }
1389
1390         struct flash_bank *bank;
1391         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1392         if (ERROR_OK != retval)
1393                 return retval;
1394
1395         stm32x_info = bank->driver_priv;
1396
1397         target = bank->target;
1398
1399         if (target->state != TARGET_HALTED)
1400         {
1401                 LOG_ERROR("Target not halted");
1402                 return ERROR_TARGET_NOT_HALTED;
1403         }
1404
1405         retval = stm32x_check_operation_supported(bank);
1406         if (ERROR_OK != retval)
1407                 return retval;
1408
1409         /* REVISIT: ignores some options which we will display...
1410          * and doesn't insist on the specified syntax.
1411          */
1412
1413         /* OPT_RDWDGSW */
1414         if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1415         {
1416                 optionbyte |= (1 << 0);
1417         }
1418         else    /* REVISIT must be "HWWDG" then ... */
1419         {
1420                 optionbyte &= ~(1 << 0);
1421         }
1422
1423         /* OPT_RDRSTSTOP */
1424         if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
1425         {
1426                 optionbyte |= (1 << 1);
1427         }
1428         else    /* REVISIT must be "RSTSTNDBY" then ... */
1429         {
1430                 optionbyte &= ~(1 << 1);
1431         }
1432
1433         /* OPT_RDRSTSTDBY */
1434         if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
1435         {
1436                 optionbyte |= (1 << 2);
1437         }
1438         else    /* REVISIT must be "RSTSTOP" then ... */
1439         {
1440                 optionbyte &= ~(1 << 2);
1441         }
1442
1443         if (CMD_ARGC > 4 && stm32x_info->has_dual_banks)
1444         {
1445                 /* OPT_BFB2 */
1446                 if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
1447                 {
1448                         optionbyte |= (1 << 3);
1449                 }
1450                 else
1451                 {
1452                         optionbyte &= ~(1 << 3);
1453                 }
1454         }
1455
1456         if (stm32x_erase_options(bank) != ERROR_OK)
1457         {
1458                 command_print(CMD_CTX, "stm32x failed to erase options");
1459                 return ERROR_OK;
1460         }
1461
1462         stm32x_info->option_bytes.user_options = optionbyte;
1463
1464         if (stm32x_write_options(bank) != ERROR_OK)
1465         {
1466                 command_print(CMD_CTX, "stm32x failed to write options");
1467                 return ERROR_OK;
1468         }
1469
1470         command_print(CMD_CTX, "stm32x write options complete.\n"
1471                                 "INFO: a reset or power cycle is required "
1472                                 "for the new settings to take effect.");
1473
1474         return ERROR_OK;
1475 }
1476
1477 static int stm32x_mass_erase(struct flash_bank *bank)
1478 {
1479         struct target *target = bank->target;
1480
1481         if (target->state != TARGET_HALTED)
1482         {
1483                 LOG_ERROR("Target not halted");
1484                 return ERROR_TARGET_NOT_HALTED;
1485         }
1486
1487         /* unlock option flash registers */
1488         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1489         if (retval != ERROR_OK)
1490                 return retval;
1491         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1492         if (retval != ERROR_OK)
1493                 return retval;
1494
1495         /* mass erase flash memory */
1496         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1497         if (retval != ERROR_OK)
1498                 return retval;
1499         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER | FLASH_STRT);
1500         if (retval != ERROR_OK)
1501                 return retval;
1502
1503         retval = stm32x_wait_status_busy(bank, 100);
1504         if (retval != ERROR_OK)
1505                 return retval;
1506
1507         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1508         if (retval != ERROR_OK)
1509                 return retval;
1510
1511         return ERROR_OK;
1512 }
1513
1514 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1515 {
1516         int i;
1517
1518         if (CMD_ARGC < 1)
1519         {
1520                 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1521                 return ERROR_OK;
1522         }
1523
1524         struct flash_bank *bank;
1525         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1526         if (ERROR_OK != retval)
1527                 return retval;
1528
1529         retval = stm32x_mass_erase(bank);
1530         if (retval == ERROR_OK)
1531         {
1532                 /* set all sectors as erased */
1533                 for (i = 0; i < bank->num_sectors; i++)
1534                 {
1535                         bank->sectors[i].is_erased = 1;
1536                 }
1537
1538                 command_print(CMD_CTX, "stm32x mass erase complete");
1539         }
1540         else
1541         {
1542                 command_print(CMD_CTX, "stm32x mass erase failed");
1543         }
1544
1545         return retval;
1546 }
1547
1548 static const struct command_registration stm32x_exec_command_handlers[] = {
1549         {
1550                 .name = "lock",
1551                 .handler = stm32x_handle_lock_command,
1552                 .mode = COMMAND_EXEC,
1553                 .usage = "bank_id",
1554                 .help = "Lock entire flash device.",
1555         },
1556         {
1557                 .name = "unlock",
1558                 .handler = stm32x_handle_unlock_command,
1559                 .mode = COMMAND_EXEC,
1560                 .usage = "bank_id",
1561                 .help = "Unlock entire protected flash device.",
1562         },
1563         {
1564                 .name = "mass_erase",
1565                 .handler = stm32x_handle_mass_erase_command,
1566                 .mode = COMMAND_EXEC,
1567                 .usage = "bank_id",
1568                 .help = "Erase entire flash device.",
1569         },
1570         {
1571                 .name = "options_read",
1572                 .handler = stm32x_handle_options_read_command,
1573                 .mode = COMMAND_EXEC,
1574                 .usage = "bank_id",
1575                 .help = "Read and display device option byte.",
1576         },
1577         {
1578                 .name = "options_write",
1579                 .handler = stm32x_handle_options_write_command,
1580                 .mode = COMMAND_EXEC,
1581                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1582                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1583                         "('RSTSTOP'|'NORSTSTOP')",
1584                 .help = "Replace bits in device option byte.",
1585         },
1586         COMMAND_REGISTRATION_DONE
1587 };
1588
1589 static const struct command_registration stm32x_command_handlers[] = {
1590         {
1591                 .name = "stm32f1x",
1592                 .mode = COMMAND_ANY,
1593                 .help = "stm32f1x flash command group",
1594                 .chain = stm32x_exec_command_handlers,
1595         },
1596         COMMAND_REGISTRATION_DONE
1597 };
1598
1599 struct flash_driver stm32f1x_flash = {
1600         .name = "stm32f1x",
1601         .commands = stm32x_command_handlers,
1602         .flash_bank_command = stm32x_flash_bank_command,
1603         .erase = stm32x_erase,
1604         .protect = stm32x_protect,
1605         .write = stm32x_write,
1606         .read = default_flash_read,
1607         .probe = stm32x_probe,
1608         .auto_probe = stm32x_auto_probe,
1609         .erase_check = default_flash_mem_blank_check,
1610         .protect_check = stm32x_protect_check,
1611         .info = get_stm32x_info,
1612 };