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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "imp.h"
  31 #include <helper/binarybuffer.h>
  32 #include <target/algorithm.h>
  33 #include <target/armv7m.h>
  34
  35 /* stm32x register locations */
  36
  37 #define FLASH_REG_BASE_B0 0x40022000
  38 #define FLASH_REG_BASE_B1 0x40022040
  39
  40 #define STM32_FLASH_ACR     0x00
  41 #define STM32_FLASH_KEYR    0x04
  42 #define STM32_FLASH_OPTKEYR 0x08
  43 #define STM32_FLASH_SR      0x0C
  44 #define STM32_FLASH_CR      0x10
  45 #define STM32_FLASH_AR      0x14
  46 #define STM32_FLASH_OBR     0x1C
  47 #define STM32_FLASH_WRPR    0x20
  48
  49 /* TODO: Check if code using these really should be hard coded to bank 0.
  50  * There are valid cases, on dual flash devices the protection of the
  51  * second bank is done on the bank0 reg's. */
  52 #define STM32_FLASH_ACR_B0     0x40022000
  53 #define STM32_FLASH_KEYR_B0    0x40022004
  54 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  55 #define STM32_FLASH_SR_B0      0x4002200C
  56 #define STM32_FLASH_CR_B0      0x40022010
  57 #define STM32_FLASH_AR_B0      0x40022014
  58 #define STM32_FLASH_OBR_B0     0x4002201C
  59 #define STM32_FLASH_WRPR_B0    0x40022020
  60
  61 /* option byte location */
  62
  63 #define STM32_OB_RDP            0x1FFFF800
  64 #define STM32_OB_USER           0x1FFFF802
  65 #define STM32_OB_DATA0          0x1FFFF804
  66 #define STM32_OB_DATA1          0x1FFFF806
  67 #define STM32_OB_WRP0           0x1FFFF808
  68 #define STM32_OB_WRP1           0x1FFFF80A
  69 #define STM32_OB_WRP2           0x1FFFF80C
  70 #define STM32_OB_WRP3           0x1FFFF80E
  71
  72 /* FLASH_CR register bits */
  73
  74 #define FLASH_PG                (1 << 0)
  75 #define FLASH_PER               (1 << 1)
  76 #define FLASH_MER               (1 << 2)
  77 #define FLASH_OPTPG             (1 << 4)
  78 #define FLASH_OPTER             (1 << 5)
  79 #define FLASH_STRT              (1 << 6)
  80 #define FLASH_LOCK              (1 << 7)
  81 #define FLASH_OPTWRE    (1 << 9)
  82
  83 /* FLASH_SR register bits */
  84
  85 #define FLASH_BSY               (1 << 0)
  86 #define FLASH_PGERR             (1 << 2)
  87 #define FLASH_WRPRTERR  (1 << 4)
  88 #define FLASH_EOP               (1 << 5)
  89
  90 /* STM32_FLASH_OBR bit definitions (reading) */
  91
  92 #define OPT_ERROR               0
  93 #define OPT_READOUT             1
  94 #define OPT_RDWDGSW             2
  95 #define OPT_RDRSTSTOP   3
  96 #define OPT_RDRSTSTDBY  4
  97 #define OPT_BFB2                5       /* dual flash bank only */
  98
  99 /* register unlock keys */
 100
 101 #define KEY1                    0x45670123
 102 #define KEY2                    0xCDEF89AB
 103
 104 struct stm32x_options
 105 {
 106         uint16_t RDP;
 107         uint16_t user_options;
 108         uint16_t protection[4];
 109 };
 110
 111 struct stm32x_flash_bank
 112 {
 113         struct stm32x_options option_bytes;
 114         struct working_area *write_algorithm;
 115         int ppage_size;
 116         int probed;
 117
 118         bool has_dual_banks;
 119         /* used to access dual flash bank stm32xl */
 120         uint32_t register_base;
 121 };
 122
 123 static int stm32x_mass_erase(struct flash_bank *bank);
 124
 125 /* flash bank stm32x <base> <size> 0 0 <target#>
 126  */
 127 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 128 {
 129         struct stm32x_flash_bank *stm32x_info;
 130
 131         if (CMD_ARGC < 6)
 132         {
 133                 return ERROR_COMMAND_SYNTAX_ERROR;
 134         }
 135
 136         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 137         bank->driver_priv = stm32x_info;
 138
 139         stm32x_info->write_algorithm = NULL;
 140         stm32x_info->probed = 0;
 141         stm32x_info->has_dual_banks = false;
 142         stm32x_info->register_base = FLASH_REG_BASE_B0;
 143
 144         return ERROR_OK;
 145 }
 146
 147 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 148 {
 149         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 150         return reg + stm32x_info->register_base;
 151 }
 152
 153 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 154 {
 155         struct target *target = bank->target;
 156         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 157 }
 158
 159 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 160 {
 161         struct target *target = bank->target;
 162         uint32_t status;
 163         int retval = ERROR_OK;
 164
 165         /* wait for busy to clear */
 166         for (;;)
 167         {
 168                 retval = stm32x_get_flash_status(bank, &status);
 169                 if (retval != ERROR_OK)
 170                         return retval;
 171                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 172                 if ((status & FLASH_BSY) == 0)
 173                         break;
 174                 if (timeout-- <= 0)
 175                 {
 176                         LOG_ERROR("timed out waiting for flash");
 177                         return ERROR_FAIL;
 178                 }
 179                 alive_sleep(1);
 180         }
 181
 182         if (status & FLASH_WRPRTERR)
 183         {
 184                 LOG_ERROR("stm32x device protected");
 185                 retval = ERROR_FAIL;
 186         }
 187
 188         if (status & FLASH_PGERR)
 189         {
 190                 LOG_ERROR("stm32x device programming failed");
 191                 retval = ERROR_FAIL;
 192         }
 193
 194         /* Clear but report errors */
 195         if (status & (FLASH_WRPRTERR | FLASH_PGERR))
 196         {
 197                 /* If this operation fails, we ignore it and report the original
 198                  * retval
 199                  */
 200                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 201                                 FLASH_WRPRTERR | FLASH_PGERR);
 202         }
 203         return retval;
 204 }
 205
 206 int stm32x_check_operation_supported(struct flash_bank *bank)
 207 {
 208         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 209
 210         /* if we have a dual flash bank device then
 211          * we need to perform option byte stuff on bank0 only */
 212         if (stm32x_info->register_base != FLASH_REG_BASE_B0)
 213         {
 214                 LOG_ERROR("Option Byte Operation's must use bank0");
 215                 return ERROR_FLASH_OPERATION_FAILED;
 216         }
 217
 218         return ERROR_OK;
 219 }
 220
 221 static int stm32x_read_options(struct flash_bank *bank)
 222 {
 223         uint32_t optiondata;
 224         struct stm32x_flash_bank *stm32x_info = NULL;
 225         struct target *target = bank->target;
 226
 227         stm32x_info = bank->driver_priv;
 228
 229         /* read current option bytes */
 230         int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
 231         if (retval != ERROR_OK)
 232                 return retval;
 233
 234         stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
 235         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 236
 237         if (optiondata & (1 << OPT_READOUT))
 238                 LOG_INFO("Device Security Bit Set");
 239
 240         /* each bit refers to a 4bank protection */
 241         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
 242         if (retval != ERROR_OK)
 243                 return retval;
 244
 245         stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
 246         stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
 247         stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
 248         stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
 249
 250         return ERROR_OK;
 251 }
 252
 253 static int stm32x_erase_options(struct flash_bank *bank)
 254 {
 255         struct stm32x_flash_bank *stm32x_info = NULL;
 256         struct target *target = bank->target;
 257
 258         stm32x_info = bank->driver_priv;
 259
 260         /* read current options */
 261         stm32x_read_options(bank);
 262
 263         /* unlock flash registers */
 264         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 265         if (retval != ERROR_OK)
 266                 return retval;
 267
 268         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 269         if (retval != ERROR_OK)
 270                 return retval;
 271
 272         /* unlock option flash registers */
 273         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 274         if (retval != ERROR_OK)
 275                 return retval;
 276         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 277         if (retval != ERROR_OK)
 278                 return retval;
 279
 280         /* erase option bytes */
 281         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 282         if (retval != ERROR_OK)
 283                 return retval;
 284         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 285         if (retval != ERROR_OK)
 286                 return retval;
 287
 288         retval = stm32x_wait_status_busy(bank, 10);
 289         if (retval != ERROR_OK)
 290                 return retval;
 291
 292         /* clear readout protection and complementary option bytes
 293          * this will also force a device unlock if set */
 294         stm32x_info->option_bytes.RDP = 0x5AA5;
 295
 296         return ERROR_OK;
 297 }
 298
 299 static int stm32x_write_options(struct flash_bank *bank)
 300 {
 301         struct stm32x_flash_bank *stm32x_info = NULL;
 302         struct target *target = bank->target;
 303
 304         stm32x_info = bank->driver_priv;
 305
 306         /* unlock flash registers */
 307         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 308         if (retval != ERROR_OK)
 309                 return retval;
 310         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 311         if (retval != ERROR_OK)
 312                 return retval;
 313
 314         /* unlock option flash registers */
 315         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 316         if (retval != ERROR_OK)
 317                 return retval;
 318         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 319         if (retval != ERROR_OK)
 320                 return retval;
 321
 322         /* program option bytes */
 323         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 324         if (retval != ERROR_OK)
 325                 return retval;
 326
 327         /* write user option byte */
 328         retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
 329         if (retval != ERROR_OK)
 330                 return retval;
 331
 332         retval = stm32x_wait_status_busy(bank, 10);
 333         if (retval != ERROR_OK)
 334                 return retval;
 335
 336         /* write protection byte 1 */
 337         retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
 338         if (retval != ERROR_OK)
 339                 return retval;
 340
 341         retval = stm32x_wait_status_busy(bank, 10);
 342         if (retval != ERROR_OK)
 343                 return retval;
 344
 345         /* write protection byte 2 */
 346         retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
 347         if (retval != ERROR_OK)
 348                 return retval;
 349
 350         retval = stm32x_wait_status_busy(bank, 10);
 351         if (retval != ERROR_OK)
 352                 return retval;
 353
 354         /* write protection byte 3 */
 355         retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
 356         if (retval != ERROR_OK)
 357                 return retval;
 358
 359         retval = stm32x_wait_status_busy(bank, 10);
 360         if (retval != ERROR_OK)
 361                 return retval;
 362
 363         /* write protection byte 4 */
 364         retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
 365         if (retval != ERROR_OK)
 366                 return retval;
 367
 368         retval = stm32x_wait_status_busy(bank, 10);
 369         if (retval != ERROR_OK)
 370                 return retval;
 371
 372         /* write readout protection bit */
 373         retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
 374         if (retval != ERROR_OK)
 375                 return retval;
 376
 377         retval = stm32x_wait_status_busy(bank, 10);
 378         if (retval != ERROR_OK)
 379                 return retval;
 380
 381         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 382         if (retval != ERROR_OK)
 383                 return retval;
 384
 385         return ERROR_OK;
 386 }
 387
 388 static int stm32x_protect_check(struct flash_bank *bank)
 389 {
 390         struct target *target = bank->target;
 391         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 392
 393         uint32_t protection;
 394         int i, s;
 395         int num_bits;
 396         int set;
 397
 398         if (target->state != TARGET_HALTED)
 399         {
 400                 LOG_ERROR("Target not halted");
 401                 return ERROR_TARGET_NOT_HALTED;
 402         }
 403
 404         int retval = stm32x_check_operation_supported(bank);
 405         if (ERROR_OK != retval)
 406                 return retval;
 407
 408         /* medium density - each bit refers to a 4bank protection
 409          * high density - each bit refers to a 2bank protection */
 410         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 411         if (retval != ERROR_OK)
 412                 return retval;
 413
 414         /* medium density - each protection bit is for 4 * 1K pages
 415          * high density - each protection bit is for 2 * 2K pages */
 416         num_bits = (bank->num_sectors / stm32x_info->ppage_size);
 417
 418         if (stm32x_info->ppage_size == 2)
 419         {
 420                 /* high density flash/connectivity line protection */
 421
 422                 set = 1;
 423
 424                 if (protection & (1 << 31))
 425                         set = 0;
 426
 427                 /* bit 31 controls sector 62 - 255 protection for high density
 428                  * bit 31 controls sector 62 - 127 protection for connectivity line */
 429                 for (s = 62; s < bank->num_sectors; s++)
 430                 {
 431                         bank->sectors[s].is_protected = set;
 432                 }
 433
 434                 if (bank->num_sectors > 61)
 435                         num_bits = 31;
 436
 437                 for (i = 0; i < num_bits; i++)
 438                 {
 439                         set = 1;
 440
 441                         if (protection & (1 << i))
 442                                 set = 0;
 443
 444                         for (s = 0; s < stm32x_info->ppage_size; s++)
 445                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 446                 }
 447         }
 448         else
 449         {
 450                 /* low/medium density flash protection */
 451                 for (i = 0; i < num_bits; i++)
 452                 {
 453                         set = 1;
 454
 455                         if (protection & (1 << i))
 456                                 set = 0;
 457
 458                         for (s = 0; s < stm32x_info->ppage_size; s++)
 459                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 460                 }
 461         }
 462
 463         return ERROR_OK;
 464 }
 465
 466 static int stm32x_erase(struct flash_bank *bank, int first, int last)
 467 {
 468         struct target *target = bank->target;
 469         int i;
 470
 471         if (bank->target->state != TARGET_HALTED)
 472         {
 473                 LOG_ERROR("Target not halted");
 474                 return ERROR_TARGET_NOT_HALTED;
 475         }
 476
 477         if ((first == 0) && (last == (bank->num_sectors - 1)))
 478         {
 479                 return stm32x_mass_erase(bank);
 480         }
 481
 482         /* unlock flash registers */
 483         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 484         if (retval != ERROR_OK)
 485                 return retval;
 486         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 487         if (retval != ERROR_OK)
 488                 return retval;
 489
 490         for (i = first; i <= last; i++)
 491         {
 492                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 493                 if (retval != ERROR_OK)
 494                         return retval;
 495                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 496                                 bank->base + bank->sectors[i].offset);
 497                 if (retval != ERROR_OK)
 498                         return retval;
 499                 retval = target_write_u32(target,
 500                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 501                 if (retval != ERROR_OK)
 502                         return retval;
 503
 504                 retval = stm32x_wait_status_busy(bank, 100);
 505                 if (retval != ERROR_OK)
 506                         return retval;
 507
 508                 bank->sectors[i].is_erased = 1;
 509         }
 510
 511         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 512         if (retval != ERROR_OK)
 513                 return retval;
 514
 515         return ERROR_OK;
 516 }
 517
 518 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
 519 {
 520         struct stm32x_flash_bank *stm32x_info = NULL;
 521         struct target *target = bank->target;
 522         uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 523         int i, reg, bit;
 524         int status;
 525         uint32_t protection;
 526
 527         stm32x_info = bank->driver_priv;
 528
 529         if (target->state != TARGET_HALTED)
 530         {
 531                 LOG_ERROR("Target not halted");
 532                 return ERROR_TARGET_NOT_HALTED;
 533         }
 534
 535         int retval = stm32x_check_operation_supported(bank);
 536         if (ERROR_OK != retval)
 537                 return retval;
 538
 539         if ((first % stm32x_info->ppage_size) != 0)
 540         {
 541                 LOG_WARNING("aligned start protect sector to a %d sector boundary",
 542                                 stm32x_info->ppage_size);
 543                 first = first - (first % stm32x_info->ppage_size);
 544         }
 545         if (((last + 1) % stm32x_info->ppage_size) != 0)
 546         {
 547                 LOG_WARNING("aligned end protect sector to a %d sector boundary",
 548                                 stm32x_info->ppage_size);
 549                 last++;
 550                 last = last - (last % stm32x_info->ppage_size);
 551                 last--;
 552         }
 553
 554         /* medium density - each bit refers to a 4bank protection
 555          * high density - each bit refers to a 2bank protection */
 556         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 557         if (retval != ERROR_OK)
 558                 return retval;
 559
 560         prot_reg[0] = (uint16_t)protection;
 561         prot_reg[1] = (uint16_t)(protection >> 8);
 562         prot_reg[2] = (uint16_t)(protection >> 16);
 563         prot_reg[3] = (uint16_t)(protection >> 24);
 564
 565         if (stm32x_info->ppage_size == 2)
 566         {
 567                 /* high density flash */
 568
 569                 /* bit 7 controls sector 62 - 255 protection */
 570                 if (last > 61)
 571                 {
 572                         if (set)
 573                                 prot_reg[3] &= ~(1 << 7);
 574                         else
 575                                 prot_reg[3] |= (1 << 7);
 576                 }
 577
 578                 if (first > 61)
 579                         first = 62;
 580                 if (last > 61)
 581                         last = 61;
 582
 583                 for (i = first; i <= last; i++)
 584                 {
 585                         reg = (i / stm32x_info->ppage_size) / 8;
 586                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 587
 588                         if (set)
 589                                 prot_reg[reg] &= ~(1 << bit);
 590                         else
 591                                 prot_reg[reg] |= (1 << bit);
 592                 }
 593         }
 594         else
 595         {
 596                 /* medium density flash */
 597                 for (i = first; i <= last; i++)
 598                 {
 599                         reg = (i / stm32x_info->ppage_size) / 8;
 600                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 601
 602                         if (set)
 603                                 prot_reg[reg] &= ~(1 << bit);
 604                         else
 605                                 prot_reg[reg] |= (1 << bit);
 606                 }
 607         }
 608
 609         if ((status = stm32x_erase_options(bank)) != ERROR_OK)
 610                 return status;
 611
 612         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 613         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 614         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 615         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 616
 617         return stm32x_write_options(bank);
 618 }
 619
 620 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 621                 uint32_t offset, uint32_t count)
 622 {
 623         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 624         struct target *target = bank->target;
 625         uint32_t buffer_size = 16384;
 626         struct working_area *source;
 627         uint32_t address = bank->base + offset;
 628         struct reg_param reg_params[5];
 629         struct armv7m_algorithm armv7m_info;
 630         int retval = ERROR_OK;
 631
 632         /* see contrib/loaders/flash/stm32f1x.S for src */
 633
 634         static const uint8_t stm32x_flash_write_code[] = {
 635                 /* #define STM32_FLASH_CR_OFFSET 0x10 */
 636                 /* #define STM32_FLASH_SR_OFFSET 0x0C */
 637                 /* wait_fifo: */
 638                         0x16, 0x68,             /* ldr          r6, [r2, #0] */
 639                         0x00, 0x2e,             /* cmp          r6, #0 */
 640                         0x1a, 0xd0,             /* beq          exit */
 641                         0x55, 0x68,             /* ldr          r5, [r2, #4] */
 642                         0xb5, 0x42,             /* cmp          r5, r6 */
 643                         0xf9, 0xd0,             /* beq          wait_fifo */
 644                         0x01, 0x26,             /* movs         r6, #1 */
 645                         0x06, 0x61,             /* str          r6, [r0, #STM32_FLASH_CR_OFFSET] */
 646                         0x35, 0xf8, 0x02, 0x6b, /* ldrh         r6, [r5], #2 */
 647                         0x24, 0xf8, 0x02, 0x6b, /* strh         r6, [r4], #2 */
 648                 /* busy: */
 649                         0xc6, 0x68,             /* ldr          r6, [r0, #STM32_FLASH_SR_OFFSET] */
 650                         0x16, 0xf0, 0x01, 0x0f, /* tst          r6, #1 */
 651                         0xfb, 0xd1,             /* bne          busy */
 652                         0x16, 0xf0, 0x14, 0x0f, /* tst          r6, #0x14 */
 653                         0x07, 0xd1,             /* bne          error */
 654                         0x9d, 0x42,             /* cmp          r5, r3 */
 655                         0x28, 0xbf,             /* it           cs */
 656                         0x02, 0xf1, 0x08, 0x05, /* addcs        r5, r2, #8 */
 657                         0x55, 0x60,             /* str          r5, [r2, #4] */
 658                         0x01, 0x39,             /* subs         r1, r1, #1 */
 659                         0x19, 0xb1,             /* cbz          r1, exit */
 660                         0xe4, 0xe7,             /* b            wait_fifo */
 661                 /* error: */
 662                         0x00, 0x20,             /* movs         r0, #0 */
 663                         0xc2, 0xf8,     0x02, 0x00, /* str      r0, [r2, #2] */
 664                 /* exit: */
 665                         0x30, 0x46,             /* mov          r0, r6 */
 666                         0x00, 0xbe,             /* bkpt         #0 */
 667         };
 668
 669         /* flash write code */
 670         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 671                         &stm32x_info->write_algorithm) != ERROR_OK)
 672         {
 673                 LOG_WARNING("no working area available, can't do block memory writes");
 674                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 675         };
 676
 677         if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
 678                         sizeof(stm32x_flash_write_code),
 679                         (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
 680                 return retval;
 681
 682         /* memory buffer */
 683         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
 684         {
 685                 buffer_size /= 2;
 686                 buffer_size &= ~3UL; // Make sure it's 4 byte aligned
 687                 if (buffer_size <= 256)
 688                 {
 689                         /* if we already allocated the writing code, but failed to get a
 690                          * buffer, free the algorithm */
 691                         if (stm32x_info->write_algorithm)
 692                                 target_free_working_area(target, stm32x_info->write_algorithm);
 693
 694                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 695                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 696                 }
 697         };
 698
 699         /* Set up working area. First word is write pointer, second word is read pointer,
 700          * rest is fifo data area. */
 701         uint32_t wp_addr = source->address;
 702         uint32_t rp_addr = source->address + 4;
 703         uint32_t fifo_start_addr = source->address + 8;
 704         uint32_t fifo_end_addr = source->address + source->size;
 705
 706         uint32_t wp = fifo_start_addr;
 707         uint32_t rp = fifo_start_addr;
 708
 709         retval = target_write_u32(target, wp_addr, wp);
 710         if (retval != ERROR_OK)
 711                 return retval;
 712         retval = target_write_u32(target, rp_addr, rp);
 713         if (retval != ERROR_OK)
 714                 return retval;
 715
 716         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 717         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 718         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 719         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 720         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 721
 722         buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
 723         buf_set_u32(reg_params[1].value, 0, 32, count);
 724         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 725         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 726         buf_set_u32(reg_params[4].value, 0, 32, address);
 727
 728         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 729         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 730
 731         /* Start up algorithm on target and let it idle while writing the first chunk */
 732         if ((retval = target_start_algorithm(target, 0, NULL, 5, reg_params,
 733                         stm32x_info->write_algorithm->address,
 734                         0,
 735                         &armv7m_info)) != ERROR_OK)
 736         {
 737                 LOG_ERROR("error starting stm32x flash write algorithm");
 738                 goto cleanup;
 739         }
 740
 741         while (count > 0)
 742         {
 743                 retval = target_read_u32(target, rp_addr, &rp);
 744                 if (retval != ERROR_OK)
 745                 {
 746                         LOG_ERROR("failed to get read pointer");
 747                         break;
 748                 }
 749
 750                 LOG_DEBUG("count 0x%"PRIx32" wp 0x%"PRIx32" rp 0x%"PRIx32, count, wp, rp);
 751
 752                 if (rp == 0)
 753                 {
 754                         LOG_ERROR("flash write algorithm aborted by target");
 755                         retval = ERROR_FLASH_OPERATION_FAILED;
 756                         break;
 757                 }
 758
 759                 if ((rp & 1) || rp < fifo_start_addr || rp >= fifo_end_addr)
 760                 {
 761                         LOG_ERROR("corrupted fifo read pointer 0x%"PRIx32, rp);
 762                         break;
 763                 }
 764
 765                 /* Count the number of bytes available in the fifo without
 766                  * crossing the wrap around. Make sure to not fill it completely,
 767                  * because that would make wp == rp and that's the empty condition. */
 768                 uint32_t thisrun_bytes;
 769                 if (rp > wp)
 770                         thisrun_bytes = rp - wp - 2;
 771                 else if (rp > fifo_start_addr)
 772                         thisrun_bytes = fifo_end_addr - wp;
 773                 else
 774                         thisrun_bytes = fifo_end_addr - wp - 2;
 775
 776                 if (thisrun_bytes == 0)
 777                 {
 778                         /* Throttle polling a bit if transfer is (much) faster than flash
 779                          * programming. The exact delay shouldn't matter as long as it's
 780                          * less than buffer size / flash speed. This is very unlikely to
 781                          * run when using high latency connections such as USB. */
 782                         alive_sleep(10);
 783                         continue;
 784                 }
 785
 786                 /* Limit to the amount of data we actually want to write */
 787                 if (thisrun_bytes > count * 2)
 788                         thisrun_bytes = count * 2;
 789
 790                 /* Write data to fifo */
 791                 retval = target_write_buffer(target, wp, thisrun_bytes, buffer);
 792                 if (retval != ERROR_OK)
 793                         break;
 794
 795                 /* Update counters and wrap write pointer */
 796                 buffer += thisrun_bytes;
 797                 count -= thisrun_bytes / 2;
 798                 wp += thisrun_bytes;
 799                 if (wp >= fifo_end_addr)
 800                         wp = fifo_start_addr;
 801
 802                 /* Store updated write pointer to target */
 803                 retval = target_write_u32(target, wp_addr, wp);
 804                 if (retval != ERROR_OK)
 805                         break;
 806         }
 807
 808         if (retval != ERROR_OK)
 809         {
 810                 /* abort flash write algorithm on target */
 811                 target_write_u32(target, wp_addr, 0);
 812         }
 813
 814         int retval2;
 815         if ((retval2 = target_wait_algorithm(target, 0, NULL, 5, reg_params,
 816                         0,
 817                         10000,
 818                         &armv7m_info)) != ERROR_OK)
 819         {
 820                 LOG_ERROR("error waiting for stm32x flash write algorithm");
 821                 retval = retval2;
 822         }
 823
 824         if (retval == ERROR_FLASH_OPERATION_FAILED)
 825         {
 826                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 827                                 buf_get_u32(reg_params[4].value, 0, 32));
 828
 829                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR)
 830                 {
 831                         LOG_ERROR("flash memory not erased before writing");
 832                         /* Clear but report errors */
 833                         target_write_u32(target, STM32_FLASH_SR_B0, FLASH_PGERR);
 834                 }
 835
 836                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR)
 837                 {
 838                         LOG_ERROR("flash memory write protected");
 839                         /* Clear but report errors */
 840                         target_write_u32(target, STM32_FLASH_SR_B0, FLASH_WRPRTERR);
 841                 }
 842         }
 843
 844 cleanup:
 845         target_free_working_area(target, source);
 846         target_free_working_area(target, stm32x_info->write_algorithm);
 847
 848         destroy_reg_param(&reg_params[0]);
 849         destroy_reg_param(&reg_params[1]);
 850         destroy_reg_param(&reg_params[2]);
 851         destroy_reg_param(&reg_params[3]);
 852         destroy_reg_param(&reg_params[4]);
 853
 854         return retval;
 855 }
 856
 857 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
 858                 uint32_t offset, uint32_t count)
 859 {
 860         struct target *target = bank->target;
 861         uint32_t words_remaining = (count / 2);
 862         uint32_t bytes_remaining = (count & 0x00000001);
 863         uint32_t address = bank->base + offset;
 864         uint32_t bytes_written = 0;
 865         int retval;
 866
 867         if (bank->target->state != TARGET_HALTED)
 868         {
 869                 LOG_ERROR("Target not halted");
 870                 return ERROR_TARGET_NOT_HALTED;
 871         }
 872
 873         if (offset & 0x1)
 874         {
 875                 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 876                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 877         }
 878
 879         /* unlock flash registers */
 880         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 881         if (retval != ERROR_OK)
 882                 return retval;
 883         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 884         if (retval != ERROR_OK)
 885                 return retval;
 886
 887         /* multiple half words (2-byte) to be programmed? */
 888         if (words_remaining > 0)
 889         {
 890                 /* try using a block write */
 891                 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
 892                 {
 893                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 894                         {
 895                                 /* if block write failed (no sufficient working area),
 896                                  * we use normal (slow) single dword accesses */
 897                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 898                         }
 899                 }
 900                 else
 901                 {
 902                         buffer += words_remaining * 2;
 903                         address += words_remaining * 2;
 904                         words_remaining = 0;
 905                 }
 906         }
 907
 908         if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
 909                 return retval;
 910
 911         while (words_remaining > 0)
 912         {
 913                 uint16_t value;
 914                 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
 915
 916                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 917                 if (retval != ERROR_OK)
 918                         return retval;
 919                 retval = target_write_u16(target, address, value);
 920                 if (retval != ERROR_OK)
 921                         return retval;
 922
 923                 retval = stm32x_wait_status_busy(bank, 5);
 924                 if (retval != ERROR_OK)
 925                         return retval;
 926
 927                 bytes_written += 2;
 928                 words_remaining--;
 929                 address += 2;
 930         }
 931
 932         if (bytes_remaining)
 933         {
 934                 uint16_t value = 0xffff;
 935                 memcpy(&value, buffer + bytes_written, bytes_remaining);
 936
 937                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 938                 if (retval != ERROR_OK)
 939                         return retval;
 940                 retval = target_write_u16(target, address, value);
 941                 if (retval != ERROR_OK)
 942                         return retval;
 943
 944                 retval = stm32x_wait_status_busy(bank, 5);
 945                 if (retval != ERROR_OK)
 946                         return retval;
 947         }
 948
 949         return target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 950 }
 951
 952 static int stm32x_probe(struct flash_bank *bank)
 953 {
 954         struct target *target = bank->target;
 955         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 956         int i;
 957         uint16_t flash_size_in_kb;
 958         uint32_t device_id;
 959         int page_size;
 960         uint32_t base_address = 0x08000000;
 961
 962         stm32x_info->probed = 0;
 963         stm32x_info->register_base = FLASH_REG_BASE_B0;
 964
 965         /* read stm32 device id register */
 966         int retval = target_read_u32(target, 0xE0042000, &device_id);
 967         if (retval != ERROR_OK)
 968                 return retval;
 969         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 970
 971         /* get flash size from target. */
 972         retval = target_read_u16(target, 0x1FFFF7E0, &flash_size_in_kb);
 973         if (retval != ERROR_OK)
 974         {
 975                 LOG_WARNING("failed reading flash size, default to max target family");
 976                 /* failed reading flash size, default to max target family */
 977                 flash_size_in_kb = 0xffff;
 978         }
 979
 980         if ((device_id & 0x7ff) == 0x410)
 981         {
 982                 /* medium density - we have 1k pages
 983                  * 4 pages for a protection area */
 984                 page_size = 1024;
 985                 stm32x_info->ppage_size = 4;
 986
 987                 /* check for early silicon */
 988                 if (flash_size_in_kb == 0xffff)
 989                 {
 990                         /* number of sectors incorrect on revA */
 991                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
 992                         flash_size_in_kb = 128;
 993                 }
 994         }
 995         else if ((device_id & 0x7ff) == 0x412)
 996         {
 997                 /* low density - we have 1k pages
 998                  * 4 pages for a protection area */
 999                 page_size = 1024;
1000                 stm32x_info->ppage_size = 4;
1001
1002                 /* check for early silicon */
1003                 if (flash_size_in_kb == 0xffff)
1004                 {
1005                         /* number of sectors incorrect on revA */
1006                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
1007                         flash_size_in_kb = 32;
1008                 }
1009         }
1010         else if ((device_id & 0x7ff) == 0x414)
1011         {
1012                 /* high density - we have 2k pages
1013                  * 2 pages for a protection area */
1014                 page_size = 2048;
1015                 stm32x_info->ppage_size = 2;
1016
1017                 /* check for early silicon */
1018                 if (flash_size_in_kb == 0xffff)
1019                 {
1020                         /* number of sectors incorrect on revZ */
1021                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
1022                         flash_size_in_kb = 512;
1023                 }
1024         }
1025         else if ((device_id & 0x7ff) == 0x418)
1026         {
1027                 /* connectivity line density - we have 2k pages
1028                  * 2 pages for a protection area */
1029                 page_size = 2048;
1030                 stm32x_info->ppage_size = 2;
1031
1032                 /* check for early silicon */
1033                 if (flash_size_in_kb == 0xffff)
1034                 {
1035                         /* number of sectors incorrect on revZ */
1036                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
1037                         flash_size_in_kb = 256;
1038                 }
1039         }
1040         else if ((device_id & 0x7ff) == 0x420)
1041         {
1042                 /* value line density - we have 1k pages
1043                  * 4 pages for a protection area */
1044                 page_size = 1024;
1045                 stm32x_info->ppage_size = 4;
1046
1047                 /* check for early silicon */
1048                 if (flash_size_in_kb == 0xffff)
1049                 {
1050                         /* number of sectors may be incorrrect on early silicon */
1051                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
1052                         flash_size_in_kb = 128;
1053                 }
1054         }
1055         else if ((device_id & 0x7ff) == 0x428)
1056         {
1057                 /* value line High density - we have 2k pages
1058                  * 4 pages for a protection area */
1059                 page_size = 2048;
1060                 stm32x_info->ppage_size = 4;
1061
1062                 /* check for early silicon */
1063                 if (flash_size_in_kb == 0xffff)
1064                 {
1065                         /* number of sectors may be incorrrect on early silicon */
1066                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
1067                         flash_size_in_kb = 128;
1068                 }
1069         }
1070
1071         else if ((device_id & 0x7ff) == 0x430)
1072         {
1073                 /* xl line density - we have 2k pages
1074                  * 2 pages for a protection area */
1075                 page_size = 2048;
1076                 stm32x_info->ppage_size = 2;
1077                 stm32x_info->has_dual_banks = true;
1078
1079                 /* check for early silicon */
1080                 if (flash_size_in_kb == 0xffff)
1081                 {
1082                         /* number of sectors may be incorrrect on early silicon */
1083                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
1084                         flash_size_in_kb = 1024;
1085                 }
1086
1087                 /* split reported size into matching bank */
1088                 if (bank->base != 0x08080000)
1089                 {
1090                         /* bank 0 will be fixed 512k */
1091                         flash_size_in_kb = 512;
1092                 }
1093                 else
1094                 {
1095                         flash_size_in_kb -= 512;
1096                         /* bank1 also uses a register offset */
1097                         stm32x_info->register_base = FLASH_REG_BASE_B1;
1098                         base_address = 0x08080000;
1099                 }
1100         }
1101         else
1102         {
1103                 LOG_WARNING("Cannot identify target as a STM32 family.");
1104                 return ERROR_FAIL;
1105         }
1106
1107         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
1108
1109         /* did we assign flash size? */
1110         assert(flash_size_in_kb != 0xffff);
1111
1112         /* calculate numbers of pages */
1113         int num_pages = flash_size_in_kb * 1024 / page_size;
1114
1115         /* check that calculation result makes sense */
1116         assert(num_pages > 0);
1117
1118         if (bank->sectors)
1119         {
1120                 free(bank->sectors);
1121                 bank->sectors = NULL;
1122         }
1123
1124         bank->base = base_address;
1125         bank->size = (num_pages * page_size);
1126         bank->num_sectors = num_pages;
1127         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1128
1129         for (i = 0; i < num_pages; i++)
1130         {
1131                 bank->sectors[i].offset = i * page_size;
1132                 bank->sectors[i].size = page_size;
1133                 bank->sectors[i].is_erased = -1;
1134                 bank->sectors[i].is_protected = 1;
1135         }
1136
1137         stm32x_info->probed = 1;
1138
1139         return ERROR_OK;
1140 }
1141
1142 static int stm32x_auto_probe(struct flash_bank *bank)
1143 {
1144         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1145         if (stm32x_info->probed)
1146                 return ERROR_OK;
1147         return stm32x_probe(bank);
1148 }
1149
1150 #if 0
1151 COMMAND_HANDLER(stm32x_handle_part_id_command)
1152 {
1153         return ERROR_OK;
1154 }
1155 #endif
1156
1157 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1158 {
1159         struct target *target = bank->target;
1160         uint32_t device_id;
1161         int printed;
1162
1163         /* read stm32 device id register */
1164         int retval = target_read_u32(target, 0xE0042000, &device_id);
1165         if (retval != ERROR_OK)
1166                 return retval;
1167
1168         if ((device_id & 0x7ff) == 0x410)
1169         {
1170                 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1171                 buf += printed;
1172                 buf_size -= printed;
1173
1174                 switch (device_id >> 16)
1175                 {
1176                         case 0x0000:
1177                                 snprintf(buf, buf_size, "A");
1178                                 break;
1179
1180                         case 0x2000:
1181                                 snprintf(buf, buf_size, "B");
1182                                 break;
1183
1184                         case 0x2001:
1185                                 snprintf(buf, buf_size, "Z");
1186                                 break;
1187
1188                         case 0x2003:
1189                                 snprintf(buf, buf_size, "Y");
1190                                 break;
1191
1192                         default:
1193                                 snprintf(buf, buf_size, "unknown");
1194                                 break;
1195                 }
1196         }
1197         else if ((device_id & 0x7ff) == 0x412)
1198         {
1199                 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1200                 buf += printed;
1201                 buf_size -= printed;
1202
1203                 switch (device_id >> 16)
1204                 {
1205                         case 0x1000:
1206                                 snprintf(buf, buf_size, "A");
1207                                 break;
1208
1209                         default:
1210                                 snprintf(buf, buf_size, "unknown");
1211                                 break;
1212                 }
1213         }
1214         else if ((device_id & 0x7ff) == 0x414)
1215         {
1216                 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1217                 buf += printed;
1218                 buf_size -= printed;
1219
1220                 switch (device_id >> 16)
1221                 {
1222                         case 0x1000:
1223                                 snprintf(buf, buf_size, "A");
1224                                 break;
1225
1226                         case 0x1001:
1227                                 snprintf(buf, buf_size, "Z");
1228                                 break;
1229
1230                         default:
1231                                 snprintf(buf, buf_size, "unknown");
1232                                 break;
1233                 }
1234         }
1235         else if ((device_id & 0x7ff) == 0x418)
1236         {
1237                 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1238                 buf += printed;
1239                 buf_size -= printed;
1240
1241                 switch (device_id >> 16)
1242                 {
1243                         case 0x1000:
1244                                 snprintf(buf, buf_size, "A");
1245                                 break;
1246
1247                         case 0x1001:
1248                                 snprintf(buf, buf_size, "Z");
1249                                 break;
1250
1251                         default:
1252                                 snprintf(buf, buf_size, "unknown");
1253                                 break;
1254                 }
1255         }
1256         else if ((device_id & 0x7ff) == 0x420)
1257         {
1258                 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1259                 buf += printed;
1260                 buf_size -= printed;
1261
1262                 switch (device_id >> 16)
1263                 {
1264                         case 0x1000:
1265                                 snprintf(buf, buf_size, "A");
1266                                 break;
1267
1268                         case 0x1001:
1269                                 snprintf(buf, buf_size, "Z");
1270                                 break;
1271
1272                         default:
1273                                 snprintf(buf, buf_size, "unknown");
1274                                 break;
1275                 }
1276         }
1277         else if ((device_id & 0x7ff) == 0x428)
1278         {
1279                 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1280                 buf += printed;
1281                 buf_size -= printed;
1282
1283                 switch (device_id >> 16)
1284                 {
1285                         case 0x1000:
1286                                 snprintf(buf, buf_size, "A");
1287                                 break;
1288
1289                         case 0x1001:
1290                                 snprintf(buf, buf_size, "Z");
1291                                 break;
1292
1293                         default:
1294                                 snprintf(buf, buf_size, "unknown");
1295                                 break;
1296                 }
1297         }
1298         else if ((device_id & 0x7ff) == 0x430)
1299         {
1300                 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1301                 buf += printed;
1302                 buf_size -= printed;
1303
1304                 switch (device_id >> 16)
1305                 {
1306                         case 0x1000:
1307                                 snprintf(buf, buf_size, "A");
1308                                 break;
1309
1310                         default:
1311                                 snprintf(buf, buf_size, "unknown");
1312                                 break;
1313                 }
1314         }
1315         else
1316         {
1317                 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1318                 return ERROR_FAIL;
1319         }
1320
1321         return ERROR_OK;
1322 }
1323
1324 COMMAND_HANDLER(stm32x_handle_lock_command)
1325 {
1326         struct target *target = NULL;
1327         struct stm32x_flash_bank *stm32x_info = NULL;
1328
1329         if (CMD_ARGC < 1)
1330         {
1331                 return ERROR_COMMAND_SYNTAX_ERROR;
1332         }
1333
1334         struct flash_bank *bank;
1335         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1336         if (ERROR_OK != retval)
1337                 return retval;
1338
1339         stm32x_info = bank->driver_priv;
1340
1341         target = bank->target;
1342
1343         if (target->state != TARGET_HALTED)
1344         {
1345                 LOG_ERROR("Target not halted");
1346                 return ERROR_TARGET_NOT_HALTED;
1347         }
1348
1349         retval = stm32x_check_operation_supported(bank);
1350         if (ERROR_OK != retval)
1351                 return retval;
1352
1353         if (stm32x_erase_options(bank) != ERROR_OK)
1354         {
1355                 command_print(CMD_CTX, "stm32x failed to erase options");
1356                 return ERROR_OK;
1357         }
1358
1359         /* set readout protection */
1360         stm32x_info->option_bytes.RDP = 0;
1361
1362         if (stm32x_write_options(bank) != ERROR_OK)
1363         {
1364                 command_print(CMD_CTX, "stm32x failed to lock device");
1365                 return ERROR_OK;
1366         }
1367
1368         command_print(CMD_CTX, "stm32x locked");
1369
1370         return ERROR_OK;
1371 }
1372
1373 COMMAND_HANDLER(stm32x_handle_unlock_command)
1374 {
1375         struct target *target = NULL;
1376
1377         if (CMD_ARGC < 1)
1378         {
1379                 return ERROR_COMMAND_SYNTAX_ERROR;
1380         }
1381
1382         struct flash_bank *bank;
1383         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1384         if (ERROR_OK != retval)
1385                 return retval;
1386
1387         target = bank->target;
1388
1389         if (target->state != TARGET_HALTED)
1390         {
1391                 LOG_ERROR("Target not halted");
1392                 return ERROR_TARGET_NOT_HALTED;
1393         }
1394
1395         retval = stm32x_check_operation_supported(bank);
1396         if (ERROR_OK != retval)
1397                 return retval;
1398
1399         if (stm32x_erase_options(bank) != ERROR_OK)
1400         {
1401                 command_print(CMD_CTX, "stm32x failed to unlock device");
1402                 return ERROR_OK;
1403         }
1404
1405         if (stm32x_write_options(bank) != ERROR_OK)
1406         {
1407                 command_print(CMD_CTX, "stm32x failed to lock device");
1408                 return ERROR_OK;
1409         }
1410
1411         command_print(CMD_CTX, "stm32x unlocked.\n"
1412                         "INFO: a reset or power cycle is required "
1413                         "for the new settings to take effect.");
1414
1415         return ERROR_OK;
1416 }
1417
1418 COMMAND_HANDLER(stm32x_handle_options_read_command)
1419 {
1420         uint32_t optionbyte;
1421         struct target *target = NULL;
1422         struct stm32x_flash_bank *stm32x_info = NULL;
1423
1424         if (CMD_ARGC < 1)
1425         {
1426                 return ERROR_COMMAND_SYNTAX_ERROR;
1427         }
1428
1429         struct flash_bank *bank;
1430         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1431         if (ERROR_OK != retval)
1432                 return retval;
1433
1434         stm32x_info = bank->driver_priv;
1435
1436         target = bank->target;
1437
1438         if (target->state != TARGET_HALTED)
1439         {
1440                 LOG_ERROR("Target not halted");
1441                 return ERROR_TARGET_NOT_HALTED;
1442         }
1443
1444         retval = stm32x_check_operation_supported(bank);
1445         if (ERROR_OK != retval)
1446                 return retval;
1447
1448         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1449         if (retval != ERROR_OK)
1450                 return retval;
1451         command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1452
1453         if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1454                 command_print(CMD_CTX, "Option Byte Complement Error");
1455
1456         if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1457                 command_print(CMD_CTX, "Readout Protection On");
1458         else
1459                 command_print(CMD_CTX, "Readout Protection Off");
1460
1461         if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1462                 command_print(CMD_CTX, "Software Watchdog");
1463         else
1464                 command_print(CMD_CTX, "Hardware Watchdog");
1465
1466         if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1467                 command_print(CMD_CTX, "Stop: No reset generated");
1468         else
1469                 command_print(CMD_CTX, "Stop: Reset generated");
1470
1471         if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1472                 command_print(CMD_CTX, "Standby: No reset generated");
1473         else
1474                 command_print(CMD_CTX, "Standby: Reset generated");
1475
1476         if (stm32x_info->has_dual_banks)
1477         {
1478                 if (buf_get_u32((uint8_t*)&optionbyte, OPT_BFB2, 1))
1479                         command_print(CMD_CTX, "Boot: Bank 0");
1480                 else
1481                         command_print(CMD_CTX, "Boot: Bank 1");
1482         }
1483
1484         return ERROR_OK;
1485 }
1486
1487 COMMAND_HANDLER(stm32x_handle_options_write_command)
1488 {
1489         struct target *target = NULL;
1490         struct stm32x_flash_bank *stm32x_info = NULL;
1491         uint16_t optionbyte = 0xF8;
1492
1493         if (CMD_ARGC < 4)
1494         {
1495                 return ERROR_COMMAND_SYNTAX_ERROR;
1496         }
1497
1498         struct flash_bank *bank;
1499         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1500         if (ERROR_OK != retval)
1501                 return retval;
1502
1503         stm32x_info = bank->driver_priv;
1504
1505         target = bank->target;
1506
1507         if (target->state != TARGET_HALTED)
1508         {
1509                 LOG_ERROR("Target not halted");
1510                 return ERROR_TARGET_NOT_HALTED;
1511         }
1512
1513         retval = stm32x_check_operation_supported(bank);
1514         if (ERROR_OK != retval)
1515                 return retval;
1516
1517         /* REVISIT: ignores some options which we will display...
1518          * and doesn't insist on the specified syntax.
1519          */
1520
1521         /* OPT_RDWDGSW */
1522         if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1523         {
1524                 optionbyte |= (1 << 0);
1525         }
1526         else    /* REVISIT must be "HWWDG" then ... */
1527         {
1528                 optionbyte &= ~(1 << 0);
1529         }
1530
1531         /* OPT_RDRSTSTOP */
1532         if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
1533         {
1534                 optionbyte |= (1 << 1);
1535         }
1536         else    /* REVISIT must be "RSTSTNDBY" then ... */
1537         {
1538                 optionbyte &= ~(1 << 1);
1539         }
1540
1541         /* OPT_RDRSTSTDBY */
1542         if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
1543         {
1544                 optionbyte |= (1 << 2);
1545         }
1546         else    /* REVISIT must be "RSTSTOP" then ... */
1547         {
1548                 optionbyte &= ~(1 << 2);
1549         }
1550
1551         if (CMD_ARGC > 4 && stm32x_info->has_dual_banks)
1552         {
1553                 /* OPT_BFB2 */
1554                 if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
1555                 {
1556                         optionbyte |= (1 << 3);
1557                 }
1558                 else
1559                 {
1560                         optionbyte &= ~(1 << 3);
1561                 }
1562         }
1563
1564         if (stm32x_erase_options(bank) != ERROR_OK)
1565         {
1566                 command_print(CMD_CTX, "stm32x failed to erase options");
1567                 return ERROR_OK;
1568         }
1569
1570         stm32x_info->option_bytes.user_options = optionbyte;
1571
1572         if (stm32x_write_options(bank) != ERROR_OK)
1573         {
1574                 command_print(CMD_CTX, "stm32x failed to write options");
1575                 return ERROR_OK;
1576         }
1577
1578         command_print(CMD_CTX, "stm32x write options complete.\n"
1579                                 "INFO: a reset or power cycle is required "
1580                                 "for the new settings to take effect.");
1581
1582         return ERROR_OK;
1583 }
1584
1585 static int stm32x_mass_erase(struct flash_bank *bank)
1586 {
1587         struct target *target = bank->target;
1588
1589         if (target->state != TARGET_HALTED)
1590         {
1591                 LOG_ERROR("Target not halted");
1592                 return ERROR_TARGET_NOT_HALTED;
1593         }
1594
1595         /* unlock option flash registers */
1596         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1597         if (retval != ERROR_OK)
1598                 return retval;
1599         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1600         if (retval != ERROR_OK)
1601                 return retval;
1602
1603         /* mass erase flash memory */
1604         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1605         if (retval != ERROR_OK)
1606                 return retval;
1607         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER | FLASH_STRT);
1608         if (retval != ERROR_OK)
1609                 return retval;
1610
1611         retval = stm32x_wait_status_busy(bank, 100);
1612         if (retval != ERROR_OK)
1613                 return retval;
1614
1615         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1616         if (retval != ERROR_OK)
1617                 return retval;
1618
1619         return ERROR_OK;
1620 }
1621
1622 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1623 {
1624         int i;
1625
1626         if (CMD_ARGC < 1)
1627         {
1628                 return ERROR_COMMAND_SYNTAX_ERROR;
1629         }
1630
1631         struct flash_bank *bank;
1632         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1633         if (ERROR_OK != retval)
1634                 return retval;
1635
1636         retval = stm32x_mass_erase(bank);
1637         if (retval == ERROR_OK)
1638         {
1639                 /* set all sectors as erased */
1640                 for (i = 0; i < bank->num_sectors; i++)
1641                 {
1642                         bank->sectors[i].is_erased = 1;
1643                 }
1644
1645                 command_print(CMD_CTX, "stm32x mass erase complete");
1646         }
1647         else
1648         {
1649                 command_print(CMD_CTX, "stm32x mass erase failed");
1650         }
1651
1652         return retval;
1653 }
1654
1655 static const struct command_registration stm32x_exec_command_handlers[] = {
1656         {
1657                 .name = "lock",
1658                 .handler = stm32x_handle_lock_command,
1659                 .mode = COMMAND_EXEC,
1660                 .usage = "bank_id",
1661                 .help = "Lock entire flash device.",
1662         },
1663         {
1664                 .name = "unlock",
1665                 .handler = stm32x_handle_unlock_command,
1666                 .mode = COMMAND_EXEC,
1667                 .usage = "bank_id",
1668                 .help = "Unlock entire protected flash device.",
1669         },
1670         {
1671                 .name = "mass_erase",
1672                 .handler = stm32x_handle_mass_erase_command,
1673                 .mode = COMMAND_EXEC,
1674                 .usage = "bank_id",
1675                 .help = "Erase entire flash device.",
1676         },
1677         {
1678                 .name = "options_read",
1679                 .handler = stm32x_handle_options_read_command,
1680                 .mode = COMMAND_EXEC,
1681                 .usage = "bank_id",
1682                 .help = "Read and display device option byte.",
1683         },
1684         {
1685                 .name = "options_write",
1686                 .handler = stm32x_handle_options_write_command,
1687                 .mode = COMMAND_EXEC,
1688                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1689                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1690                         "('RSTSTOP'|'NORSTSTOP')",
1691                 .help = "Replace bits in device option byte.",
1692         },
1693         COMMAND_REGISTRATION_DONE
1694 };
1695
1696 static const struct command_registration stm32x_command_handlers[] = {
1697         {
1698                 .name = "stm32f1x",
1699                 .mode = COMMAND_ANY,
1700                 .help = "stm32f1x flash command group",
1701                 .chain = stm32x_exec_command_handlers,
1702         },
1703         COMMAND_REGISTRATION_DONE
1704 };
1705
1706 struct flash_driver stm32f1x_flash = {
1707         .name = "stm32f1x",
1708         .commands = stm32x_command_handlers,
1709         .flash_bank_command = stm32x_flash_bank_command,
1710         .erase = stm32x_erase,
1711         .protect = stm32x_protect,
1712         .write = stm32x_write,
1713         .read = default_flash_read,
1714         .probe = stm32x_probe,
1715         .auto_probe = stm32x_auto_probe,
1716         .erase_check = default_flash_mem_blank_check,
1717         .protect_check = stm32x_protect_check,
1718         .info = get_stm32x_info,
1719 };