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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "imp.h"
  30 #include <helper/binarybuffer.h>
  31 #include <target/algorithm.h>
  32 #include <target/cortex_m.h>
  33
  34 /* stm32x register locations */
  35
  36 #define FLASH_REG_BASE_B0 0x40022000
  37 #define FLASH_REG_BASE_B1 0x40022040
  38
  39 #define STM32_FLASH_ACR     0x00
  40 #define STM32_FLASH_KEYR    0x04
  41 #define STM32_FLASH_OPTKEYR 0x08
  42 #define STM32_FLASH_SR      0x0C
  43 #define STM32_FLASH_CR      0x10
  44 #define STM32_FLASH_AR      0x14
  45 #define STM32_FLASH_OBR     0x1C
  46 #define STM32_FLASH_WRPR    0x20
  47
  48 /* TODO: Check if code using these really should be hard coded to bank 0.
  49  * There are valid cases, on dual flash devices the protection of the
  50  * second bank is done on the bank0 reg's. */
  51 #define STM32_FLASH_ACR_B0     0x40022000
  52 #define STM32_FLASH_KEYR_B0    0x40022004
  53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  54 #define STM32_FLASH_SR_B0      0x4002200C
  55 #define STM32_FLASH_CR_B0      0x40022010
  56 #define STM32_FLASH_AR_B0      0x40022014
  57 #define STM32_FLASH_OBR_B0     0x4002201C
  58 #define STM32_FLASH_WRPR_B0    0x40022020
  59
  60 /* option byte location */
  61
  62 #define STM32_OB_RDP            0x1FFFF800
  63 #define STM32_OB_USER           0x1FFFF802
  64 #define STM32_OB_DATA0          0x1FFFF804
  65 #define STM32_OB_DATA1          0x1FFFF806
  66 #define STM32_OB_WRP0           0x1FFFF808
  67 #define STM32_OB_WRP1           0x1FFFF80A
  68 #define STM32_OB_WRP2           0x1FFFF80C
  69 #define STM32_OB_WRP3           0x1FFFF80E
  70
  71 /* FLASH_CR register bits */
  72
  73 #define FLASH_PG                        (1 << 0)
  74 #define FLASH_PER                       (1 << 1)
  75 #define FLASH_MER                       (1 << 2)
  76 #define FLASH_OPTPG                     (1 << 4)
  77 #define FLASH_OPTER                     (1 << 5)
  78 #define FLASH_STRT                      (1 << 6)
  79 #define FLASH_LOCK                      (1 << 7)
  80 #define FLASH_OPTWRE            (1 << 9)
  81 #define FLASH_OBL_LAUNCH        (1 << 13)       /* except stm32f1x series */
  82
  83 /* FLASH_SR register bits */
  84
  85 #define FLASH_BSY               (1 << 0)
  86 #define FLASH_PGERR             (1 << 2)
  87 #define FLASH_WRPRTERR  (1 << 4)
  88 #define FLASH_EOP               (1 << 5)
  89
  90 /* STM32_FLASH_OBR bit definitions (reading) */
  91
  92 #define OPT_ERROR               0
  93 #define OPT_READOUT             1
  94 #define OPT_RDWDGSW             2
  95 #define OPT_RDRSTSTOP   3
  96 #define OPT_RDRSTSTDBY  4
  97 #define OPT_BFB2                5       /* dual flash bank only */
  98
  99 /* register unlock keys */
 100
 101 #define KEY1                    0x45670123
 102 #define KEY2                    0xCDEF89AB
 103
 104 /* timeout values */
 105
 106 #define FLASH_WRITE_TIMEOUT 10
 107 #define FLASH_ERASE_TIMEOUT 100
 108
 109 struct stm32x_options {
 110         uint8_t rdp;
 111         uint8_t user;
 112         uint16_t data;
 113         uint32_t protection;
 114 };
 115
 116 struct stm32x_flash_bank {
 117         struct stm32x_options option_bytes;
 118         int ppage_size;
 119         bool probed;
 120
 121         bool has_dual_banks;
 122         /* used to access dual flash bank stm32xl */
 123         bool can_load_options;
 124         uint32_t register_base;
 125         uint8_t default_rdp;
 126         int user_data_offset;
 127         int option_offset;
 128         uint32_t user_bank_size;
 129 };
 130
 131 static int stm32x_mass_erase(struct flash_bank *bank);
 132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
 133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 134                 uint32_t address, uint32_t count);
 135
 136 /* flash bank stm32x <base> <size> 0 0 <target#>
 137  */
 138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 139 {
 140         struct stm32x_flash_bank *stm32x_info;
 141
 142         if (CMD_ARGC < 6)
 143                 return ERROR_COMMAND_SYNTAX_ERROR;
 144
 145         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 146
 147         bank->driver_priv = stm32x_info;
 148         stm32x_info->probed = false;
 149         stm32x_info->has_dual_banks = false;
 150         stm32x_info->can_load_options = false;
 151         stm32x_info->register_base = FLASH_REG_BASE_B0;
 152         stm32x_info->user_bank_size = bank->size;
 153
 154         return ERROR_OK;
 155 }
 156
 157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 158 {
 159         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 160         return reg + stm32x_info->register_base;
 161 }
 162
 163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 164 {
 165         struct target *target = bank->target;
 166         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 167 }
 168
 169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 170 {
 171         struct target *target = bank->target;
 172         uint32_t status;
 173         int retval = ERROR_OK;
 174
 175         /* wait for busy to clear */
 176         for (;;) {
 177                 retval = stm32x_get_flash_status(bank, &status);
 178                 if (retval != ERROR_OK)
 179                         return retval;
 180                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 181                 if ((status & FLASH_BSY) == 0)
 182                         break;
 183                 if (timeout-- <= 0) {
 184                         LOG_ERROR("timed out waiting for flash");
 185                         return ERROR_FAIL;
 186                 }
 187                 alive_sleep(1);
 188         }
 189
 190         if (status & FLASH_WRPRTERR) {
 191                 LOG_ERROR("stm32x device protected");
 192                 retval = ERROR_FAIL;
 193         }
 194
 195         if (status & FLASH_PGERR) {
 196                 LOG_ERROR("stm32x device programming failed");
 197                 retval = ERROR_FAIL;
 198         }
 199
 200         /* Clear but report errors */
 201         if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
 202                 /* If this operation fails, we ignore it and report the original
 203                  * retval
 204                  */
 205                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 206                                 FLASH_WRPRTERR | FLASH_PGERR);
 207         }
 208         return retval;
 209 }
 210
 211 static int stm32x_check_operation_supported(struct flash_bank *bank)
 212 {
 213         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 214
 215         /* if we have a dual flash bank device then
 216          * we need to perform option byte stuff on bank0 only */
 217         if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
 218                 LOG_ERROR("Option byte operations must use bank 0");
 219                 return ERROR_FLASH_OPERATION_FAILED;
 220         }
 221
 222         return ERROR_OK;
 223 }
 224
 225 static int stm32x_read_options(struct flash_bank *bank)
 226 {
 227         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 228         struct target *target = bank->target;
 229         uint32_t option_bytes;
 230         int retval;
 231
 232         /* read user and read protection option bytes, user data option bytes */
 233         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
 234         if (retval != ERROR_OK)
 235                 return retval;
 236
 237         stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
 238         stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
 239         stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
 240
 241         /* read write protection option bytes */
 242         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
 243         if (retval != ERROR_OK)
 244                 return retval;
 245
 246         return ERROR_OK;
 247 }
 248
 249 static int stm32x_erase_options(struct flash_bank *bank)
 250 {
 251         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 252         struct target *target = bank->target;
 253
 254         /* read current options */
 255         stm32x_read_options(bank);
 256
 257         /* unlock flash registers */
 258         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 259         if (retval != ERROR_OK)
 260                 return retval;
 261
 262         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 263         if (retval != ERROR_OK)
 264                 return retval;
 265
 266         /* unlock option flash registers */
 267         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 268         if (retval != ERROR_OK)
 269                 return retval;
 270         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 271         if (retval != ERROR_OK)
 272                 return retval;
 273
 274         /* erase option bytes */
 275         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 276         if (retval != ERROR_OK)
 277                 return retval;
 278         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 279         if (retval != ERROR_OK)
 280                 return retval;
 281
 282         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 283         if (retval != ERROR_OK)
 284                 return retval;
 285
 286         /* clear read protection option byte
 287          * this will also force a device unlock if set */
 288         stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
 289
 290         return ERROR_OK;
 291 }
 292
 293 static int stm32x_write_options(struct flash_bank *bank)
 294 {
 295         struct stm32x_flash_bank *stm32x_info = NULL;
 296         struct target *target = bank->target;
 297
 298         stm32x_info = bank->driver_priv;
 299
 300         /* unlock flash registers */
 301         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 302         if (retval != ERROR_OK)
 303                 return retval;
 304         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 305         if (retval != ERROR_OK)
 306                 return retval;
 307
 308         /* unlock option flash registers */
 309         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 310         if (retval != ERROR_OK)
 311                 return retval;
 312         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 313         if (retval != ERROR_OK)
 314                 return retval;
 315
 316         /* program option bytes */
 317         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 318         if (retval != ERROR_OK)
 319                 return retval;
 320
 321         uint8_t opt_bytes[16];
 322
 323         target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
 324         target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
 325         target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
 326         target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
 327         target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
 328         target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
 329         target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
 330         target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
 331
 332         retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
 333         if (retval != ERROR_OK) {
 334                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 335                         LOG_ERROR("working area required to erase options bytes");
 336                 return retval;
 337         }
 338
 339         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 340         if (retval != ERROR_OK)
 341                 return retval;
 342
 343         return ERROR_OK;
 344 }
 345
 346 static int stm32x_protect_check(struct flash_bank *bank)
 347 {
 348         struct target *target = bank->target;
 349         uint32_t protection;
 350
 351         int retval = stm32x_check_operation_supported(bank);
 352         if (ERROR_OK != retval)
 353                 return retval;
 354
 355         /* medium density - each bit refers to a 4 sector protection block
 356          * high density - each bit refers to a 2 sector protection block
 357          * bit 31 refers to all remaining sectors in a bank */
 358         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 359         if (retval != ERROR_OK)
 360                 return retval;
 361
 362         for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
 363                 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
 364
 365         return ERROR_OK;
 366 }
 367
 368 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
 369                 unsigned int last)
 370 {
 371         struct target *target = bank->target;
 372
 373         if (bank->target->state != TARGET_HALTED) {
 374                 LOG_ERROR("Target not halted");
 375                 return ERROR_TARGET_NOT_HALTED;
 376         }
 377
 378         if ((first == 0) && (last == (bank->num_sectors - 1)))
 379                 return stm32x_mass_erase(bank);
 380
 381         /* unlock flash registers */
 382         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 383         if (retval != ERROR_OK)
 384                 return retval;
 385         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 386         if (retval != ERROR_OK)
 387                 return retval;
 388
 389         for (unsigned int i = first; i <= last; i++) {
 390                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 391                 if (retval != ERROR_OK)
 392                         return retval;
 393                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 394                                 bank->base + bank->sectors[i].offset);
 395                 if (retval != ERROR_OK)
 396                         return retval;
 397                 retval = target_write_u32(target,
 398                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 399                 if (retval != ERROR_OK)
 400                         return retval;
 401
 402                 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 403                 if (retval != ERROR_OK)
 404                         return retval;
 405
 406                 bank->sectors[i].is_erased = 1;
 407         }
 408
 409         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 410         if (retval != ERROR_OK)
 411                 return retval;
 412
 413         return ERROR_OK;
 414 }
 415
 416 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 417                 unsigned int last)
 418 {
 419         struct target *target = bank->target;
 420         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 421
 422         if (target->state != TARGET_HALTED) {
 423                 LOG_ERROR("Target not halted");
 424                 return ERROR_TARGET_NOT_HALTED;
 425         }
 426
 427         int retval = stm32x_check_operation_supported(bank);
 428         if (retval != ERROR_OK)
 429                 return retval;
 430
 431         retval = stm32x_erase_options(bank);
 432         if (retval != ERROR_OK) {
 433                 LOG_ERROR("stm32x failed to erase options");
 434                 return retval;
 435         }
 436
 437         for (unsigned int i = first; i <= last; i++) {
 438                 if (set)
 439                         stm32x_info->option_bytes.protection &= ~(1 << i);
 440                 else
 441                         stm32x_info->option_bytes.protection |= (1 << i);
 442         }
 443
 444         return stm32x_write_options(bank);
 445 }
 446
 447 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 448                 uint32_t address, uint32_t count)
 449 {
 450         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 451         struct target *target = bank->target;
 452         uint32_t buffer_size = 16384;
 453         struct working_area *write_algorithm;
 454         struct working_area *source;
 455         struct reg_param reg_params[5];
 456         struct armv7m_algorithm armv7m_info;
 457         int retval = ERROR_OK;
 458
 459         static const uint8_t stm32x_flash_write_code[] = {
 460 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
 461         };
 462
 463         /* flash write code */
 464         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 465                         &write_algorithm) != ERROR_OK) {
 466                 LOG_WARNING("no working area available, can't do block memory writes");
 467                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 468         }
 469
 470         retval = target_write_buffer(target, write_algorithm->address,
 471                         sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
 472         if (retval != ERROR_OK) {
 473                 target_free_working_area(target, write_algorithm);
 474                 return retval;
 475         }
 476
 477         /* memory buffer */
 478         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 479                 buffer_size /= 2;
 480                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 481                 if (buffer_size <= 256) {
 482                         /* we already allocated the writing code, but failed to get a
 483                          * buffer, free the algorithm */
 484                         target_free_working_area(target, write_algorithm);
 485
 486                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 487                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 488                 }
 489         }
 490
 491         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 492         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 493         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 494         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 495         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 496
 497         buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
 498         buf_set_u32(reg_params[1].value, 0, 32, count);
 499         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 500         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 501         buf_set_u32(reg_params[4].value, 0, 32, address);
 502
 503         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 504         armv7m_info.core_mode = ARM_MODE_THREAD;
 505
 506         retval = target_run_flash_async_algorithm(target, buffer, count, 2,
 507                         0, NULL,
 508                         5, reg_params,
 509                         source->address, source->size,
 510                         write_algorithm->address, 0,
 511                         &armv7m_info);
 512
 513         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 514                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 515                                 buf_get_u32(reg_params[4].value, 0, 32));
 516
 517                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
 518                         LOG_ERROR("flash memory not erased before writing");
 519                         /* Clear but report errors */
 520                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
 521                 }
 522
 523                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
 524                         LOG_ERROR("flash memory write protected");
 525                         /* Clear but report errors */
 526                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
 527                 }
 528         }
 529
 530         target_free_working_area(target, source);
 531         target_free_working_area(target, write_algorithm);
 532
 533         destroy_reg_param(&reg_params[0]);
 534         destroy_reg_param(&reg_params[1]);
 535         destroy_reg_param(&reg_params[2]);
 536         destroy_reg_param(&reg_params[3]);
 537         destroy_reg_param(&reg_params[4]);
 538
 539         return retval;
 540 }
 541
 542 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 543                 uint32_t offset, uint32_t count)
 544 {
 545         struct target *target = bank->target;
 546         uint8_t *new_buffer = NULL;
 547
 548         if (bank->target->state != TARGET_HALTED) {
 549                 LOG_ERROR("Target not halted");
 550                 return ERROR_TARGET_NOT_HALTED;
 551         }
 552
 553         if (offset & 0x1) {
 554                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 555                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 556         }
 557
 558         /* If there's an odd number of bytes, the data has to be padded. Duplicate
 559          * the buffer and use the normal code path with a single block write since
 560          * it's probably cheaper than to special case the last odd write using
 561          * discrete accesses. */
 562         if (count & 1) {
 563                 new_buffer = malloc(count + 1);
 564                 if (new_buffer == NULL) {
 565                         LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
 566                         return ERROR_FAIL;
 567                 }
 568                 LOG_INFO("odd number of bytes to write, padding with 0xff");
 569                 buffer = memcpy(new_buffer, buffer, count);
 570                 new_buffer[count++] = 0xff;
 571         }
 572
 573         uint32_t words_remaining = count / 2;
 574         int retval, retval2;
 575
 576         /* unlock flash registers */
 577         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 578         if (retval != ERROR_OK)
 579                 goto cleanup;
 580         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 581         if (retval != ERROR_OK)
 582                 goto cleanup;
 583
 584         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 585         if (retval != ERROR_OK)
 586                 goto cleanup;
 587
 588         /* try using a block write */
 589         retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
 590
 591         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 592                 /* if block write failed (no sufficient working area),
 593                  * we use normal (slow) single halfword accesses */
 594                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 595
 596                 while (words_remaining > 0) {
 597                         uint16_t value;
 598                         memcpy(&value, buffer, sizeof(uint16_t));
 599
 600                         retval = target_write_u16(target, bank->base + offset, value);
 601                         if (retval != ERROR_OK)
 602                                 goto reset_pg_and_lock;
 603
 604                         retval = stm32x_wait_status_busy(bank, 5);
 605                         if (retval != ERROR_OK)
 606                                 goto reset_pg_and_lock;
 607
 608                         words_remaining--;
 609                         buffer += 2;
 610                         offset += 2;
 611                 }
 612         }
 613
 614 reset_pg_and_lock:
 615         retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 616         if (retval == ERROR_OK)
 617                 retval = retval2;
 618
 619 cleanup:
 620         free(new_buffer);
 621         return retval;
 622 }
 623
 624 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 625 {
 626         struct target *target = bank->target;
 627         struct cortex_m_common *cortex_m = target_to_cm(target);
 628         uint32_t device_id_register = 0;
 629
 630         if (!target_was_examined(target)) {
 631                 LOG_ERROR("Target not examined yet");
 632                 return ERROR_FAIL;
 633         }
 634
 635         switch (cortex_m->core_info->partno) {
 636         case CORTEX_M0_PARTNO: /* STM32F0x devices */
 637                 device_id_register = 0x40015800;
 638                 break;
 639         case CORTEX_M3_PARTNO: /* STM32F1x devices */
 640                 device_id_register = 0xE0042000;
 641                 break;
 642         case CORTEX_M4_PARTNO: /* STM32F3x devices */
 643                 device_id_register = 0xE0042000;
 644                 break;
 645         default:
 646                 LOG_ERROR("Cannot identify target as a stm32x");
 647                 return ERROR_FAIL;
 648         }
 649
 650         /* read stm32 device id register */
 651         int retval = target_read_u32(target, device_id_register, device_id);
 652         if (retval != ERROR_OK)
 653                 return retval;
 654
 655         return retval;
 656 }
 657
 658 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
 659 {
 660         struct target *target = bank->target;
 661         struct cortex_m_common *cortex_m = target_to_cm(target);
 662         uint32_t flash_size_reg;
 663
 664         if (!target_was_examined(target)) {
 665                 LOG_ERROR("Target not examined yet");
 666                 return ERROR_FAIL;
 667         }
 668
 669         switch (cortex_m->core_info->partno) {
 670         case CORTEX_M0_PARTNO: /* STM32F0x devices */
 671                 flash_size_reg = 0x1FFFF7CC;
 672                 break;
 673         case CORTEX_M3_PARTNO: /* STM32F1x devices */
 674                 flash_size_reg = 0x1FFFF7E0;
 675                 break;
 676         case CORTEX_M4_PARTNO: /* STM32F3x devices */
 677                 flash_size_reg = 0x1FFFF7CC;
 678                 break;
 679         default:
 680                 LOG_ERROR("Cannot identify target as a stm32x");
 681                 return ERROR_FAIL;
 682         }
 683
 684         int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
 685         if (retval != ERROR_OK)
 686                 return retval;
 687
 688         return retval;
 689 }
 690
 691 static int stm32x_probe(struct flash_bank *bank)
 692 {
 693         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 694         uint16_t flash_size_in_kb;
 695         uint16_t max_flash_size_in_kb;
 696         uint32_t dbgmcu_idcode;
 697         int page_size;
 698         uint32_t base_address = 0x08000000;
 699
 700         stm32x_info->probed = false;
 701         stm32x_info->register_base = FLASH_REG_BASE_B0;
 702         stm32x_info->user_data_offset = 10;
 703         stm32x_info->option_offset = 0;
 704
 705         /* default factory read protection level 0 */
 706         stm32x_info->default_rdp = 0xA5;
 707
 708         /* read stm32 device id register */
 709         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 710         if (retval != ERROR_OK)
 711                 return retval;
 712
 713         LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
 714
 715         uint16_t device_id = dbgmcu_idcode & 0xfff;
 716         uint16_t rev_id = dbgmcu_idcode >> 16;
 717
 718         /* set page size, protection granularity and max flash size depending on family */
 719         switch (device_id) {
 720         case 0x440: /* stm32f05x */
 721                 page_size = 1024;
 722                 stm32x_info->ppage_size = 4;
 723                 max_flash_size_in_kb = 64;
 724                 stm32x_info->user_data_offset = 16;
 725                 stm32x_info->option_offset = 6;
 726                 stm32x_info->default_rdp = 0xAA;
 727                 stm32x_info->can_load_options = true;
 728                 break;
 729         case 0x444: /* stm32f03x */
 730         case 0x445: /* stm32f04x */
 731                 page_size = 1024;
 732                 stm32x_info->ppage_size = 4;
 733                 max_flash_size_in_kb = 32;
 734                 stm32x_info->user_data_offset = 16;
 735                 stm32x_info->option_offset = 6;
 736                 stm32x_info->default_rdp = 0xAA;
 737                 stm32x_info->can_load_options = true;
 738                 break;
 739         case 0x448: /* stm32f07x */
 740                 page_size = 2048;
 741                 stm32x_info->ppage_size = 4;
 742                 max_flash_size_in_kb = 128;
 743                 stm32x_info->user_data_offset = 16;
 744                 stm32x_info->option_offset = 6;
 745                 stm32x_info->default_rdp = 0xAA;
 746                 stm32x_info->can_load_options = true;
 747                 break;
 748         case 0x442: /* stm32f09x */
 749                 page_size = 2048;
 750                 stm32x_info->ppage_size = 4;
 751                 max_flash_size_in_kb = 256;
 752                 stm32x_info->user_data_offset = 16;
 753                 stm32x_info->option_offset = 6;
 754                 stm32x_info->default_rdp = 0xAA;
 755                 stm32x_info->can_load_options = true;
 756                 break;
 757         case 0x410: /* stm32f1x medium-density */
 758                 page_size = 1024;
 759                 stm32x_info->ppage_size = 4;
 760                 max_flash_size_in_kb = 128;
 761                 /* GigaDevice GD32F1x0 & GD32F3x0 series devices share DEV_ID
 762                    with STM32F101/2/3 medium-density line,
 763                    however they use a REV_ID different from any STM32 device.
 764                    The main difference is another offset of user option bits
 765                    (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
 766                    (FLASH_OBR/FMC_OBSTAT 0x4002201C).
 767                    This caused problems e.g. during flash block programming
 768                    because of unexpected active hardware watchog. */
 769                 switch (rev_id) {
 770                 case 0x1303: /* gd32f1x0 */
 771                         stm32x_info->user_data_offset = 16;
 772                         stm32x_info->option_offset = 6;
 773                         max_flash_size_in_kb = 64;
 774                         break;
 775                 case 0x1704: /* gd32f3x0 */
 776                         stm32x_info->user_data_offset = 16;
 777                         stm32x_info->option_offset = 6;
 778                         break;
 779                 }
 780                 break;
 781         case 0x412: /* stm32f1x low-density */
 782                 page_size = 1024;
 783                 stm32x_info->ppage_size = 4;
 784                 max_flash_size_in_kb = 32;
 785                 break;
 786         case 0x414: /* stm32f1x high-density */
 787                 page_size = 2048;
 788                 stm32x_info->ppage_size = 2;
 789                 max_flash_size_in_kb = 512;
 790                 break;
 791         case 0x418: /* stm32f1x connectivity */
 792                 page_size = 2048;
 793                 stm32x_info->ppage_size = 2;
 794                 max_flash_size_in_kb = 256;
 795                 break;
 796         case 0x430: /* stm32f1 XL-density (dual flash banks) */
 797                 page_size = 2048;
 798                 stm32x_info->ppage_size = 2;
 799                 max_flash_size_in_kb = 1024;
 800                 stm32x_info->has_dual_banks = true;
 801                 break;
 802         case 0x420: /* stm32f100xx low- and medium-density value line */
 803                 page_size = 1024;
 804                 stm32x_info->ppage_size = 4;
 805                 max_flash_size_in_kb = 128;
 806                 break;
 807         case 0x428: /* stm32f100xx high-density value line */
 808                 page_size = 2048;
 809                 stm32x_info->ppage_size = 4;
 810                 max_flash_size_in_kb = 512;
 811                 break;
 812         case 0x422: /* stm32f302/3xb/c */
 813                 page_size = 2048;
 814                 stm32x_info->ppage_size = 2;
 815                 max_flash_size_in_kb = 256;
 816                 stm32x_info->user_data_offset = 16;
 817                 stm32x_info->option_offset = 6;
 818                 stm32x_info->default_rdp = 0xAA;
 819                 stm32x_info->can_load_options = true;
 820                 break;
 821         case 0x446: /* stm32f303xD/E */
 822                 page_size = 2048;
 823                 stm32x_info->ppage_size = 2;
 824                 max_flash_size_in_kb = 512;
 825                 stm32x_info->user_data_offset = 16;
 826                 stm32x_info->option_offset = 6;
 827                 stm32x_info->default_rdp = 0xAA;
 828                 stm32x_info->can_load_options = true;
 829                 break;
 830         case 0x432: /* stm32f37x */
 831                 page_size = 2048;
 832                 stm32x_info->ppage_size = 2;
 833                 max_flash_size_in_kb = 256;
 834                 stm32x_info->user_data_offset = 16;
 835                 stm32x_info->option_offset = 6;
 836                 stm32x_info->default_rdp = 0xAA;
 837                 stm32x_info->can_load_options = true;
 838                 break;
 839         case 0x438: /* stm32f33x */
 840         case 0x439: /* stm32f302x6/8 */
 841                 page_size = 2048;
 842                 stm32x_info->ppage_size = 2;
 843                 max_flash_size_in_kb = 64;
 844                 stm32x_info->user_data_offset = 16;
 845                 stm32x_info->option_offset = 6;
 846                 stm32x_info->default_rdp = 0xAA;
 847                 stm32x_info->can_load_options = true;
 848                 break;
 849         default:
 850                 LOG_WARNING("Cannot identify target as a STM32 family.");
 851                 return ERROR_FAIL;
 852         }
 853
 854         /* get flash size from target. */
 855         retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
 856
 857         /* failed reading flash size or flash size invalid (early silicon),
 858          * default to max target family */
 859         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 860                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 861                         max_flash_size_in_kb);
 862                 flash_size_in_kb = max_flash_size_in_kb;
 863         }
 864
 865         if (stm32x_info->has_dual_banks) {
 866                 /* split reported size into matching bank */
 867                 if (bank->base != 0x08080000) {
 868                         /* bank 0 will be fixed 512k */
 869                         flash_size_in_kb = 512;
 870                 } else {
 871                         flash_size_in_kb -= 512;
 872                         /* bank1 also uses a register offset */
 873                         stm32x_info->register_base = FLASH_REG_BASE_B1;
 874                         base_address = 0x08080000;
 875                 }
 876         }
 877
 878         /* if the user sets the size manually then ignore the probed value
 879          * this allows us to work around devices that have a invalid flash size register value */
 880         if (stm32x_info->user_bank_size) {
 881                 LOG_INFO("ignoring flash probed value, using configured bank size");
 882                 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
 883         }
 884
 885         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 886
 887         /* did we assign flash size? */
 888         assert(flash_size_in_kb != 0xffff);
 889
 890         /* calculate numbers of pages */
 891         int num_pages = flash_size_in_kb * 1024 / page_size;
 892
 893         /* check that calculation result makes sense */
 894         assert(num_pages > 0);
 895
 896         free(bank->sectors);
 897         bank->sectors = NULL;
 898
 899         free(bank->prot_blocks);
 900         bank->prot_blocks = NULL;
 901
 902         bank->base = base_address;
 903         bank->size = (num_pages * page_size);
 904
 905         bank->num_sectors = num_pages;
 906         bank->sectors = alloc_block_array(0, page_size, num_pages);
 907         if (!bank->sectors)
 908                 return ERROR_FAIL;
 909
 910         /* calculate number of write protection blocks */
 911         int num_prot_blocks = num_pages / stm32x_info->ppage_size;
 912         if (num_prot_blocks > 32)
 913                 num_prot_blocks = 32;
 914
 915         bank->num_prot_blocks = num_prot_blocks;
 916         bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
 917         if (!bank->prot_blocks)
 918                 return ERROR_FAIL;
 919
 920         if (num_prot_blocks == 32)
 921                 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
 922
 923         stm32x_info->probed = true;
 924
 925         return ERROR_OK;
 926 }
 927
 928 static int stm32x_auto_probe(struct flash_bank *bank)
 929 {
 930         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 931         if (stm32x_info->probed)
 932                 return ERROR_OK;
 933         return stm32x_probe(bank);
 934 }
 935
 936 #if 0
 937 COMMAND_HANDLER(stm32x_handle_part_id_command)
 938 {
 939         return ERROR_OK;
 940 }
 941 #endif
 942
 943 static const char *get_stm32f0_revision(uint16_t rev_id)
 944 {
 945         const char *rev_str = NULL;
 946
 947         switch (rev_id) {
 948         case 0x1000:
 949                 rev_str = "1.0";
 950                 break;
 951         case 0x2000:
 952                 rev_str = "2.0";
 953                 break;
 954         }
 955         return rev_str;
 956 }
 957
 958 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
 959 {
 960         uint32_t dbgmcu_idcode;
 961
 962         /* read stm32 device id register */
 963         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 964         if (retval != ERROR_OK)
 965                 return retval;
 966
 967         uint16_t device_id = dbgmcu_idcode & 0xfff;
 968         uint16_t rev_id = dbgmcu_idcode >> 16;
 969         const char *device_str;
 970         const char *rev_str = NULL;
 971
 972         switch (device_id) {
 973         case 0x410:
 974                 device_str = "STM32F10x (Medium Density)";
 975
 976                 switch (rev_id) {
 977                 case 0x0000:
 978                         rev_str = "A";
 979                         break;
 980
 981                 case 0x1303: /* gd32f1x0 */
 982                         device_str = "GD32F1x0";
 983                         break;
 984
 985                 case 0x1704: /* gd32f3x0 */
 986                         device_str = "GD32F3x0";
 987                         break;
 988
 989                 case 0x2000:
 990                         rev_str = "B";
 991                         break;
 992
 993                 case 0x2001:
 994                         rev_str = "Z";
 995                         break;
 996
 997                 case 0x2003:
 998                         rev_str = "Y";
 999                         break;
1000                 }
1001                 break;
1002
1003         case 0x412:
1004                 device_str = "STM32F10x (Low Density)";
1005
1006                 switch (rev_id) {
1007                 case 0x1000:
1008                         rev_str = "A";
1009                         break;
1010                 }
1011                 break;
1012
1013         case 0x414:
1014                 device_str = "STM32F10x (High Density)";
1015
1016                 switch (rev_id) {
1017                 case 0x1000:
1018                         rev_str = "A";
1019                         break;
1020
1021                 case 0x1001:
1022                         rev_str = "Z";
1023                         break;
1024
1025                 case 0x1003:
1026                         rev_str = "Y";
1027                         break;
1028                 }
1029                 break;
1030
1031         case 0x418:
1032                 device_str = "STM32F10x (Connectivity)";
1033
1034                 switch (rev_id) {
1035                 case 0x1000:
1036                         rev_str = "A";
1037                         break;
1038
1039                 case 0x1001:
1040                         rev_str = "Z";
1041                         break;
1042                 }
1043                 break;
1044
1045         case 0x420:
1046                 device_str = "STM32F100 (Low/Medium Density)";
1047
1048                 switch (rev_id) {
1049                 case 0x1000:
1050                         rev_str = "A";
1051                         break;
1052
1053                 case 0x1001:
1054                         rev_str = "Z";
1055                         break;
1056                 }
1057                 break;
1058
1059         case 0x422:
1060                 device_str = "STM32F302xB/C";
1061
1062                 switch (rev_id) {
1063                 case 0x1000:
1064                         rev_str = "A";
1065                         break;
1066
1067                 case 0x1001:
1068                         rev_str = "Z";
1069                         break;
1070
1071                 case 0x1003:
1072                         rev_str = "Y";
1073                         break;
1074
1075                 case 0x2000:
1076                         rev_str = "B";
1077                         break;
1078                 }
1079                 break;
1080
1081         case 0x428:
1082                 device_str = "STM32F100 (High Density)";
1083
1084                 switch (rev_id) {
1085                 case 0x1000:
1086                         rev_str = "A";
1087                         break;
1088
1089                 case 0x1001:
1090                         rev_str = "Z";
1091                         break;
1092                 }
1093                 break;
1094
1095         case 0x430:
1096                 device_str = "STM32F10x (XL Density)";
1097
1098                 switch (rev_id) {
1099                 case 0x1000:
1100                         rev_str = "A";
1101                         break;
1102                 }
1103                 break;
1104
1105         case 0x432:
1106                 device_str = "STM32F37x";
1107
1108                 switch (rev_id) {
1109                 case 0x1000:
1110                         rev_str = "A";
1111                         break;
1112
1113                 case 0x2000:
1114                         rev_str = "B";
1115                         break;
1116                 }
1117                 break;
1118
1119         case 0x438:
1120                 device_str = "STM32F33x";
1121
1122                 switch (rev_id) {
1123                 case 0x1000:
1124                         rev_str = "A";
1125                         break;
1126                 }
1127                 break;
1128
1129         case 0x439:
1130                 device_str = "STM32F302x6/8";
1131
1132                 switch (rev_id) {
1133                 case 0x1000:
1134                         rev_str = "A";
1135                         break;
1136
1137                 case 0x1001:
1138                         rev_str = "Z";
1139                         break;
1140                 }
1141                 break;
1142
1143         case 0x444:
1144                 device_str = "STM32F03x";
1145                 rev_str = get_stm32f0_revision(rev_id);
1146                 break;
1147
1148         case 0x440:
1149                 device_str = "STM32F05x";
1150                 rev_str = get_stm32f0_revision(rev_id);
1151                 break;
1152
1153         case 0x445:
1154                 device_str = "STM32F04x";
1155                 rev_str = get_stm32f0_revision(rev_id);
1156                 break;
1157
1158         case 0x446:
1159                 device_str = "STM32F303xD/E";
1160                 switch (rev_id) {
1161                 case 0x1000:
1162                         rev_str = "A";
1163                         break;
1164                 }
1165                 break;
1166
1167         case 0x448:
1168                 device_str = "STM32F07x";
1169                 rev_str = get_stm32f0_revision(rev_id);
1170                 break;
1171
1172         case 0x442:
1173                 device_str = "STM32F09x";
1174                 rev_str = get_stm32f0_revision(rev_id);
1175                 break;
1176
1177         default:
1178                 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1179                 return ERROR_FAIL;
1180         }
1181
1182         if (rev_str != NULL)
1183                 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1184         else
1185                 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1186
1187         return ERROR_OK;
1188 }
1189
1190 COMMAND_HANDLER(stm32x_handle_lock_command)
1191 {
1192         struct target *target = NULL;
1193         struct stm32x_flash_bank *stm32x_info = NULL;
1194
1195         if (CMD_ARGC < 1)
1196                 return ERROR_COMMAND_SYNTAX_ERROR;
1197
1198         struct flash_bank *bank;
1199         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1200         if (ERROR_OK != retval)
1201                 return retval;
1202
1203         stm32x_info = bank->driver_priv;
1204
1205         target = bank->target;
1206
1207         if (target->state != TARGET_HALTED) {
1208                 LOG_ERROR("Target not halted");
1209                 return ERROR_TARGET_NOT_HALTED;
1210         }
1211
1212         retval = stm32x_check_operation_supported(bank);
1213         if (ERROR_OK != retval)
1214                 return retval;
1215
1216         if (stm32x_erase_options(bank) != ERROR_OK) {
1217                 command_print(CMD, "stm32x failed to erase options");
1218                 return ERROR_OK;
1219         }
1220
1221         /* set readout protection */
1222         stm32x_info->option_bytes.rdp = 0;
1223
1224         if (stm32x_write_options(bank) != ERROR_OK) {
1225                 command_print(CMD, "stm32x failed to lock device");
1226                 return ERROR_OK;
1227         }
1228
1229         command_print(CMD, "stm32x locked");
1230
1231         return ERROR_OK;
1232 }
1233
1234 COMMAND_HANDLER(stm32x_handle_unlock_command)
1235 {
1236         struct target *target = NULL;
1237
1238         if (CMD_ARGC < 1)
1239                 return ERROR_COMMAND_SYNTAX_ERROR;
1240
1241         struct flash_bank *bank;
1242         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1243         if (ERROR_OK != retval)
1244                 return retval;
1245
1246         target = bank->target;
1247
1248         if (target->state != TARGET_HALTED) {
1249                 LOG_ERROR("Target not halted");
1250                 return ERROR_TARGET_NOT_HALTED;
1251         }
1252
1253         retval = stm32x_check_operation_supported(bank);
1254         if (ERROR_OK != retval)
1255                 return retval;
1256
1257         if (stm32x_erase_options(bank) != ERROR_OK) {
1258                 command_print(CMD, "stm32x failed to erase options");
1259                 return ERROR_OK;
1260         }
1261
1262         if (stm32x_write_options(bank) != ERROR_OK) {
1263                 command_print(CMD, "stm32x failed to unlock device");
1264                 return ERROR_OK;
1265         }
1266
1267         command_print(CMD, "stm32x unlocked.\n"
1268                         "INFO: a reset or power cycle is required "
1269                         "for the new settings to take effect.");
1270
1271         return ERROR_OK;
1272 }
1273
1274 COMMAND_HANDLER(stm32x_handle_options_read_command)
1275 {
1276         uint32_t optionbyte, protection;
1277         struct target *target = NULL;
1278         struct stm32x_flash_bank *stm32x_info = NULL;
1279
1280         if (CMD_ARGC < 1)
1281                 return ERROR_COMMAND_SYNTAX_ERROR;
1282
1283         struct flash_bank *bank;
1284         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1285         if (ERROR_OK != retval)
1286                 return retval;
1287
1288         stm32x_info = bank->driver_priv;
1289
1290         target = bank->target;
1291
1292         if (target->state != TARGET_HALTED) {
1293                 LOG_ERROR("Target not halted");
1294                 return ERROR_TARGET_NOT_HALTED;
1295         }
1296
1297         retval = stm32x_check_operation_supported(bank);
1298         if (ERROR_OK != retval)
1299                 return retval;
1300
1301         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1302         if (retval != ERROR_OK)
1303                 return retval;
1304
1305         uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1306
1307         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1308         if (retval != ERROR_OK)
1309                 return retval;
1310
1311         if (optionbyte & (1 << OPT_ERROR))
1312                 command_print(CMD, "option byte complement error");
1313
1314         command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1315         command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1316
1317         command_print(CMD, "read protection: %s",
1318                                 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1319
1320         /* user option bytes are offset depending on variant */
1321         optionbyte >>= stm32x_info->option_offset;
1322
1323         command_print(CMD, "watchdog: %sware",
1324                                 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1325
1326         command_print(CMD, "stop mode: %sreset generated upon entry",
1327                                 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1328
1329         command_print(CMD, "standby mode: %sreset generated upon entry",
1330                                 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1331
1332         if (stm32x_info->has_dual_banks)
1333                 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1334
1335         command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1336
1337         return ERROR_OK;
1338 }
1339
1340 COMMAND_HANDLER(stm32x_handle_options_write_command)
1341 {
1342         struct target *target = NULL;
1343         struct stm32x_flash_bank *stm32x_info = NULL;
1344         uint8_t optionbyte;
1345         uint16_t useropt;
1346
1347         if (CMD_ARGC < 2)
1348                 return ERROR_COMMAND_SYNTAX_ERROR;
1349
1350         struct flash_bank *bank;
1351         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1352         if (ERROR_OK != retval)
1353                 return retval;
1354
1355         stm32x_info = bank->driver_priv;
1356
1357         target = bank->target;
1358
1359         if (target->state != TARGET_HALTED) {
1360                 LOG_ERROR("Target not halted");
1361                 return ERROR_TARGET_NOT_HALTED;
1362         }
1363
1364         retval = stm32x_check_operation_supported(bank);
1365         if (ERROR_OK != retval)
1366                 return retval;
1367
1368         retval = stm32x_read_options(bank);
1369         if (ERROR_OK != retval)
1370                 return retval;
1371
1372         /* start with current options */
1373         optionbyte = stm32x_info->option_bytes.user;
1374         useropt = stm32x_info->option_bytes.data;
1375
1376         /* skip over flash bank */
1377         CMD_ARGC--;
1378         CMD_ARGV++;
1379
1380         while (CMD_ARGC) {
1381                 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1382                         optionbyte |= (1 << 0);
1383                 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1384                         optionbyte &= ~(1 << 0);
1385                 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1386                         optionbyte |= (1 << 1);
1387                 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1388                         optionbyte &= ~(1 << 1);
1389                 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1390                         optionbyte |= (1 << 2);
1391                 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1392                         optionbyte &= ~(1 << 2);
1393                 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1394                         if (CMD_ARGC < 2)
1395                                 return ERROR_COMMAND_SYNTAX_ERROR;
1396                         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1397                         CMD_ARGC--;
1398                         CMD_ARGV++;
1399                 } else if (stm32x_info->has_dual_banks) {
1400                         if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1401                                 optionbyte |= (1 << 3);
1402                         else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1403                                 optionbyte &= ~(1 << 3);
1404                         else
1405                                 return ERROR_COMMAND_SYNTAX_ERROR;
1406                 } else
1407                         return ERROR_COMMAND_SYNTAX_ERROR;
1408                 CMD_ARGC--;
1409                 CMD_ARGV++;
1410         }
1411
1412         if (stm32x_erase_options(bank) != ERROR_OK) {
1413                 command_print(CMD, "stm32x failed to erase options");
1414                 return ERROR_OK;
1415         }
1416
1417         stm32x_info->option_bytes.user = optionbyte;
1418         stm32x_info->option_bytes.data = useropt;
1419
1420         if (stm32x_write_options(bank) != ERROR_OK) {
1421                 command_print(CMD, "stm32x failed to write options");
1422                 return ERROR_OK;
1423         }
1424
1425         command_print(CMD, "stm32x write options complete.\n"
1426                                 "INFO: %spower cycle is required "
1427                                 "for the new settings to take effect.",
1428                                 stm32x_info->can_load_options
1429                                         ? "'stm32f1x options_load' command or " : "");
1430
1431         return ERROR_OK;
1432 }
1433
1434 COMMAND_HANDLER(stm32x_handle_options_load_command)
1435 {
1436         if (CMD_ARGC < 1)
1437                 return ERROR_COMMAND_SYNTAX_ERROR;
1438
1439         struct flash_bank *bank;
1440         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1441         if (ERROR_OK != retval)
1442                 return retval;
1443
1444         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1445
1446         if (!stm32x_info->can_load_options) {
1447                 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1448                         "required instead.");
1449                 return ERROR_FAIL;
1450         }
1451
1452         struct target *target = bank->target;
1453
1454         if (target->state != TARGET_HALTED) {
1455                 LOG_ERROR("Target not halted");
1456                 return ERROR_TARGET_NOT_HALTED;
1457         }
1458
1459         retval = stm32x_check_operation_supported(bank);
1460         if (ERROR_OK != retval)
1461                 return retval;
1462
1463         /* unlock option flash registers */
1464         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1465         if (retval != ERROR_OK)
1466                 return retval;
1467         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1468         if (retval != ERROR_OK)
1469                 return retval;
1470
1471         /* force re-load of option bytes - generates software reset */
1472         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1473         if (retval != ERROR_OK)
1474                 return retval;
1475
1476         return ERROR_OK;
1477 }
1478
1479 static int stm32x_mass_erase(struct flash_bank *bank)
1480 {
1481         struct target *target = bank->target;
1482
1483         if (target->state != TARGET_HALTED) {
1484                 LOG_ERROR("Target not halted");
1485                 return ERROR_TARGET_NOT_HALTED;
1486         }
1487
1488         /* unlock option flash registers */
1489         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1490         if (retval != ERROR_OK)
1491                 return retval;
1492         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1493         if (retval != ERROR_OK)
1494                 return retval;
1495
1496         /* mass erase flash memory */
1497         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1498         if (retval != ERROR_OK)
1499                 return retval;
1500         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1501                         FLASH_MER | FLASH_STRT);
1502         if (retval != ERROR_OK)
1503                 return retval;
1504
1505         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1506         if (retval != ERROR_OK)
1507                 return retval;
1508
1509         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1510         if (retval != ERROR_OK)
1511                 return retval;
1512
1513         return ERROR_OK;
1514 }
1515
1516 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1517 {
1518         if (CMD_ARGC < 1)
1519                 return ERROR_COMMAND_SYNTAX_ERROR;
1520
1521         struct flash_bank *bank;
1522         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1523         if (ERROR_OK != retval)
1524                 return retval;
1525
1526         retval = stm32x_mass_erase(bank);
1527         if (retval == ERROR_OK) {
1528                 /* set all sectors as erased */
1529                 for (unsigned int i = 0; i < bank->num_sectors; i++)
1530                         bank->sectors[i].is_erased = 1;
1531
1532                 command_print(CMD, "stm32x mass erase complete");
1533         } else
1534                 command_print(CMD, "stm32x mass erase failed");
1535
1536         return retval;
1537 }
1538
1539 static const struct command_registration stm32x_exec_command_handlers[] = {
1540         {
1541                 .name = "lock",
1542                 .handler = stm32x_handle_lock_command,
1543                 .mode = COMMAND_EXEC,
1544                 .usage = "bank_id",
1545                 .help = "Lock entire flash device.",
1546         },
1547         {
1548                 .name = "unlock",
1549                 .handler = stm32x_handle_unlock_command,
1550                 .mode = COMMAND_EXEC,
1551                 .usage = "bank_id",
1552                 .help = "Unlock entire protected flash device.",
1553         },
1554         {
1555                 .name = "mass_erase",
1556                 .handler = stm32x_handle_mass_erase_command,
1557                 .mode = COMMAND_EXEC,
1558                 .usage = "bank_id",
1559                 .help = "Erase entire flash device.",
1560         },
1561         {
1562                 .name = "options_read",
1563                 .handler = stm32x_handle_options_read_command,
1564                 .mode = COMMAND_EXEC,
1565                 .usage = "bank_id",
1566                 .help = "Read and display device option bytes.",
1567         },
1568         {
1569                 .name = "options_write",
1570                 .handler = stm32x_handle_options_write_command,
1571                 .mode = COMMAND_EXEC,
1572                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1573                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1574                         "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1575                 .help = "Replace bits in device option bytes.",
1576         },
1577         {
1578                 .name = "options_load",
1579                 .handler = stm32x_handle_options_load_command,
1580                 .mode = COMMAND_EXEC,
1581                 .usage = "bank_id",
1582                 .help = "Force re-load of device option bytes.",
1583         },
1584         COMMAND_REGISTRATION_DONE
1585 };
1586
1587 static const struct command_registration stm32x_command_handlers[] = {
1588         {
1589                 .name = "stm32f1x",
1590                 .mode = COMMAND_ANY,
1591                 .help = "stm32f1x flash command group",
1592                 .usage = "",
1593                 .chain = stm32x_exec_command_handlers,
1594         },
1595         COMMAND_REGISTRATION_DONE
1596 };
1597
1598 const struct flash_driver stm32f1x_flash = {
1599         .name = "stm32f1x",
1600         .commands = stm32x_command_handlers,
1601         .flash_bank_command = stm32x_flash_bank_command,
1602         .erase = stm32x_erase,
1603         .protect = stm32x_protect,
1604         .write = stm32x_write,
1605         .read = default_flash_read,
1606         .probe = stm32x_probe,
1607         .auto_probe = stm32x_auto_probe,
1608         .erase_check = default_flash_blank_check,
1609         .protect_check = stm32x_protect_check,
1610         .info = get_stm32x_info,
1611         .free_driver_priv = default_flash_free_driver_priv,
1612 };