1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
34 /* stm32x register locations */
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
60 /* option byte location */
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
71 /* FLASH_CR register bits */
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
83 /* FLASH_SR register bits */
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
90 /* STM32_FLASH_OBR bit definitions (reading) */
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
99 /* register unlock keys */
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
109 struct stm32x_options {
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
126 int user_data_offset;
128 uint32_t user_bank_size;
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t count);
136 /* flash bank stm32x <base> <size> 0 0 <target#>
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
140 struct stm32x_flash_bank *stm32x_info;
143 return ERROR_COMMAND_SYNTAX_ERROR;
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = false;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
159 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
160 return reg + stm32x_info->register_base;
163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
165 struct target *target = bank->target;
166 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
171 struct target *target = bank->target;
173 int retval = ERROR_OK;
175 /* wait for busy to clear */
177 retval = stm32x_get_flash_status(bank, &status);
178 if (retval != ERROR_OK)
180 LOG_DEBUG("status: 0x%" PRIx32 "", status);
181 if ((status & FLASH_BSY) == 0)
183 if (timeout-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
190 if (status & FLASH_WRPRTERR) {
191 LOG_ERROR("stm32x device protected");
195 if (status & FLASH_PGERR) {
196 LOG_ERROR("stm32x device programming failed");
200 /* Clear but report errors */
201 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
202 /* If this operation fails, we ignore it and report the original
205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
206 FLASH_WRPRTERR | FLASH_PGERR);
211 static int stm32x_check_operation_supported(struct flash_bank *bank)
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
218 LOG_ERROR("Option Byte Operation's must use bank0");
219 return ERROR_FLASH_OPERATION_FAILED;
225 static int stm32x_read_options(struct flash_bank *bank)
227 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
228 struct target *target = bank->target;
229 uint32_t option_bytes;
232 /* read user and read protection option bytes, user data option bytes */
233 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
234 if (retval != ERROR_OK)
237 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
238 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
239 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
241 /* read write protection option bytes */
242 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
243 if (retval != ERROR_OK)
249 static int stm32x_erase_options(struct flash_bank *bank)
251 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
252 struct target *target = bank->target;
254 /* read current options */
255 stm32x_read_options(bank);
257 /* unlock flash registers */
258 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
259 if (retval != ERROR_OK)
262 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
263 if (retval != ERROR_OK)
266 /* unlock option flash registers */
267 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
268 if (retval != ERROR_OK)
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
271 if (retval != ERROR_OK)
274 /* erase option bytes */
275 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
276 if (retval != ERROR_OK)
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
282 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
283 if (retval != ERROR_OK)
286 /* clear read protection option byte
287 * this will also force a device unlock if set */
288 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
293 static int stm32x_write_options(struct flash_bank *bank)
295 struct stm32x_flash_bank *stm32x_info = NULL;
296 struct target *target = bank->target;
298 stm32x_info = bank->driver_priv;
300 /* unlock flash registers */
301 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
302 if (retval != ERROR_OK)
304 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
305 if (retval != ERROR_OK)
308 /* unlock option flash registers */
309 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
310 if (retval != ERROR_OK)
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
313 if (retval != ERROR_OK)
316 /* program option bytes */
317 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
318 if (retval != ERROR_OK)
321 uint8_t opt_bytes[16];
323 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
324 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
325 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
326 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
327 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
328 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
329 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
330 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
332 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
333 if (retval != ERROR_OK) {
334 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
335 LOG_ERROR("working area required to erase options bytes");
339 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
340 if (retval != ERROR_OK)
346 static int stm32x_protect_check(struct flash_bank *bank)
348 struct target *target = bank->target;
351 int retval = stm32x_check_operation_supported(bank);
352 if (ERROR_OK != retval)
355 /* medium density - each bit refers to a 4 sector protection block
356 * high density - each bit refers to a 2 sector protection block
357 * bit 31 refers to all remaining sectors in a bank */
358 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
359 if (retval != ERROR_OK)
362 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
363 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
368 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
371 struct target *target = bank->target;
373 if (bank->target->state != TARGET_HALTED) {
374 LOG_ERROR("Target not halted");
375 return ERROR_TARGET_NOT_HALTED;
378 if ((first == 0) && (last == (bank->num_sectors - 1)))
379 return stm32x_mass_erase(bank);
381 /* unlock flash registers */
382 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
383 if (retval != ERROR_OK)
385 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
386 if (retval != ERROR_OK)
389 for (unsigned int i = first; i <= last; i++) {
390 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
391 if (retval != ERROR_OK)
393 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
394 bank->base + bank->sectors[i].offset);
395 if (retval != ERROR_OK)
397 retval = target_write_u32(target,
398 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
399 if (retval != ERROR_OK)
402 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
403 if (retval != ERROR_OK)
406 bank->sectors[i].is_erased = 1;
409 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
410 if (retval != ERROR_OK)
416 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
419 struct target *target = bank->target;
420 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
422 if (target->state != TARGET_HALTED) {
423 LOG_ERROR("Target not halted");
424 return ERROR_TARGET_NOT_HALTED;
427 int retval = stm32x_check_operation_supported(bank);
428 if (retval != ERROR_OK)
431 retval = stm32x_erase_options(bank);
432 if (retval != ERROR_OK) {
433 LOG_ERROR("stm32x failed to erase options");
437 for (unsigned int i = first; i <= last; i++) {
439 stm32x_info->option_bytes.protection &= ~(1 << i);
441 stm32x_info->option_bytes.protection |= (1 << i);
444 return stm32x_write_options(bank);
447 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
448 uint32_t address, uint32_t count)
450 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
451 struct target *target = bank->target;
452 uint32_t buffer_size = 16384;
453 struct working_area *write_algorithm;
454 struct working_area *source;
455 struct reg_param reg_params[5];
456 struct armv7m_algorithm armv7m_info;
457 int retval = ERROR_OK;
459 static const uint8_t stm32x_flash_write_code[] = {
460 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
463 /* flash write code */
464 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
465 &write_algorithm) != ERROR_OK) {
466 LOG_WARNING("no working area available, can't do block memory writes");
467 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
470 retval = target_write_buffer(target, write_algorithm->address,
471 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
472 if (retval != ERROR_OK) {
473 target_free_working_area(target, write_algorithm);
478 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
480 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
481 if (buffer_size <= 256) {
482 /* we already allocated the writing code, but failed to get a
483 * buffer, free the algorithm */
484 target_free_working_area(target, write_algorithm);
486 LOG_WARNING("no large enough working area available, can't do block memory writes");
487 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
491 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
492 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
493 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer start */
494 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* buffer end */
495 init_reg_param(®_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
497 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
498 buf_set_u32(reg_params[1].value, 0, 32, count);
499 buf_set_u32(reg_params[2].value, 0, 32, source->address);
500 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
501 buf_set_u32(reg_params[4].value, 0, 32, address);
503 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
504 armv7m_info.core_mode = ARM_MODE_THREAD;
506 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
509 source->address, source->size,
510 write_algorithm->address, 0,
513 if (retval == ERROR_FLASH_OPERATION_FAILED) {
514 LOG_ERROR("flash write failed at address 0x%"PRIx32,
515 buf_get_u32(reg_params[4].value, 0, 32));
517 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
518 LOG_ERROR("flash memory not erased before writing");
519 /* Clear but report errors */
520 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
523 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
524 LOG_ERROR("flash memory write protected");
525 /* Clear but report errors */
526 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
530 target_free_working_area(target, source);
531 target_free_working_area(target, write_algorithm);
533 destroy_reg_param(®_params[0]);
534 destroy_reg_param(®_params[1]);
535 destroy_reg_param(®_params[2]);
536 destroy_reg_param(®_params[3]);
537 destroy_reg_param(®_params[4]);
542 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
543 uint32_t offset, uint32_t count)
545 struct target *target = bank->target;
546 uint8_t *new_buffer = NULL;
548 if (bank->target->state != TARGET_HALTED) {
549 LOG_ERROR("Target not halted");
550 return ERROR_TARGET_NOT_HALTED;
554 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
555 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
558 /* If there's an odd number of bytes, the data has to be padded. Duplicate
559 * the buffer and use the normal code path with a single block write since
560 * it's probably cheaper than to special case the last odd write using
561 * discrete accesses. */
563 new_buffer = malloc(count + 1);
564 if (new_buffer == NULL) {
565 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
568 LOG_INFO("odd number of bytes to write, padding with 0xff");
569 buffer = memcpy(new_buffer, buffer, count);
570 new_buffer[count++] = 0xff;
573 uint32_t words_remaining = count / 2;
576 /* unlock flash registers */
577 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
578 if (retval != ERROR_OK)
580 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
581 if (retval != ERROR_OK)
584 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
585 if (retval != ERROR_OK)
588 /* try using a block write */
589 retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
591 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
592 /* if block write failed (no sufficient working area),
593 * we use normal (slow) single halfword accesses */
594 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
596 while (words_remaining > 0) {
598 memcpy(&value, buffer, sizeof(uint16_t));
600 retval = target_write_u16(target, bank->base + offset, value);
601 if (retval != ERROR_OK)
602 goto reset_pg_and_lock;
604 retval = stm32x_wait_status_busy(bank, 5);
605 if (retval != ERROR_OK)
606 goto reset_pg_and_lock;
615 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
616 if (retval == ERROR_OK)
626 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
628 /* This check the device CPUID core register to detect
629 * the M0 from the M3 devices. */
631 struct target *target = bank->target;
632 uint32_t cpuid, device_id_register = 0;
634 /* Get the CPUID from the ARM Core
635 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
636 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
637 if (retval != ERROR_OK)
640 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
641 /* 0xC20 is M0 devices */
642 device_id_register = 0x40015800;
643 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
644 /* 0xC23 is M3 devices */
645 device_id_register = 0xE0042000;
646 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
647 /* 0xC24 is M4 devices */
648 device_id_register = 0xE0042000;
650 LOG_ERROR("Cannot identify target as a stm32x");
654 /* read stm32 device id register */
655 retval = target_read_u32(target, device_id_register, device_id);
656 if (retval != ERROR_OK)
662 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
664 struct target *target = bank->target;
665 uint32_t cpuid, flash_size_reg;
667 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
668 if (retval != ERROR_OK)
671 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
672 /* 0xC20 is M0 devices */
673 flash_size_reg = 0x1FFFF7CC;
674 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
675 /* 0xC23 is M3 devices */
676 flash_size_reg = 0x1FFFF7E0;
677 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
678 /* 0xC24 is M4 devices */
679 flash_size_reg = 0x1FFFF7CC;
681 LOG_ERROR("Cannot identify target as a stm32x");
685 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
686 if (retval != ERROR_OK)
692 static int stm32x_probe(struct flash_bank *bank)
694 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
695 uint16_t flash_size_in_kb;
696 uint16_t max_flash_size_in_kb;
699 uint32_t base_address = 0x08000000;
701 stm32x_info->probed = false;
702 stm32x_info->register_base = FLASH_REG_BASE_B0;
703 stm32x_info->user_data_offset = 10;
704 stm32x_info->option_offset = 0;
706 /* default factory read protection level 0 */
707 stm32x_info->default_rdp = 0xA5;
709 /* read stm32 device id register */
710 int retval = stm32x_get_device_id(bank, &device_id);
711 if (retval != ERROR_OK)
714 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
716 /* set page size, protection granularity and max flash size depending on family */
717 switch (device_id & 0xfff) {
718 case 0x440: /* stm32f05x */
720 stm32x_info->ppage_size = 4;
721 max_flash_size_in_kb = 64;
722 stm32x_info->user_data_offset = 16;
723 stm32x_info->option_offset = 6;
724 stm32x_info->default_rdp = 0xAA;
725 stm32x_info->can_load_options = true;
727 case 0x444: /* stm32f03x */
728 case 0x445: /* stm32f04x */
730 stm32x_info->ppage_size = 4;
731 max_flash_size_in_kb = 32;
732 stm32x_info->user_data_offset = 16;
733 stm32x_info->option_offset = 6;
734 stm32x_info->default_rdp = 0xAA;
735 stm32x_info->can_load_options = true;
737 case 0x448: /* stm32f07x */
739 stm32x_info->ppage_size = 4;
740 max_flash_size_in_kb = 128;
741 stm32x_info->user_data_offset = 16;
742 stm32x_info->option_offset = 6;
743 stm32x_info->default_rdp = 0xAA;
744 stm32x_info->can_load_options = true;
746 case 0x442: /* stm32f09x */
748 stm32x_info->ppage_size = 4;
749 max_flash_size_in_kb = 256;
750 stm32x_info->user_data_offset = 16;
751 stm32x_info->option_offset = 6;
752 stm32x_info->default_rdp = 0xAA;
753 stm32x_info->can_load_options = true;
755 case 0x410: /* stm32f1x medium-density */
757 stm32x_info->ppage_size = 4;
758 max_flash_size_in_kb = 128;
760 case 0x412: /* stm32f1x low-density */
762 stm32x_info->ppage_size = 4;
763 max_flash_size_in_kb = 32;
765 case 0x414: /* stm32f1x high-density */
767 stm32x_info->ppage_size = 2;
768 max_flash_size_in_kb = 512;
770 case 0x418: /* stm32f1x connectivity */
772 stm32x_info->ppage_size = 2;
773 max_flash_size_in_kb = 256;
775 case 0x430: /* stm32f1 XL-density (dual flash banks) */
777 stm32x_info->ppage_size = 2;
778 max_flash_size_in_kb = 1024;
779 stm32x_info->has_dual_banks = true;
781 case 0x420: /* stm32f100xx low- and medium-density value line */
783 stm32x_info->ppage_size = 4;
784 max_flash_size_in_kb = 128;
786 case 0x428: /* stm32f100xx high-density value line */
788 stm32x_info->ppage_size = 4;
789 max_flash_size_in_kb = 512;
791 case 0x422: /* stm32f302/3xb/c */
793 stm32x_info->ppage_size = 2;
794 max_flash_size_in_kb = 256;
795 stm32x_info->user_data_offset = 16;
796 stm32x_info->option_offset = 6;
797 stm32x_info->default_rdp = 0xAA;
798 stm32x_info->can_load_options = true;
800 case 0x446: /* stm32f303xD/E */
802 stm32x_info->ppage_size = 2;
803 max_flash_size_in_kb = 512;
804 stm32x_info->user_data_offset = 16;
805 stm32x_info->option_offset = 6;
806 stm32x_info->default_rdp = 0xAA;
807 stm32x_info->can_load_options = true;
809 case 0x432: /* stm32f37x */
811 stm32x_info->ppage_size = 2;
812 max_flash_size_in_kb = 256;
813 stm32x_info->user_data_offset = 16;
814 stm32x_info->option_offset = 6;
815 stm32x_info->default_rdp = 0xAA;
816 stm32x_info->can_load_options = true;
818 case 0x438: /* stm32f33x */
819 case 0x439: /* stm32f302x6/8 */
821 stm32x_info->ppage_size = 2;
822 max_flash_size_in_kb = 64;
823 stm32x_info->user_data_offset = 16;
824 stm32x_info->option_offset = 6;
825 stm32x_info->default_rdp = 0xAA;
826 stm32x_info->can_load_options = true;
829 LOG_WARNING("Cannot identify target as a STM32 family.");
833 /* get flash size from target. */
834 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
836 /* failed reading flash size or flash size invalid (early silicon),
837 * default to max target family */
838 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
839 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
840 max_flash_size_in_kb);
841 flash_size_in_kb = max_flash_size_in_kb;
844 if (stm32x_info->has_dual_banks) {
845 /* split reported size into matching bank */
846 if (bank->base != 0x08080000) {
847 /* bank 0 will be fixed 512k */
848 flash_size_in_kb = 512;
850 flash_size_in_kb -= 512;
851 /* bank1 also uses a register offset */
852 stm32x_info->register_base = FLASH_REG_BASE_B1;
853 base_address = 0x08080000;
857 /* if the user sets the size manually then ignore the probed value
858 * this allows us to work around devices that have a invalid flash size register value */
859 if (stm32x_info->user_bank_size) {
860 LOG_INFO("ignoring flash probed value, using configured bank size");
861 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
864 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
866 /* did we assign flash size? */
867 assert(flash_size_in_kb != 0xffff);
869 /* calculate numbers of pages */
870 int num_pages = flash_size_in_kb * 1024 / page_size;
872 /* check that calculation result makes sense */
873 assert(num_pages > 0);
877 bank->sectors = NULL;
880 if (bank->prot_blocks) {
881 free(bank->prot_blocks);
882 bank->prot_blocks = NULL;
885 bank->base = base_address;
886 bank->size = (num_pages * page_size);
888 bank->num_sectors = num_pages;
889 bank->sectors = alloc_block_array(0, page_size, num_pages);
893 /* calculate number of write protection blocks */
894 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
895 if (num_prot_blocks > 32)
896 num_prot_blocks = 32;
898 bank->num_prot_blocks = num_prot_blocks;
899 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
900 if (!bank->prot_blocks)
903 if (num_prot_blocks == 32)
904 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
906 stm32x_info->probed = true;
911 static int stm32x_auto_probe(struct flash_bank *bank)
913 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
914 if (stm32x_info->probed)
916 return stm32x_probe(bank);
920 COMMAND_HANDLER(stm32x_handle_part_id_command)
926 static const char *get_stm32f0_revision(uint16_t rev_id)
928 const char *rev_str = NULL;
941 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
943 uint32_t dbgmcu_idcode;
945 /* read stm32 device id register */
946 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
947 if (retval != ERROR_OK)
950 uint16_t device_id = dbgmcu_idcode & 0xfff;
951 uint16_t rev_id = dbgmcu_idcode >> 16;
952 const char *device_str;
953 const char *rev_str = NULL;
957 device_str = "STM32F10x (Medium Density)";
979 device_str = "STM32F10x (Low Density)";
989 device_str = "STM32F10x (High Density)";
1007 device_str = "STM32F10x (Connectivity)";
1021 device_str = "STM32F100 (Low/Medium Density)";
1035 device_str = "STM32F302xB/C";
1057 device_str = "STM32F100 (High Density)";
1071 device_str = "STM32F10x (XL Density)";
1081 device_str = "STM32F37x";
1095 device_str = "STM32F33x";
1105 device_str = "STM32F302x6/8";
1119 device_str = "STM32F03x";
1120 rev_str = get_stm32f0_revision(rev_id);
1124 device_str = "STM32F05x";
1125 rev_str = get_stm32f0_revision(rev_id);
1129 device_str = "STM32F04x";
1130 rev_str = get_stm32f0_revision(rev_id);
1134 device_str = "STM32F303xD/E";
1143 device_str = "STM32F07x";
1144 rev_str = get_stm32f0_revision(rev_id);
1148 device_str = "STM32F09x";
1149 rev_str = get_stm32f0_revision(rev_id);
1153 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1157 if (rev_str != NULL)
1158 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1160 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1165 COMMAND_HANDLER(stm32x_handle_lock_command)
1167 struct target *target = NULL;
1168 struct stm32x_flash_bank *stm32x_info = NULL;
1171 return ERROR_COMMAND_SYNTAX_ERROR;
1173 struct flash_bank *bank;
1174 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1175 if (ERROR_OK != retval)
1178 stm32x_info = bank->driver_priv;
1180 target = bank->target;
1182 if (target->state != TARGET_HALTED) {
1183 LOG_ERROR("Target not halted");
1184 return ERROR_TARGET_NOT_HALTED;
1187 retval = stm32x_check_operation_supported(bank);
1188 if (ERROR_OK != retval)
1191 if (stm32x_erase_options(bank) != ERROR_OK) {
1192 command_print(CMD, "stm32x failed to erase options");
1196 /* set readout protection */
1197 stm32x_info->option_bytes.rdp = 0;
1199 if (stm32x_write_options(bank) != ERROR_OK) {
1200 command_print(CMD, "stm32x failed to lock device");
1204 command_print(CMD, "stm32x locked");
1209 COMMAND_HANDLER(stm32x_handle_unlock_command)
1211 struct target *target = NULL;
1214 return ERROR_COMMAND_SYNTAX_ERROR;
1216 struct flash_bank *bank;
1217 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1218 if (ERROR_OK != retval)
1221 target = bank->target;
1223 if (target->state != TARGET_HALTED) {
1224 LOG_ERROR("Target not halted");
1225 return ERROR_TARGET_NOT_HALTED;
1228 retval = stm32x_check_operation_supported(bank);
1229 if (ERROR_OK != retval)
1232 if (stm32x_erase_options(bank) != ERROR_OK) {
1233 command_print(CMD, "stm32x failed to erase options");
1237 if (stm32x_write_options(bank) != ERROR_OK) {
1238 command_print(CMD, "stm32x failed to unlock device");
1242 command_print(CMD, "stm32x unlocked.\n"
1243 "INFO: a reset or power cycle is required "
1244 "for the new settings to take effect.");
1249 COMMAND_HANDLER(stm32x_handle_options_read_command)
1251 uint32_t optionbyte, protection;
1252 struct target *target = NULL;
1253 struct stm32x_flash_bank *stm32x_info = NULL;
1256 return ERROR_COMMAND_SYNTAX_ERROR;
1258 struct flash_bank *bank;
1259 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1260 if (ERROR_OK != retval)
1263 stm32x_info = bank->driver_priv;
1265 target = bank->target;
1267 if (target->state != TARGET_HALTED) {
1268 LOG_ERROR("Target not halted");
1269 return ERROR_TARGET_NOT_HALTED;
1272 retval = stm32x_check_operation_supported(bank);
1273 if (ERROR_OK != retval)
1276 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1277 if (retval != ERROR_OK)
1280 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1282 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1283 if (retval != ERROR_OK)
1286 if (optionbyte & (1 << OPT_ERROR))
1287 command_print(CMD, "option byte complement error");
1289 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1290 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1292 command_print(CMD, "read protection: %s",
1293 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1295 /* user option bytes are offset depending on variant */
1296 optionbyte >>= stm32x_info->option_offset;
1298 command_print(CMD, "watchdog: %sware",
1299 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1301 command_print(CMD, "stop mode: %sreset generated upon entry",
1302 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1304 command_print(CMD, "standby mode: %sreset generated upon entry",
1305 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1307 if (stm32x_info->has_dual_banks)
1308 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1310 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1315 COMMAND_HANDLER(stm32x_handle_options_write_command)
1317 struct target *target = NULL;
1318 struct stm32x_flash_bank *stm32x_info = NULL;
1323 return ERROR_COMMAND_SYNTAX_ERROR;
1325 struct flash_bank *bank;
1326 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1327 if (ERROR_OK != retval)
1330 stm32x_info = bank->driver_priv;
1332 target = bank->target;
1334 if (target->state != TARGET_HALTED) {
1335 LOG_ERROR("Target not halted");
1336 return ERROR_TARGET_NOT_HALTED;
1339 retval = stm32x_check_operation_supported(bank);
1340 if (ERROR_OK != retval)
1343 retval = stm32x_read_options(bank);
1344 if (ERROR_OK != retval)
1347 /* start with current options */
1348 optionbyte = stm32x_info->option_bytes.user;
1349 useropt = stm32x_info->option_bytes.data;
1351 /* skip over flash bank */
1356 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1357 optionbyte |= (1 << 0);
1358 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1359 optionbyte &= ~(1 << 0);
1360 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1361 optionbyte |= (1 << 1);
1362 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1363 optionbyte &= ~(1 << 1);
1364 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1365 optionbyte |= (1 << 2);
1366 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1367 optionbyte &= ~(1 << 2);
1368 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1370 return ERROR_COMMAND_SYNTAX_ERROR;
1371 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1374 } else if (stm32x_info->has_dual_banks) {
1375 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1376 optionbyte |= (1 << 3);
1377 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1378 optionbyte &= ~(1 << 3);
1380 return ERROR_COMMAND_SYNTAX_ERROR;
1382 return ERROR_COMMAND_SYNTAX_ERROR;
1387 if (stm32x_erase_options(bank) != ERROR_OK) {
1388 command_print(CMD, "stm32x failed to erase options");
1392 stm32x_info->option_bytes.user = optionbyte;
1393 stm32x_info->option_bytes.data = useropt;
1395 if (stm32x_write_options(bank) != ERROR_OK) {
1396 command_print(CMD, "stm32x failed to write options");
1400 command_print(CMD, "stm32x write options complete.\n"
1401 "INFO: %spower cycle is required "
1402 "for the new settings to take effect.",
1403 stm32x_info->can_load_options
1404 ? "'stm32f1x options_load' command or " : "");
1409 COMMAND_HANDLER(stm32x_handle_options_load_command)
1412 return ERROR_COMMAND_SYNTAX_ERROR;
1414 struct flash_bank *bank;
1415 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1416 if (ERROR_OK != retval)
1419 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1421 if (!stm32x_info->can_load_options) {
1422 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1423 "required instead.");
1427 struct target *target = bank->target;
1429 if (target->state != TARGET_HALTED) {
1430 LOG_ERROR("Target not halted");
1431 return ERROR_TARGET_NOT_HALTED;
1434 retval = stm32x_check_operation_supported(bank);
1435 if (ERROR_OK != retval)
1438 /* unlock option flash registers */
1439 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1440 if (retval != ERROR_OK)
1442 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1443 if (retval != ERROR_OK)
1446 /* force re-load of option bytes - generates software reset */
1447 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1448 if (retval != ERROR_OK)
1454 static int stm32x_mass_erase(struct flash_bank *bank)
1456 struct target *target = bank->target;
1458 if (target->state != TARGET_HALTED) {
1459 LOG_ERROR("Target not halted");
1460 return ERROR_TARGET_NOT_HALTED;
1463 /* unlock option flash registers */
1464 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1465 if (retval != ERROR_OK)
1467 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1468 if (retval != ERROR_OK)
1471 /* mass erase flash memory */
1472 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1473 if (retval != ERROR_OK)
1475 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1476 FLASH_MER | FLASH_STRT);
1477 if (retval != ERROR_OK)
1480 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1481 if (retval != ERROR_OK)
1484 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1485 if (retval != ERROR_OK)
1491 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1494 return ERROR_COMMAND_SYNTAX_ERROR;
1496 struct flash_bank *bank;
1497 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1498 if (ERROR_OK != retval)
1501 retval = stm32x_mass_erase(bank);
1502 if (retval == ERROR_OK) {
1503 /* set all sectors as erased */
1504 for (unsigned int i = 0; i < bank->num_sectors; i++)
1505 bank->sectors[i].is_erased = 1;
1507 command_print(CMD, "stm32x mass erase complete");
1509 command_print(CMD, "stm32x mass erase failed");
1514 static const struct command_registration stm32x_exec_command_handlers[] = {
1517 .handler = stm32x_handle_lock_command,
1518 .mode = COMMAND_EXEC,
1520 .help = "Lock entire flash device.",
1524 .handler = stm32x_handle_unlock_command,
1525 .mode = COMMAND_EXEC,
1527 .help = "Unlock entire protected flash device.",
1530 .name = "mass_erase",
1531 .handler = stm32x_handle_mass_erase_command,
1532 .mode = COMMAND_EXEC,
1534 .help = "Erase entire flash device.",
1537 .name = "options_read",
1538 .handler = stm32x_handle_options_read_command,
1539 .mode = COMMAND_EXEC,
1541 .help = "Read and display device option bytes.",
1544 .name = "options_write",
1545 .handler = stm32x_handle_options_write_command,
1546 .mode = COMMAND_EXEC,
1547 .usage = "bank_id ('SWWDG'|'HWWDG') "
1548 "('RSTSTNDBY'|'NORSTSTNDBY') "
1549 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1550 .help = "Replace bits in device option bytes.",
1553 .name = "options_load",
1554 .handler = stm32x_handle_options_load_command,
1555 .mode = COMMAND_EXEC,
1557 .help = "Force re-load of device option bytes.",
1559 COMMAND_REGISTRATION_DONE
1562 static const struct command_registration stm32x_command_handlers[] = {
1565 .mode = COMMAND_ANY,
1566 .help = "stm32f1x flash command group",
1568 .chain = stm32x_exec_command_handlers,
1570 COMMAND_REGISTRATION_DONE
1573 const struct flash_driver stm32f1x_flash = {
1575 .commands = stm32x_command_handlers,
1576 .flash_bank_command = stm32x_flash_bank_command,
1577 .erase = stm32x_erase,
1578 .protect = stm32x_protect,
1579 .write = stm32x_write,
1580 .read = default_flash_read,
1581 .probe = stm32x_probe,
1582 .auto_probe = stm32x_auto_probe,
1583 .erase_check = default_flash_blank_check,
1584 .protect_check = stm32x_protect_check,
1585 .info = get_stm32x_info,
1586 .free_driver_priv = default_flash_free_driver_priv,