git.gag.com Git - fw/openocd/blob - src/flash/nor/stm32f1x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "imp.h"
  30 #include <helper/binarybuffer.h>
  31 #include <target/algorithm.h>
  32 #include <target/armv7m.h>
  33
  34 /* stm32x register locations */
  35
  36 #define FLASH_REG_BASE_B0 0x40022000
  37 #define FLASH_REG_BASE_B1 0x40022040
  38
  39 #define STM32_FLASH_ACR     0x00
  40 #define STM32_FLASH_KEYR    0x04
  41 #define STM32_FLASH_OPTKEYR 0x08
  42 #define STM32_FLASH_SR      0x0C
  43 #define STM32_FLASH_CR      0x10
  44 #define STM32_FLASH_AR      0x14
  45 #define STM32_FLASH_OBR     0x1C
  46 #define STM32_FLASH_WRPR    0x20
  47
  48 /* TODO: Check if code using these really should be hard coded to bank 0.
  49  * There are valid cases, on dual flash devices the protection of the
  50  * second bank is done on the bank0 reg's. */
  51 #define STM32_FLASH_ACR_B0     0x40022000
  52 #define STM32_FLASH_KEYR_B0    0x40022004
  53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  54 #define STM32_FLASH_SR_B0      0x4002200C
  55 #define STM32_FLASH_CR_B0      0x40022010
  56 #define STM32_FLASH_AR_B0      0x40022014
  57 #define STM32_FLASH_OBR_B0     0x4002201C
  58 #define STM32_FLASH_WRPR_B0    0x40022020
  59
  60 /* option byte location */
  61
  62 #define STM32_OB_RDP            0x1FFFF800
  63 #define STM32_OB_USER           0x1FFFF802
  64 #define STM32_OB_DATA0          0x1FFFF804
  65 #define STM32_OB_DATA1          0x1FFFF806
  66 #define STM32_OB_WRP0           0x1FFFF808
  67 #define STM32_OB_WRP1           0x1FFFF80A
  68 #define STM32_OB_WRP2           0x1FFFF80C
  69 #define STM32_OB_WRP3           0x1FFFF80E
  70
  71 /* FLASH_CR register bits */
  72
  73 #define FLASH_PG                        (1 << 0)
  74 #define FLASH_PER                       (1 << 1)
  75 #define FLASH_MER                       (1 << 2)
  76 #define FLASH_OPTPG                     (1 << 4)
  77 #define FLASH_OPTER                     (1 << 5)
  78 #define FLASH_STRT                      (1 << 6)
  79 #define FLASH_LOCK                      (1 << 7)
  80 #define FLASH_OPTWRE            (1 << 9)
  81 #define FLASH_OBL_LAUNCH        (1 << 13)       /* except stm32f1x series */
  82
  83 /* FLASH_SR register bits */
  84
  85 #define FLASH_BSY               (1 << 0)
  86 #define FLASH_PGERR             (1 << 2)
  87 #define FLASH_WRPRTERR  (1 << 4)
  88 #define FLASH_EOP               (1 << 5)
  89
  90 /* STM32_FLASH_OBR bit definitions (reading) */
  91
  92 #define OPT_ERROR               0
  93 #define OPT_READOUT             1
  94 #define OPT_RDWDGSW             2
  95 #define OPT_RDRSTSTOP   3
  96 #define OPT_RDRSTSTDBY  4
  97 #define OPT_BFB2                5       /* dual flash bank only */
  98
  99 /* register unlock keys */
 100
 101 #define KEY1                    0x45670123
 102 #define KEY2                    0xCDEF89AB
 103
 104 /* timeout values */
 105
 106 #define FLASH_WRITE_TIMEOUT 10
 107 #define FLASH_ERASE_TIMEOUT 100
 108
 109 struct stm32x_options {
 110         uint8_t rdp;
 111         uint8_t user;
 112         uint16_t data;
 113         uint32_t protection;
 114 };
 115
 116 struct stm32x_flash_bank {
 117         struct stm32x_options option_bytes;
 118         int ppage_size;
 119         bool probed;
 120
 121         bool has_dual_banks;
 122         /* used to access dual flash bank stm32xl */
 123         bool can_load_options;
 124         uint32_t register_base;
 125         uint8_t default_rdp;
 126         int user_data_offset;
 127         int option_offset;
 128         uint32_t user_bank_size;
 129 };
 130
 131 static int stm32x_mass_erase(struct flash_bank *bank);
 132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
 133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 134                 uint32_t address, uint32_t count);
 135
 136 /* flash bank stm32x <base> <size> 0 0 <target#>
 137  */
 138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 139 {
 140         struct stm32x_flash_bank *stm32x_info;
 141
 142         if (CMD_ARGC < 6)
 143                 return ERROR_COMMAND_SYNTAX_ERROR;
 144
 145         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 146
 147         bank->driver_priv = stm32x_info;
 148         stm32x_info->probed = false;
 149         stm32x_info->has_dual_banks = false;
 150         stm32x_info->can_load_options = false;
 151         stm32x_info->register_base = FLASH_REG_BASE_B0;
 152         stm32x_info->user_bank_size = bank->size;
 153
 154         return ERROR_OK;
 155 }
 156
 157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 158 {
 159         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 160         return reg + stm32x_info->register_base;
 161 }
 162
 163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 164 {
 165         struct target *target = bank->target;
 166         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 167 }
 168
 169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 170 {
 171         struct target *target = bank->target;
 172         uint32_t status;
 173         int retval = ERROR_OK;
 174
 175         /* wait for busy to clear */
 176         for (;;) {
 177                 retval = stm32x_get_flash_status(bank, &status);
 178                 if (retval != ERROR_OK)
 179                         return retval;
 180                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 181                 if ((status & FLASH_BSY) == 0)
 182                         break;
 183                 if (timeout-- <= 0) {
 184                         LOG_ERROR("timed out waiting for flash");
 185                         return ERROR_FAIL;
 186                 }
 187                 alive_sleep(1);
 188         }
 189
 190         if (status & FLASH_WRPRTERR) {
 191                 LOG_ERROR("stm32x device protected");
 192                 retval = ERROR_FAIL;
 193         }
 194
 195         if (status & FLASH_PGERR) {
 196                 LOG_ERROR("stm32x device programming failed");
 197                 retval = ERROR_FAIL;
 198         }
 199
 200         /* Clear but report errors */
 201         if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
 202                 /* If this operation fails, we ignore it and report the original
 203                  * retval
 204                  */
 205                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 206                                 FLASH_WRPRTERR | FLASH_PGERR);
 207         }
 208         return retval;
 209 }
 210
 211 static int stm32x_check_operation_supported(struct flash_bank *bank)
 212 {
 213         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 214
 215         /* if we have a dual flash bank device then
 216          * we need to perform option byte stuff on bank0 only */
 217         if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
 218                 LOG_ERROR("Option byte operations must use bank 0");
 219                 return ERROR_FLASH_OPERATION_FAILED;
 220         }
 221
 222         return ERROR_OK;
 223 }
 224
 225 static int stm32x_read_options(struct flash_bank *bank)
 226 {
 227         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 228         struct target *target = bank->target;
 229         uint32_t option_bytes;
 230         int retval;
 231
 232         /* read user and read protection option bytes, user data option bytes */
 233         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
 234         if (retval != ERROR_OK)
 235                 return retval;
 236
 237         stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
 238         stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
 239         stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
 240
 241         /* read write protection option bytes */
 242         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
 243         if (retval != ERROR_OK)
 244                 return retval;
 245
 246         return ERROR_OK;
 247 }
 248
 249 static int stm32x_erase_options(struct flash_bank *bank)
 250 {
 251         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 252         struct target *target = bank->target;
 253
 254         /* read current options */
 255         stm32x_read_options(bank);
 256
 257         /* unlock flash registers */
 258         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 259         if (retval != ERROR_OK)
 260                 return retval;
 261
 262         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 263         if (retval != ERROR_OK)
 264                 return retval;
 265
 266         /* unlock option flash registers */
 267         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 268         if (retval != ERROR_OK)
 269                 return retval;
 270         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 271         if (retval != ERROR_OK)
 272                 return retval;
 273
 274         /* erase option bytes */
 275         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 276         if (retval != ERROR_OK)
 277                 return retval;
 278         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 279         if (retval != ERROR_OK)
 280                 return retval;
 281
 282         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 283         if (retval != ERROR_OK)
 284                 return retval;
 285
 286         /* clear read protection option byte
 287          * this will also force a device unlock if set */
 288         stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
 289
 290         return ERROR_OK;
 291 }
 292
 293 static int stm32x_write_options(struct flash_bank *bank)
 294 {
 295         struct stm32x_flash_bank *stm32x_info = NULL;
 296         struct target *target = bank->target;
 297
 298         stm32x_info = bank->driver_priv;
 299
 300         /* unlock flash registers */
 301         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 302         if (retval != ERROR_OK)
 303                 return retval;
 304         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 305         if (retval != ERROR_OK)
 306                 return retval;
 307
 308         /* unlock option flash registers */
 309         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 310         if (retval != ERROR_OK)
 311                 return retval;
 312         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 313         if (retval != ERROR_OK)
 314                 return retval;
 315
 316         /* program option bytes */
 317         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 318         if (retval != ERROR_OK)
 319                 return retval;
 320
 321         uint8_t opt_bytes[16];
 322
 323         target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
 324         target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
 325         target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
 326         target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
 327         target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
 328         target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
 329         target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
 330         target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
 331
 332         retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
 333         if (retval != ERROR_OK) {
 334                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 335                         LOG_ERROR("working area required to erase options bytes");
 336                 return retval;
 337         }
 338
 339         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 340         if (retval != ERROR_OK)
 341                 return retval;
 342
 343         return ERROR_OK;
 344 }
 345
 346 static int stm32x_protect_check(struct flash_bank *bank)
 347 {
 348         struct target *target = bank->target;
 349         uint32_t protection;
 350
 351         int retval = stm32x_check_operation_supported(bank);
 352         if (ERROR_OK != retval)
 353                 return retval;
 354
 355         /* medium density - each bit refers to a 4 sector protection block
 356          * high density - each bit refers to a 2 sector protection block
 357          * bit 31 refers to all remaining sectors in a bank */
 358         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 359         if (retval != ERROR_OK)
 360                 return retval;
 361
 362         for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
 363                 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
 364
 365         return ERROR_OK;
 366 }
 367
 368 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
 369                 unsigned int last)
 370 {
 371         struct target *target = bank->target;
 372
 373         if (bank->target->state != TARGET_HALTED) {
 374                 LOG_ERROR("Target not halted");
 375                 return ERROR_TARGET_NOT_HALTED;
 376         }
 377
 378         if ((first == 0) && (last == (bank->num_sectors - 1)))
 379                 return stm32x_mass_erase(bank);
 380
 381         /* unlock flash registers */
 382         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 383         if (retval != ERROR_OK)
 384                 return retval;
 385         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 386         if (retval != ERROR_OK)
 387                 return retval;
 388
 389         for (unsigned int i = first; i <= last; i++) {
 390                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 391                 if (retval != ERROR_OK)
 392                         return retval;
 393                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 394                                 bank->base + bank->sectors[i].offset);
 395                 if (retval != ERROR_OK)
 396                         return retval;
 397                 retval = target_write_u32(target,
 398                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 399                 if (retval != ERROR_OK)
 400                         return retval;
 401
 402                 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 403                 if (retval != ERROR_OK)
 404                         return retval;
 405
 406                 bank->sectors[i].is_erased = 1;
 407         }
 408
 409         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 410         if (retval != ERROR_OK)
 411                 return retval;
 412
 413         return ERROR_OK;
 414 }
 415
 416 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 417                 unsigned int last)
 418 {
 419         struct target *target = bank->target;
 420         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 421
 422         if (target->state != TARGET_HALTED) {
 423                 LOG_ERROR("Target not halted");
 424                 return ERROR_TARGET_NOT_HALTED;
 425         }
 426
 427         int retval = stm32x_check_operation_supported(bank);
 428         if (retval != ERROR_OK)
 429                 return retval;
 430
 431         retval = stm32x_erase_options(bank);
 432         if (retval != ERROR_OK) {
 433                 LOG_ERROR("stm32x failed to erase options");
 434                 return retval;
 435         }
 436
 437         for (unsigned int i = first; i <= last; i++) {
 438                 if (set)
 439                         stm32x_info->option_bytes.protection &= ~(1 << i);
 440                 else
 441                         stm32x_info->option_bytes.protection |= (1 << i);
 442         }
 443
 444         return stm32x_write_options(bank);
 445 }
 446
 447 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 448                 uint32_t address, uint32_t count)
 449 {
 450         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 451         struct target *target = bank->target;
 452         uint32_t buffer_size = 16384;
 453         struct working_area *write_algorithm;
 454         struct working_area *source;
 455         struct reg_param reg_params[5];
 456         struct armv7m_algorithm armv7m_info;
 457         int retval = ERROR_OK;
 458
 459         static const uint8_t stm32x_flash_write_code[] = {
 460 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
 461         };
 462
 463         /* flash write code */
 464         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 465                         &write_algorithm) != ERROR_OK) {
 466                 LOG_WARNING("no working area available, can't do block memory writes");
 467                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 468         }
 469
 470         retval = target_write_buffer(target, write_algorithm->address,
 471                         sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
 472         if (retval != ERROR_OK) {
 473                 target_free_working_area(target, write_algorithm);
 474                 return retval;
 475         }
 476
 477         /* memory buffer */
 478         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 479                 buffer_size /= 2;
 480                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 481                 if (buffer_size <= 256) {
 482                         /* we already allocated the writing code, but failed to get a
 483                          * buffer, free the algorithm */
 484                         target_free_working_area(target, write_algorithm);
 485
 486                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 487                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 488                 }
 489         }
 490
 491         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 492         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 493         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 494         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 495         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 496
 497         buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
 498         buf_set_u32(reg_params[1].value, 0, 32, count);
 499         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 500         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 501         buf_set_u32(reg_params[4].value, 0, 32, address);
 502
 503         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 504         armv7m_info.core_mode = ARM_MODE_THREAD;
 505
 506         retval = target_run_flash_async_algorithm(target, buffer, count, 2,
 507                         0, NULL,
 508                         5, reg_params,
 509                         source->address, source->size,
 510                         write_algorithm->address, 0,
 511                         &armv7m_info);
 512
 513         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 514                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 515                                 buf_get_u32(reg_params[4].value, 0, 32));
 516
 517                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
 518                         LOG_ERROR("flash memory not erased before writing");
 519                         /* Clear but report errors */
 520                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
 521                 }
 522
 523                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
 524                         LOG_ERROR("flash memory write protected");
 525                         /* Clear but report errors */
 526                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
 527                 }
 528         }
 529
 530         target_free_working_area(target, source);
 531         target_free_working_area(target, write_algorithm);
 532
 533         destroy_reg_param(&reg_params[0]);
 534         destroy_reg_param(&reg_params[1]);
 535         destroy_reg_param(&reg_params[2]);
 536         destroy_reg_param(&reg_params[3]);
 537         destroy_reg_param(&reg_params[4]);
 538
 539         return retval;
 540 }
 541
 542 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 543                 uint32_t offset, uint32_t count)
 544 {
 545         struct target *target = bank->target;
 546         uint8_t *new_buffer = NULL;
 547
 548         if (bank->target->state != TARGET_HALTED) {
 549                 LOG_ERROR("Target not halted");
 550                 return ERROR_TARGET_NOT_HALTED;
 551         }
 552
 553         if (offset & 0x1) {
 554                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 555                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 556         }
 557
 558         /* If there's an odd number of bytes, the data has to be padded. Duplicate
 559          * the buffer and use the normal code path with a single block write since
 560          * it's probably cheaper than to special case the last odd write using
 561          * discrete accesses. */
 562         if (count & 1) {
 563                 new_buffer = malloc(count + 1);
 564                 if (new_buffer == NULL) {
 565                         LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
 566                         return ERROR_FAIL;
 567                 }
 568                 LOG_INFO("odd number of bytes to write, padding with 0xff");
 569                 buffer = memcpy(new_buffer, buffer, count);
 570                 new_buffer[count++] = 0xff;
 571         }
 572
 573         uint32_t words_remaining = count / 2;
 574         int retval, retval2;
 575
 576         /* unlock flash registers */
 577         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 578         if (retval != ERROR_OK)
 579                 goto cleanup;
 580         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 581         if (retval != ERROR_OK)
 582                 goto cleanup;
 583
 584         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 585         if (retval != ERROR_OK)
 586                 goto cleanup;
 587
 588         /* try using a block write */
 589         retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
 590
 591         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 592                 /* if block write failed (no sufficient working area),
 593                  * we use normal (slow) single halfword accesses */
 594                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 595
 596                 while (words_remaining > 0) {
 597                         uint16_t value;
 598                         memcpy(&value, buffer, sizeof(uint16_t));
 599
 600                         retval = target_write_u16(target, bank->base + offset, value);
 601                         if (retval != ERROR_OK)
 602                                 goto reset_pg_and_lock;
 603
 604                         retval = stm32x_wait_status_busy(bank, 5);
 605                         if (retval != ERROR_OK)
 606                                 goto reset_pg_and_lock;
 607
 608                         words_remaining--;
 609                         buffer += 2;
 610                         offset += 2;
 611                 }
 612         }
 613
 614 reset_pg_and_lock:
 615         retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 616         if (retval == ERROR_OK)
 617                 retval = retval2;
 618
 619 cleanup:
 620         free(new_buffer);
 621         return retval;
 622 }
 623
 624 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 625 {
 626         /* This check the device CPUID core register to detect
 627          * the M0 from the M3 devices. */
 628
 629         struct target *target = bank->target;
 630         uint32_t cpuid, device_id_register = 0;
 631
 632         /* Get the CPUID from the ARM Core
 633          * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
 634         int retval = target_read_u32(target, 0xE000ED00, &cpuid);
 635         if (retval != ERROR_OK)
 636                 return retval;
 637
 638         if (((cpuid >> 4) & 0xFFF) == 0xC20) {
 639                 /* 0xC20 is M0 devices */
 640                 device_id_register = 0x40015800;
 641         } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
 642                 /* 0xC23 is M3 devices */
 643                 device_id_register = 0xE0042000;
 644         } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
 645                 /* 0xC24 is M4 devices */
 646                 device_id_register = 0xE0042000;
 647         } else {
 648                 LOG_ERROR("Cannot identify target as a stm32x");
 649                 return ERROR_FAIL;
 650         }
 651
 652         /* read stm32 device id register */
 653         retval = target_read_u32(target, device_id_register, device_id);
 654         if (retval != ERROR_OK)
 655                 return retval;
 656
 657         return retval;
 658 }
 659
 660 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
 661 {
 662         struct target *target = bank->target;
 663         uint32_t cpuid, flash_size_reg;
 664
 665         int retval = target_read_u32(target, 0xE000ED00, &cpuid);
 666         if (retval != ERROR_OK)
 667                 return retval;
 668
 669         if (((cpuid >> 4) & 0xFFF) == 0xC20) {
 670                 /* 0xC20 is M0 devices */
 671                 flash_size_reg = 0x1FFFF7CC;
 672         } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
 673                 /* 0xC23 is M3 devices */
 674                 flash_size_reg = 0x1FFFF7E0;
 675         } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
 676                 /* 0xC24 is M4 devices */
 677                 flash_size_reg = 0x1FFFF7CC;
 678         } else {
 679                 LOG_ERROR("Cannot identify target as a stm32x");
 680                 return ERROR_FAIL;
 681         }
 682
 683         retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
 684         if (retval != ERROR_OK)
 685                 return retval;
 686
 687         return retval;
 688 }
 689
 690 static int stm32x_probe(struct flash_bank *bank)
 691 {
 692         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 693         uint16_t flash_size_in_kb;
 694         uint16_t max_flash_size_in_kb;
 695         uint32_t dbgmcu_idcode;
 696         int page_size;
 697         uint32_t base_address = 0x08000000;
 698
 699         stm32x_info->probed = false;
 700         stm32x_info->register_base = FLASH_REG_BASE_B0;
 701         stm32x_info->user_data_offset = 10;
 702         stm32x_info->option_offset = 0;
 703
 704         /* default factory read protection level 0 */
 705         stm32x_info->default_rdp = 0xA5;
 706
 707         /* read stm32 device id register */
 708         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 709         if (retval != ERROR_OK)
 710                 return retval;
 711
 712         LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
 713
 714         uint16_t device_id = dbgmcu_idcode & 0xfff;
 715         uint16_t rev_id = dbgmcu_idcode >> 16;
 716
 717         /* set page size, protection granularity and max flash size depending on family */
 718         switch (device_id) {
 719         case 0x440: /* stm32f05x */
 720                 page_size = 1024;
 721                 stm32x_info->ppage_size = 4;
 722                 max_flash_size_in_kb = 64;
 723                 stm32x_info->user_data_offset = 16;
 724                 stm32x_info->option_offset = 6;
 725                 stm32x_info->default_rdp = 0xAA;
 726                 stm32x_info->can_load_options = true;
 727                 break;
 728         case 0x444: /* stm32f03x */
 729         case 0x445: /* stm32f04x */
 730                 page_size = 1024;
 731                 stm32x_info->ppage_size = 4;
 732                 max_flash_size_in_kb = 32;
 733                 stm32x_info->user_data_offset = 16;
 734                 stm32x_info->option_offset = 6;
 735                 stm32x_info->default_rdp = 0xAA;
 736                 stm32x_info->can_load_options = true;
 737                 break;
 738         case 0x448: /* stm32f07x */
 739                 page_size = 2048;
 740                 stm32x_info->ppage_size = 4;
 741                 max_flash_size_in_kb = 128;
 742                 stm32x_info->user_data_offset = 16;
 743                 stm32x_info->option_offset = 6;
 744                 stm32x_info->default_rdp = 0xAA;
 745                 stm32x_info->can_load_options = true;
 746                 break;
 747         case 0x442: /* stm32f09x */
 748                 page_size = 2048;
 749                 stm32x_info->ppage_size = 4;
 750                 max_flash_size_in_kb = 256;
 751                 stm32x_info->user_data_offset = 16;
 752                 stm32x_info->option_offset = 6;
 753                 stm32x_info->default_rdp = 0xAA;
 754                 stm32x_info->can_load_options = true;
 755                 break;
 756         case 0x410: /* stm32f1x medium-density */
 757                 page_size = 1024;
 758                 stm32x_info->ppage_size = 4;
 759                 max_flash_size_in_kb = 128;
 760                 /* GigaDevice GD32F1x0 & GD32F3x0 series devices share DEV_ID
 761                    with STM32F101/2/3 medium-density line,
 762                    however they use a REV_ID different from any STM32 device.
 763                    The main difference is another offset of user option bits
 764                    (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
 765                    (FLASH_OBR/FMC_OBSTAT 0x4002201C).
 766                    This caused problems e.g. during flash block programming
 767                    because of unexpected active hardware watchog. */
 768                 switch (rev_id) {
 769                 case 0x1303: /* gd32f1x0 */
 770                         stm32x_info->user_data_offset = 16;
 771                         stm32x_info->option_offset = 6;
 772                         max_flash_size_in_kb = 64;
 773                         break;
 774                 case 0x1704: /* gd32f3x0 */
 775                         stm32x_info->user_data_offset = 16;
 776                         stm32x_info->option_offset = 6;
 777                         break;
 778                 }
 779                 break;
 780         case 0x412: /* stm32f1x low-density */
 781                 page_size = 1024;
 782                 stm32x_info->ppage_size = 4;
 783                 max_flash_size_in_kb = 32;
 784                 break;
 785         case 0x414: /* stm32f1x high-density */
 786                 page_size = 2048;
 787                 stm32x_info->ppage_size = 2;
 788                 max_flash_size_in_kb = 512;
 789                 break;
 790         case 0x418: /* stm32f1x connectivity */
 791                 page_size = 2048;
 792                 stm32x_info->ppage_size = 2;
 793                 max_flash_size_in_kb = 256;
 794                 break;
 795         case 0x430: /* stm32f1 XL-density (dual flash banks) */
 796                 page_size = 2048;
 797                 stm32x_info->ppage_size = 2;
 798                 max_flash_size_in_kb = 1024;
 799                 stm32x_info->has_dual_banks = true;
 800                 break;
 801         case 0x420: /* stm32f100xx low- and medium-density value line */
 802                 page_size = 1024;
 803                 stm32x_info->ppage_size = 4;
 804                 max_flash_size_in_kb = 128;
 805                 break;
 806         case 0x428: /* stm32f100xx high-density value line */
 807                 page_size = 2048;
 808                 stm32x_info->ppage_size = 4;
 809                 max_flash_size_in_kb = 512;
 810                 break;
 811         case 0x422: /* stm32f302/3xb/c */
 812                 page_size = 2048;
 813                 stm32x_info->ppage_size = 2;
 814                 max_flash_size_in_kb = 256;
 815                 stm32x_info->user_data_offset = 16;
 816                 stm32x_info->option_offset = 6;
 817                 stm32x_info->default_rdp = 0xAA;
 818                 stm32x_info->can_load_options = true;
 819                 break;
 820         case 0x446: /* stm32f303xD/E */
 821                 page_size = 2048;
 822                 stm32x_info->ppage_size = 2;
 823                 max_flash_size_in_kb = 512;
 824                 stm32x_info->user_data_offset = 16;
 825                 stm32x_info->option_offset = 6;
 826                 stm32x_info->default_rdp = 0xAA;
 827                 stm32x_info->can_load_options = true;
 828                 break;
 829         case 0x432: /* stm32f37x */
 830                 page_size = 2048;
 831                 stm32x_info->ppage_size = 2;
 832                 max_flash_size_in_kb = 256;
 833                 stm32x_info->user_data_offset = 16;
 834                 stm32x_info->option_offset = 6;
 835                 stm32x_info->default_rdp = 0xAA;
 836                 stm32x_info->can_load_options = true;
 837                 break;
 838         case 0x438: /* stm32f33x */
 839         case 0x439: /* stm32f302x6/8 */
 840                 page_size = 2048;
 841                 stm32x_info->ppage_size = 2;
 842                 max_flash_size_in_kb = 64;
 843                 stm32x_info->user_data_offset = 16;
 844                 stm32x_info->option_offset = 6;
 845                 stm32x_info->default_rdp = 0xAA;
 846                 stm32x_info->can_load_options = true;
 847                 break;
 848         default:
 849                 LOG_WARNING("Cannot identify target as a STM32 family.");
 850                 return ERROR_FAIL;
 851         }
 852
 853         /* get flash size from target. */
 854         retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
 855
 856         /* failed reading flash size or flash size invalid (early silicon),
 857          * default to max target family */
 858         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 859                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 860                         max_flash_size_in_kb);
 861                 flash_size_in_kb = max_flash_size_in_kb;
 862         }
 863
 864         if (stm32x_info->has_dual_banks) {
 865                 /* split reported size into matching bank */
 866                 if (bank->base != 0x08080000) {
 867                         /* bank 0 will be fixed 512k */
 868                         flash_size_in_kb = 512;
 869                 } else {
 870                         flash_size_in_kb -= 512;
 871                         /* bank1 also uses a register offset */
 872                         stm32x_info->register_base = FLASH_REG_BASE_B1;
 873                         base_address = 0x08080000;
 874                 }
 875         }
 876
 877         /* if the user sets the size manually then ignore the probed value
 878          * this allows us to work around devices that have a invalid flash size register value */
 879         if (stm32x_info->user_bank_size) {
 880                 LOG_INFO("ignoring flash probed value, using configured bank size");
 881                 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
 882         }
 883
 884         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 885
 886         /* did we assign flash size? */
 887         assert(flash_size_in_kb != 0xffff);
 888
 889         /* calculate numbers of pages */
 890         int num_pages = flash_size_in_kb * 1024 / page_size;
 891
 892         /* check that calculation result makes sense */
 893         assert(num_pages > 0);
 894
 895         free(bank->sectors);
 896         bank->sectors = NULL;
 897
 898         free(bank->prot_blocks);
 899         bank->prot_blocks = NULL;
 900
 901         bank->base = base_address;
 902         bank->size = (num_pages * page_size);
 903
 904         bank->num_sectors = num_pages;
 905         bank->sectors = alloc_block_array(0, page_size, num_pages);
 906         if (!bank->sectors)
 907                 return ERROR_FAIL;
 908
 909         /* calculate number of write protection blocks */
 910         int num_prot_blocks = num_pages / stm32x_info->ppage_size;
 911         if (num_prot_blocks > 32)
 912                 num_prot_blocks = 32;
 913
 914         bank->num_prot_blocks = num_prot_blocks;
 915         bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
 916         if (!bank->prot_blocks)
 917                 return ERROR_FAIL;
 918
 919         if (num_prot_blocks == 32)
 920                 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
 921
 922         stm32x_info->probed = true;
 923
 924         return ERROR_OK;
 925 }
 926
 927 static int stm32x_auto_probe(struct flash_bank *bank)
 928 {
 929         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 930         if (stm32x_info->probed)
 931                 return ERROR_OK;
 932         return stm32x_probe(bank);
 933 }
 934
 935 #if 0
 936 COMMAND_HANDLER(stm32x_handle_part_id_command)
 937 {
 938         return ERROR_OK;
 939 }
 940 #endif
 941
 942 static const char *get_stm32f0_revision(uint16_t rev_id)
 943 {
 944         const char *rev_str = NULL;
 945
 946         switch (rev_id) {
 947         case 0x1000:
 948                 rev_str = "1.0";
 949                 break;
 950         case 0x2000:
 951                 rev_str = "2.0";
 952                 break;
 953         }
 954         return rev_str;
 955 }
 956
 957 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
 958 {
 959         uint32_t dbgmcu_idcode;
 960
 961         /* read stm32 device id register */
 962         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 963         if (retval != ERROR_OK)
 964                 return retval;
 965
 966         uint16_t device_id = dbgmcu_idcode & 0xfff;
 967         uint16_t rev_id = dbgmcu_idcode >> 16;
 968         const char *device_str;
 969         const char *rev_str = NULL;
 970
 971         switch (device_id) {
 972         case 0x410:
 973                 device_str = "STM32F10x (Medium Density)";
 974
 975                 switch (rev_id) {
 976                 case 0x0000:
 977                         rev_str = "A";
 978                         break;
 979
 980                 case 0x1303: /* gd32f1x0 */
 981                         device_str = "GD32F1x0";
 982                         break;
 983
 984                 case 0x1704: /* gd32f3x0 */
 985                         device_str = "GD32F3x0";
 986                         break;
 987
 988                 case 0x2000:
 989                         rev_str = "B";
 990                         break;
 991
 992                 case 0x2001:
 993                         rev_str = "Z";
 994                         break;
 995
 996                 case 0x2003:
 997                         rev_str = "Y";
 998                         break;
 999                 }
1000                 break;
1001
1002         case 0x412:
1003                 device_str = "STM32F10x (Low Density)";
1004
1005                 switch (rev_id) {
1006                 case 0x1000:
1007                         rev_str = "A";
1008                         break;
1009                 }
1010                 break;
1011
1012         case 0x414:
1013                 device_str = "STM32F10x (High Density)";
1014
1015                 switch (rev_id) {
1016                 case 0x1000:
1017                         rev_str = "A";
1018                         break;
1019
1020                 case 0x1001:
1021                         rev_str = "Z";
1022                         break;
1023
1024                 case 0x1003:
1025                         rev_str = "Y";
1026                         break;
1027                 }
1028                 break;
1029
1030         case 0x418:
1031                 device_str = "STM32F10x (Connectivity)";
1032
1033                 switch (rev_id) {
1034                 case 0x1000:
1035                         rev_str = "A";
1036                         break;
1037
1038                 case 0x1001:
1039                         rev_str = "Z";
1040                         break;
1041                 }
1042                 break;
1043
1044         case 0x420:
1045                 device_str = "STM32F100 (Low/Medium Density)";
1046
1047                 switch (rev_id) {
1048                 case 0x1000:
1049                         rev_str = "A";
1050                         break;
1051
1052                 case 0x1001:
1053                         rev_str = "Z";
1054                         break;
1055                 }
1056                 break;
1057
1058         case 0x422:
1059                 device_str = "STM32F302xB/C";
1060
1061                 switch (rev_id) {
1062                 case 0x1000:
1063                         rev_str = "A";
1064                         break;
1065
1066                 case 0x1001:
1067                         rev_str = "Z";
1068                         break;
1069
1070                 case 0x1003:
1071                         rev_str = "Y";
1072                         break;
1073
1074                 case 0x2000:
1075                         rev_str = "B";
1076                         break;
1077                 }
1078                 break;
1079
1080         case 0x428:
1081                 device_str = "STM32F100 (High Density)";
1082
1083                 switch (rev_id) {
1084                 case 0x1000:
1085                         rev_str = "A";
1086                         break;
1087
1088                 case 0x1001:
1089                         rev_str = "Z";
1090                         break;
1091                 }
1092                 break;
1093
1094         case 0x430:
1095                 device_str = "STM32F10x (XL Density)";
1096
1097                 switch (rev_id) {
1098                 case 0x1000:
1099                         rev_str = "A";
1100                         break;
1101                 }
1102                 break;
1103
1104         case 0x432:
1105                 device_str = "STM32F37x";
1106
1107                 switch (rev_id) {
1108                 case 0x1000:
1109                         rev_str = "A";
1110                         break;
1111
1112                 case 0x2000:
1113                         rev_str = "B";
1114                         break;
1115                 }
1116                 break;
1117
1118         case 0x438:
1119                 device_str = "STM32F33x";
1120
1121                 switch (rev_id) {
1122                 case 0x1000:
1123                         rev_str = "A";
1124                         break;
1125                 }
1126                 break;
1127
1128         case 0x439:
1129                 device_str = "STM32F302x6/8";
1130
1131                 switch (rev_id) {
1132                 case 0x1000:
1133                         rev_str = "A";
1134                         break;
1135
1136                 case 0x1001:
1137                         rev_str = "Z";
1138                         break;
1139                 }
1140                 break;
1141
1142         case 0x444:
1143                 device_str = "STM32F03x";
1144                 rev_str = get_stm32f0_revision(rev_id);
1145                 break;
1146
1147         case 0x440:
1148                 device_str = "STM32F05x";
1149                 rev_str = get_stm32f0_revision(rev_id);
1150                 break;
1151
1152         case 0x445:
1153                 device_str = "STM32F04x";
1154                 rev_str = get_stm32f0_revision(rev_id);
1155                 break;
1156
1157         case 0x446:
1158                 device_str = "STM32F303xD/E";
1159                 switch (rev_id) {
1160                 case 0x1000:
1161                         rev_str = "A";
1162                         break;
1163                 }
1164                 break;
1165
1166         case 0x448:
1167                 device_str = "STM32F07x";
1168                 rev_str = get_stm32f0_revision(rev_id);
1169                 break;
1170
1171         case 0x442:
1172                 device_str = "STM32F09x";
1173                 rev_str = get_stm32f0_revision(rev_id);
1174                 break;
1175
1176         default:
1177                 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1178                 return ERROR_FAIL;
1179         }
1180
1181         if (rev_str != NULL)
1182                 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1183         else
1184                 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1185
1186         return ERROR_OK;
1187 }
1188
1189 COMMAND_HANDLER(stm32x_handle_lock_command)
1190 {
1191         struct target *target = NULL;
1192         struct stm32x_flash_bank *stm32x_info = NULL;
1193
1194         if (CMD_ARGC < 1)
1195                 return ERROR_COMMAND_SYNTAX_ERROR;
1196
1197         struct flash_bank *bank;
1198         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1199         if (ERROR_OK != retval)
1200                 return retval;
1201
1202         stm32x_info = bank->driver_priv;
1203
1204         target = bank->target;
1205
1206         if (target->state != TARGET_HALTED) {
1207                 LOG_ERROR("Target not halted");
1208                 return ERROR_TARGET_NOT_HALTED;
1209         }
1210
1211         retval = stm32x_check_operation_supported(bank);
1212         if (ERROR_OK != retval)
1213                 return retval;
1214
1215         if (stm32x_erase_options(bank) != ERROR_OK) {
1216                 command_print(CMD, "stm32x failed to erase options");
1217                 return ERROR_OK;
1218         }
1219
1220         /* set readout protection */
1221         stm32x_info->option_bytes.rdp = 0;
1222
1223         if (stm32x_write_options(bank) != ERROR_OK) {
1224                 command_print(CMD, "stm32x failed to lock device");
1225                 return ERROR_OK;
1226         }
1227
1228         command_print(CMD, "stm32x locked");
1229
1230         return ERROR_OK;
1231 }
1232
1233 COMMAND_HANDLER(stm32x_handle_unlock_command)
1234 {
1235         struct target *target = NULL;
1236
1237         if (CMD_ARGC < 1)
1238                 return ERROR_COMMAND_SYNTAX_ERROR;
1239
1240         struct flash_bank *bank;
1241         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1242         if (ERROR_OK != retval)
1243                 return retval;
1244
1245         target = bank->target;
1246
1247         if (target->state != TARGET_HALTED) {
1248                 LOG_ERROR("Target not halted");
1249                 return ERROR_TARGET_NOT_HALTED;
1250         }
1251
1252         retval = stm32x_check_operation_supported(bank);
1253         if (ERROR_OK != retval)
1254                 return retval;
1255
1256         if (stm32x_erase_options(bank) != ERROR_OK) {
1257                 command_print(CMD, "stm32x failed to erase options");
1258                 return ERROR_OK;
1259         }
1260
1261         if (stm32x_write_options(bank) != ERROR_OK) {
1262                 command_print(CMD, "stm32x failed to unlock device");
1263                 return ERROR_OK;
1264         }
1265
1266         command_print(CMD, "stm32x unlocked.\n"
1267                         "INFO: a reset or power cycle is required "
1268                         "for the new settings to take effect.");
1269
1270         return ERROR_OK;
1271 }
1272
1273 COMMAND_HANDLER(stm32x_handle_options_read_command)
1274 {
1275         uint32_t optionbyte, protection;
1276         struct target *target = NULL;
1277         struct stm32x_flash_bank *stm32x_info = NULL;
1278
1279         if (CMD_ARGC < 1)
1280                 return ERROR_COMMAND_SYNTAX_ERROR;
1281
1282         struct flash_bank *bank;
1283         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1284         if (ERROR_OK != retval)
1285                 return retval;
1286
1287         stm32x_info = bank->driver_priv;
1288
1289         target = bank->target;
1290
1291         if (target->state != TARGET_HALTED) {
1292                 LOG_ERROR("Target not halted");
1293                 return ERROR_TARGET_NOT_HALTED;
1294         }
1295
1296         retval = stm32x_check_operation_supported(bank);
1297         if (ERROR_OK != retval)
1298                 return retval;
1299
1300         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1301         if (retval != ERROR_OK)
1302                 return retval;
1303
1304         uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1305
1306         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1307         if (retval != ERROR_OK)
1308                 return retval;
1309
1310         if (optionbyte & (1 << OPT_ERROR))
1311                 command_print(CMD, "option byte complement error");
1312
1313         command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1314         command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1315
1316         command_print(CMD, "read protection: %s",
1317                                 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1318
1319         /* user option bytes are offset depending on variant */
1320         optionbyte >>= stm32x_info->option_offset;
1321
1322         command_print(CMD, "watchdog: %sware",
1323                                 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1324
1325         command_print(CMD, "stop mode: %sreset generated upon entry",
1326                                 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1327
1328         command_print(CMD, "standby mode: %sreset generated upon entry",
1329                                 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1330
1331         if (stm32x_info->has_dual_banks)
1332                 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1333
1334         command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1335
1336         return ERROR_OK;
1337 }
1338
1339 COMMAND_HANDLER(stm32x_handle_options_write_command)
1340 {
1341         struct target *target = NULL;
1342         struct stm32x_flash_bank *stm32x_info = NULL;
1343         uint8_t optionbyte;
1344         uint16_t useropt;
1345
1346         if (CMD_ARGC < 2)
1347                 return ERROR_COMMAND_SYNTAX_ERROR;
1348
1349         struct flash_bank *bank;
1350         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1351         if (ERROR_OK != retval)
1352                 return retval;
1353
1354         stm32x_info = bank->driver_priv;
1355
1356         target = bank->target;
1357
1358         if (target->state != TARGET_HALTED) {
1359                 LOG_ERROR("Target not halted");
1360                 return ERROR_TARGET_NOT_HALTED;
1361         }
1362
1363         retval = stm32x_check_operation_supported(bank);
1364         if (ERROR_OK != retval)
1365                 return retval;
1366
1367         retval = stm32x_read_options(bank);
1368         if (ERROR_OK != retval)
1369                 return retval;
1370
1371         /* start with current options */
1372         optionbyte = stm32x_info->option_bytes.user;
1373         useropt = stm32x_info->option_bytes.data;
1374
1375         /* skip over flash bank */
1376         CMD_ARGC--;
1377         CMD_ARGV++;
1378
1379         while (CMD_ARGC) {
1380                 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1381                         optionbyte |= (1 << 0);
1382                 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1383                         optionbyte &= ~(1 << 0);
1384                 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1385                         optionbyte |= (1 << 1);
1386                 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1387                         optionbyte &= ~(1 << 1);
1388                 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1389                         optionbyte |= (1 << 2);
1390                 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1391                         optionbyte &= ~(1 << 2);
1392                 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1393                         if (CMD_ARGC < 2)
1394                                 return ERROR_COMMAND_SYNTAX_ERROR;
1395                         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1396                         CMD_ARGC--;
1397                         CMD_ARGV++;
1398                 } else if (stm32x_info->has_dual_banks) {
1399                         if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1400                                 optionbyte |= (1 << 3);
1401                         else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1402                                 optionbyte &= ~(1 << 3);
1403                         else
1404                                 return ERROR_COMMAND_SYNTAX_ERROR;
1405                 } else
1406                         return ERROR_COMMAND_SYNTAX_ERROR;
1407                 CMD_ARGC--;
1408                 CMD_ARGV++;
1409         }
1410
1411         if (stm32x_erase_options(bank) != ERROR_OK) {
1412                 command_print(CMD, "stm32x failed to erase options");
1413                 return ERROR_OK;
1414         }
1415
1416         stm32x_info->option_bytes.user = optionbyte;
1417         stm32x_info->option_bytes.data = useropt;
1418
1419         if (stm32x_write_options(bank) != ERROR_OK) {
1420                 command_print(CMD, "stm32x failed to write options");
1421                 return ERROR_OK;
1422         }
1423
1424         command_print(CMD, "stm32x write options complete.\n"
1425                                 "INFO: %spower cycle is required "
1426                                 "for the new settings to take effect.",
1427                                 stm32x_info->can_load_options
1428                                         ? "'stm32f1x options_load' command or " : "");
1429
1430         return ERROR_OK;
1431 }
1432
1433 COMMAND_HANDLER(stm32x_handle_options_load_command)
1434 {
1435         if (CMD_ARGC < 1)
1436                 return ERROR_COMMAND_SYNTAX_ERROR;
1437
1438         struct flash_bank *bank;
1439         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1440         if (ERROR_OK != retval)
1441                 return retval;
1442
1443         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1444
1445         if (!stm32x_info->can_load_options) {
1446                 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1447                         "required instead.");
1448                 return ERROR_FAIL;
1449         }
1450
1451         struct target *target = bank->target;
1452
1453         if (target->state != TARGET_HALTED) {
1454                 LOG_ERROR("Target not halted");
1455                 return ERROR_TARGET_NOT_HALTED;
1456         }
1457
1458         retval = stm32x_check_operation_supported(bank);
1459         if (ERROR_OK != retval)
1460                 return retval;
1461
1462         /* unlock option flash registers */
1463         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1464         if (retval != ERROR_OK)
1465                 return retval;
1466         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1467         if (retval != ERROR_OK)
1468                 return retval;
1469
1470         /* force re-load of option bytes - generates software reset */
1471         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1472         if (retval != ERROR_OK)
1473                 return retval;
1474
1475         return ERROR_OK;
1476 }
1477
1478 static int stm32x_mass_erase(struct flash_bank *bank)
1479 {
1480         struct target *target = bank->target;
1481
1482         if (target->state != TARGET_HALTED) {
1483                 LOG_ERROR("Target not halted");
1484                 return ERROR_TARGET_NOT_HALTED;
1485         }
1486
1487         /* unlock option flash registers */
1488         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1489         if (retval != ERROR_OK)
1490                 return retval;
1491         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1492         if (retval != ERROR_OK)
1493                 return retval;
1494
1495         /* mass erase flash memory */
1496         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1497         if (retval != ERROR_OK)
1498                 return retval;
1499         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1500                         FLASH_MER | FLASH_STRT);
1501         if (retval != ERROR_OK)
1502                 return retval;
1503
1504         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1505         if (retval != ERROR_OK)
1506                 return retval;
1507
1508         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1509         if (retval != ERROR_OK)
1510                 return retval;
1511
1512         return ERROR_OK;
1513 }
1514
1515 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1516 {
1517         if (CMD_ARGC < 1)
1518                 return ERROR_COMMAND_SYNTAX_ERROR;
1519
1520         struct flash_bank *bank;
1521         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1522         if (ERROR_OK != retval)
1523                 return retval;
1524
1525         retval = stm32x_mass_erase(bank);
1526         if (retval == ERROR_OK) {
1527                 /* set all sectors as erased */
1528                 for (unsigned int i = 0; i < bank->num_sectors; i++)
1529                         bank->sectors[i].is_erased = 1;
1530
1531                 command_print(CMD, "stm32x mass erase complete");
1532         } else
1533                 command_print(CMD, "stm32x mass erase failed");
1534
1535         return retval;
1536 }
1537
1538 static const struct command_registration stm32x_exec_command_handlers[] = {
1539         {
1540                 .name = "lock",
1541                 .handler = stm32x_handle_lock_command,
1542                 .mode = COMMAND_EXEC,
1543                 .usage = "bank_id",
1544                 .help = "Lock entire flash device.",
1545         },
1546         {
1547                 .name = "unlock",
1548                 .handler = stm32x_handle_unlock_command,
1549                 .mode = COMMAND_EXEC,
1550                 .usage = "bank_id",
1551                 .help = "Unlock entire protected flash device.",
1552         },
1553         {
1554                 .name = "mass_erase",
1555                 .handler = stm32x_handle_mass_erase_command,
1556                 .mode = COMMAND_EXEC,
1557                 .usage = "bank_id",
1558                 .help = "Erase entire flash device.",
1559         },
1560         {
1561                 .name = "options_read",
1562                 .handler = stm32x_handle_options_read_command,
1563                 .mode = COMMAND_EXEC,
1564                 .usage = "bank_id",
1565                 .help = "Read and display device option bytes.",
1566         },
1567         {
1568                 .name = "options_write",
1569                 .handler = stm32x_handle_options_write_command,
1570                 .mode = COMMAND_EXEC,
1571                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1572                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1573                         "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1574                 .help = "Replace bits in device option bytes.",
1575         },
1576         {
1577                 .name = "options_load",
1578                 .handler = stm32x_handle_options_load_command,
1579                 .mode = COMMAND_EXEC,
1580                 .usage = "bank_id",
1581                 .help = "Force re-load of device option bytes.",
1582         },
1583         COMMAND_REGISTRATION_DONE
1584 };
1585
1586 static const struct command_registration stm32x_command_handlers[] = {
1587         {
1588                 .name = "stm32f1x",
1589                 .mode = COMMAND_ANY,
1590                 .help = "stm32f1x flash command group",
1591                 .usage = "",
1592                 .chain = stm32x_exec_command_handlers,
1593         },
1594         COMMAND_REGISTRATION_DONE
1595 };
1596
1597 const struct flash_driver stm32f1x_flash = {
1598         .name = "stm32f1x",
1599         .commands = stm32x_command_handlers,
1600         .flash_bank_command = stm32x_flash_bank_command,
1601         .erase = stm32x_erase,
1602         .protect = stm32x_protect,
1603         .write = stm32x_write,
1604         .read = default_flash_read,
1605         .probe = stm32x_probe,
1606         .auto_probe = stm32x_auto_probe,
1607         .erase_check = default_flash_blank_check,
1608         .protect_check = stm32x_protect_check,
1609         .info = get_stm32x_info,
1610         .free_driver_priv = default_flash_free_driver_priv,
1611 };