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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "imp.h"
  30 #include <helper/binarybuffer.h>
  31 #include <target/algorithm.h>
  32 #include <target/cortex_m.h>
  33
  34 /* stm32x register locations */
  35
  36 #define FLASH_REG_BASE_B0 0x40022000
  37 #define FLASH_REG_BASE_B1 0x40022040
  38
  39 #define STM32_FLASH_ACR     0x00
  40 #define STM32_FLASH_KEYR    0x04
  41 #define STM32_FLASH_OPTKEYR 0x08
  42 #define STM32_FLASH_SR      0x0C
  43 #define STM32_FLASH_CR      0x10
  44 #define STM32_FLASH_AR      0x14
  45 #define STM32_FLASH_OBR     0x1C
  46 #define STM32_FLASH_WRPR    0x20
  47
  48 /* TODO: Check if code using these really should be hard coded to bank 0.
  49  * There are valid cases, on dual flash devices the protection of the
  50  * second bank is done on the bank0 reg's. */
  51 #define STM32_FLASH_ACR_B0     0x40022000
  52 #define STM32_FLASH_KEYR_B0    0x40022004
  53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  54 #define STM32_FLASH_SR_B0      0x4002200C
  55 #define STM32_FLASH_CR_B0      0x40022010
  56 #define STM32_FLASH_AR_B0      0x40022014
  57 #define STM32_FLASH_OBR_B0     0x4002201C
  58 #define STM32_FLASH_WRPR_B0    0x40022020
  59
  60 /* option byte location */
  61
  62 #define STM32_OB_RDP            0x1FFFF800
  63 #define STM32_OB_USER           0x1FFFF802
  64 #define STM32_OB_DATA0          0x1FFFF804
  65 #define STM32_OB_DATA1          0x1FFFF806
  66 #define STM32_OB_WRP0           0x1FFFF808
  67 #define STM32_OB_WRP1           0x1FFFF80A
  68 #define STM32_OB_WRP2           0x1FFFF80C
  69 #define STM32_OB_WRP3           0x1FFFF80E
  70
  71 /* FLASH_CR register bits */
  72
  73 #define FLASH_PG                        (1 << 0)
  74 #define FLASH_PER                       (1 << 1)
  75 #define FLASH_MER                       (1 << 2)
  76 #define FLASH_OPTPG                     (1 << 4)
  77 #define FLASH_OPTER                     (1 << 5)
  78 #define FLASH_STRT                      (1 << 6)
  79 #define FLASH_LOCK                      (1 << 7)
  80 #define FLASH_OPTWRE            (1 << 9)
  81 #define FLASH_OBL_LAUNCH        (1 << 13)       /* except stm32f1x series */
  82
  83 /* FLASH_SR register bits */
  84
  85 #define FLASH_BSY               (1 << 0)
  86 #define FLASH_PGERR             (1 << 2)
  87 #define FLASH_WRPRTERR  (1 << 4)
  88 #define FLASH_EOP               (1 << 5)
  89
  90 /* STM32_FLASH_OBR bit definitions (reading) */
  91
  92 #define OPT_ERROR               0
  93 #define OPT_READOUT             1
  94 #define OPT_RDWDGSW             2
  95 #define OPT_RDRSTSTOP   3
  96 #define OPT_RDRSTSTDBY  4
  97 #define OPT_BFB2                5       /* dual flash bank only */
  98
  99 /* register unlock keys */
 100
 101 #define KEY1                    0x45670123
 102 #define KEY2                    0xCDEF89AB
 103
 104 /* timeout values */
 105
 106 #define FLASH_WRITE_TIMEOUT 10
 107 #define FLASH_ERASE_TIMEOUT 100
 108
 109 struct stm32x_options {
 110         uint8_t rdp;
 111         uint8_t user;
 112         uint16_t data;
 113         uint32_t protection;
 114 };
 115
 116 struct stm32x_flash_bank {
 117         struct stm32x_options option_bytes;
 118         int ppage_size;
 119         bool probed;
 120
 121         bool has_dual_banks;
 122         /* used to access dual flash bank stm32xl */
 123         bool can_load_options;
 124         uint32_t register_base;
 125         uint8_t default_rdp;
 126         int user_data_offset;
 127         int option_offset;
 128         uint32_t user_bank_size;
 129 };
 130
 131 static int stm32x_mass_erase(struct flash_bank *bank);
 132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
 133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 134                 uint32_t address, uint32_t count);
 135
 136 /* flash bank stm32x <base> <size> 0 0 <target#>
 137  */
 138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 139 {
 140         struct stm32x_flash_bank *stm32x_info;
 141
 142         if (CMD_ARGC < 6)
 143                 return ERROR_COMMAND_SYNTAX_ERROR;
 144
 145         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 146
 147         bank->driver_priv = stm32x_info;
 148         stm32x_info->probed = false;
 149         stm32x_info->has_dual_banks = false;
 150         stm32x_info->can_load_options = false;
 151         stm32x_info->register_base = FLASH_REG_BASE_B0;
 152         stm32x_info->user_bank_size = bank->size;
 153
 154         return ERROR_OK;
 155 }
 156
 157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 158 {
 159         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 160         return reg + stm32x_info->register_base;
 161 }
 162
 163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 164 {
 165         struct target *target = bank->target;
 166         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 167 }
 168
 169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 170 {
 171         struct target *target = bank->target;
 172         uint32_t status;
 173         int retval = ERROR_OK;
 174
 175         /* wait for busy to clear */
 176         for (;;) {
 177                 retval = stm32x_get_flash_status(bank, &status);
 178                 if (retval != ERROR_OK)
 179                         return retval;
 180                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 181                 if ((status & FLASH_BSY) == 0)
 182                         break;
 183                 if (timeout-- <= 0) {
 184                         LOG_ERROR("timed out waiting for flash");
 185                         return ERROR_FAIL;
 186                 }
 187                 alive_sleep(1);
 188         }
 189
 190         if (status & FLASH_WRPRTERR) {
 191                 LOG_ERROR("stm32x device protected");
 192                 retval = ERROR_FAIL;
 193         }
 194
 195         if (status & FLASH_PGERR) {
 196                 LOG_ERROR("stm32x device programming failed");
 197                 retval = ERROR_FAIL;
 198         }
 199
 200         /* Clear but report errors */
 201         if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
 202                 /* If this operation fails, we ignore it and report the original
 203                  * retval
 204                  */
 205                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 206                                 FLASH_WRPRTERR | FLASH_PGERR);
 207         }
 208         return retval;
 209 }
 210
 211 static int stm32x_check_operation_supported(struct flash_bank *bank)
 212 {
 213         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 214
 215         /* if we have a dual flash bank device then
 216          * we need to perform option byte stuff on bank0 only */
 217         if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
 218                 LOG_ERROR("Option byte operations must use bank 0");
 219                 return ERROR_FLASH_OPERATION_FAILED;
 220         }
 221
 222         return ERROR_OK;
 223 }
 224
 225 static int stm32x_read_options(struct flash_bank *bank)
 226 {
 227         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 228         struct target *target = bank->target;
 229         uint32_t option_bytes;
 230         int retval;
 231
 232         /* read user and read protection option bytes, user data option bytes */
 233         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
 234         if (retval != ERROR_OK)
 235                 return retval;
 236
 237         stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
 238         stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
 239         stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
 240
 241         /* read write protection option bytes */
 242         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
 243         if (retval != ERROR_OK)
 244                 return retval;
 245
 246         return ERROR_OK;
 247 }
 248
 249 static int stm32x_erase_options(struct flash_bank *bank)
 250 {
 251         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 252         struct target *target = bank->target;
 253
 254         /* read current options */
 255         stm32x_read_options(bank);
 256
 257         /* unlock flash registers */
 258         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 259         if (retval != ERROR_OK)
 260                 return retval;
 261
 262         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 263         if (retval != ERROR_OK)
 264                 return retval;
 265
 266         /* unlock option flash registers */
 267         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 268         if (retval != ERROR_OK)
 269                 return retval;
 270         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 271         if (retval != ERROR_OK)
 272                 return retval;
 273
 274         /* erase option bytes */
 275         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 276         if (retval != ERROR_OK)
 277                 return retval;
 278         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 279         if (retval != ERROR_OK)
 280                 return retval;
 281
 282         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 283         if (retval != ERROR_OK)
 284                 return retval;
 285
 286         /* clear read protection option byte
 287          * this will also force a device unlock if set */
 288         stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
 289
 290         return ERROR_OK;
 291 }
 292
 293 static int stm32x_write_options(struct flash_bank *bank)
 294 {
 295         struct stm32x_flash_bank *stm32x_info = NULL;
 296         struct target *target = bank->target;
 297
 298         stm32x_info = bank->driver_priv;
 299
 300         /* unlock flash registers */
 301         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 302         if (retval != ERROR_OK)
 303                 return retval;
 304         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 305         if (retval != ERROR_OK)
 306                 return retval;
 307
 308         /* unlock option flash registers */
 309         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 310         if (retval != ERROR_OK)
 311                 return retval;
 312         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 313         if (retval != ERROR_OK)
 314                 return retval;
 315
 316         /* program option bytes */
 317         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 318         if (retval != ERROR_OK)
 319                 return retval;
 320
 321         uint8_t opt_bytes[16];
 322
 323         target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
 324         target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
 325         target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
 326         target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
 327         target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
 328         target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
 329         target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
 330         target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
 331
 332         retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
 333         if (retval != ERROR_OK) {
 334                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 335                         LOG_ERROR("working area required to erase options bytes");
 336                 return retval;
 337         }
 338
 339         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 340         if (retval != ERROR_OK)
 341                 return retval;
 342
 343         return ERROR_OK;
 344 }
 345
 346 static int stm32x_protect_check(struct flash_bank *bank)
 347 {
 348         struct target *target = bank->target;
 349         uint32_t protection;
 350
 351         int retval = stm32x_check_operation_supported(bank);
 352         if (retval != ERROR_OK)
 353                 return retval;
 354
 355         /* medium density - each bit refers to a 4 sector protection block
 356          * high density - each bit refers to a 2 sector protection block
 357          * bit 31 refers to all remaining sectors in a bank */
 358         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 359         if (retval != ERROR_OK)
 360                 return retval;
 361
 362         for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
 363                 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
 364
 365         return ERROR_OK;
 366 }
 367
 368 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
 369                 unsigned int last)
 370 {
 371         struct target *target = bank->target;
 372
 373         if (bank->target->state != TARGET_HALTED) {
 374                 LOG_ERROR("Target not halted");
 375                 return ERROR_TARGET_NOT_HALTED;
 376         }
 377
 378         if ((first == 0) && (last == (bank->num_sectors - 1)))
 379                 return stm32x_mass_erase(bank);
 380
 381         /* unlock flash registers */
 382         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 383         if (retval != ERROR_OK)
 384                 return retval;
 385         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 386         if (retval != ERROR_OK)
 387                 return retval;
 388
 389         for (unsigned int i = first; i <= last; i++) {
 390                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 391                 if (retval != ERROR_OK)
 392                         return retval;
 393                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 394                                 bank->base + bank->sectors[i].offset);
 395                 if (retval != ERROR_OK)
 396                         return retval;
 397                 retval = target_write_u32(target,
 398                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 399                 if (retval != ERROR_OK)
 400                         return retval;
 401
 402                 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 403                 if (retval != ERROR_OK)
 404                         return retval;
 405         }
 406
 407         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 408         if (retval != ERROR_OK)
 409                 return retval;
 410
 411         return ERROR_OK;
 412 }
 413
 414 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 415                 unsigned int last)
 416 {
 417         struct target *target = bank->target;
 418         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 419
 420         if (target->state != TARGET_HALTED) {
 421                 LOG_ERROR("Target not halted");
 422                 return ERROR_TARGET_NOT_HALTED;
 423         }
 424
 425         int retval = stm32x_check_operation_supported(bank);
 426         if (retval != ERROR_OK)
 427                 return retval;
 428
 429         retval = stm32x_erase_options(bank);
 430         if (retval != ERROR_OK) {
 431                 LOG_ERROR("stm32x failed to erase options");
 432                 return retval;
 433         }
 434
 435         for (unsigned int i = first; i <= last; i++) {
 436                 if (set)
 437                         stm32x_info->option_bytes.protection &= ~(1 << i);
 438                 else
 439                         stm32x_info->option_bytes.protection |= (1 << i);
 440         }
 441
 442         return stm32x_write_options(bank);
 443 }
 444
 445 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 446                 uint32_t address, uint32_t count)
 447 {
 448         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 449         struct target *target = bank->target;
 450         uint32_t buffer_size = 16384;
 451         struct working_area *write_algorithm;
 452         struct working_area *source;
 453         struct reg_param reg_params[5];
 454         struct armv7m_algorithm armv7m_info;
 455         int retval = ERROR_OK;
 456
 457         static const uint8_t stm32x_flash_write_code[] = {
 458 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
 459         };
 460
 461         /* flash write code */
 462         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 463                         &write_algorithm) != ERROR_OK) {
 464                 LOG_WARNING("no working area available, can't do block memory writes");
 465                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 466         }
 467
 468         retval = target_write_buffer(target, write_algorithm->address,
 469                         sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
 470         if (retval != ERROR_OK) {
 471                 target_free_working_area(target, write_algorithm);
 472                 return retval;
 473         }
 474
 475         /* memory buffer */
 476         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 477                 buffer_size /= 2;
 478                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 479                 if (buffer_size <= 256) {
 480                         /* we already allocated the writing code, but failed to get a
 481                          * buffer, free the algorithm */
 482                         target_free_working_area(target, write_algorithm);
 483
 484                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 485                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 486                 }
 487         }
 488
 489         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 490         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 491         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 492         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 493         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 494
 495         buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
 496         buf_set_u32(reg_params[1].value, 0, 32, count);
 497         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 498         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 499         buf_set_u32(reg_params[4].value, 0, 32, address);
 500
 501         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 502         armv7m_info.core_mode = ARM_MODE_THREAD;
 503
 504         retval = target_run_flash_async_algorithm(target, buffer, count, 2,
 505                         0, NULL,
 506                         5, reg_params,
 507                         source->address, source->size,
 508                         write_algorithm->address, 0,
 509                         &armv7m_info);
 510
 511         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 512                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 513                                 buf_get_u32(reg_params[4].value, 0, 32));
 514
 515                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
 516                         LOG_ERROR("flash memory not erased before writing");
 517                         /* Clear but report errors */
 518                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
 519                 }
 520
 521                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
 522                         LOG_ERROR("flash memory write protected");
 523                         /* Clear but report errors */
 524                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
 525                 }
 526         }
 527
 528         target_free_working_area(target, source);
 529         target_free_working_area(target, write_algorithm);
 530
 531         destroy_reg_param(&reg_params[0]);
 532         destroy_reg_param(&reg_params[1]);
 533         destroy_reg_param(&reg_params[2]);
 534         destroy_reg_param(&reg_params[3]);
 535         destroy_reg_param(&reg_params[4]);
 536
 537         return retval;
 538 }
 539
 540 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 541                 uint32_t offset, uint32_t count)
 542 {
 543         struct target *target = bank->target;
 544         uint8_t *new_buffer = NULL;
 545
 546         if (bank->target->state != TARGET_HALTED) {
 547                 LOG_ERROR("Target not halted");
 548                 return ERROR_TARGET_NOT_HALTED;
 549         }
 550
 551         if (offset & 0x1) {
 552                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 553                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 554         }
 555
 556         /* If there's an odd number of bytes, the data has to be padded. Duplicate
 557          * the buffer and use the normal code path with a single block write since
 558          * it's probably cheaper than to special case the last odd write using
 559          * discrete accesses. */
 560         if (count & 1) {
 561                 new_buffer = malloc(count + 1);
 562                 if (!new_buffer) {
 563                         LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
 564                         return ERROR_FAIL;
 565                 }
 566                 LOG_INFO("odd number of bytes to write, padding with 0xff");
 567                 buffer = memcpy(new_buffer, buffer, count);
 568                 new_buffer[count++] = 0xff;
 569         }
 570
 571         uint32_t words_remaining = count / 2;
 572         int retval, retval2;
 573
 574         /* unlock flash registers */
 575         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 576         if (retval != ERROR_OK)
 577                 goto cleanup;
 578         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 579         if (retval != ERROR_OK)
 580                 goto cleanup;
 581
 582         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 583         if (retval != ERROR_OK)
 584                 goto cleanup;
 585
 586         /* try using a block write */
 587         retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
 588
 589         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 590                 /* if block write failed (no sufficient working area),
 591                  * we use normal (slow) single halfword accesses */
 592                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 593
 594                 while (words_remaining > 0) {
 595                         retval = target_write_memory(target, bank->base + offset, 2, 1, buffer);
 596                         if (retval != ERROR_OK)
 597                                 goto reset_pg_and_lock;
 598
 599                         retval = stm32x_wait_status_busy(bank, 5);
 600                         if (retval != ERROR_OK)
 601                                 goto reset_pg_and_lock;
 602
 603                         words_remaining--;
 604                         buffer += 2;
 605                         offset += 2;
 606                 }
 607         }
 608
 609 reset_pg_and_lock:
 610         retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 611         if (retval == ERROR_OK)
 612                 retval = retval2;
 613
 614 cleanup:
 615         free(new_buffer);
 616         return retval;
 617 }
 618
 619 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 620 {
 621         struct target *target = bank->target;
 622         uint32_t device_id_register = 0;
 623
 624         if (!target_was_examined(target)) {
 625                 LOG_ERROR("Target not examined yet");
 626                 return ERROR_TARGET_NOT_EXAMINED;
 627         }
 628
 629         switch (cortex_m_get_partno_safe(target)) {
 630         case CORTEX_M0_PARTNO: /* STM32F0x devices */
 631                 device_id_register = 0x40015800;
 632                 break;
 633         case CORTEX_M3_PARTNO: /* STM32F1x devices */
 634                 device_id_register = 0xE0042000;
 635                 break;
 636         case CORTEX_M4_PARTNO: /* STM32F3x devices */
 637                 device_id_register = 0xE0042000;
 638                 break;
 639         case CORTEX_M23_PARTNO: /* GD32E23x devices */
 640                 device_id_register = 0x40015800;
 641                 break;
 642         default:
 643                 LOG_ERROR("Cannot identify target as a stm32x");
 644                 return ERROR_FAIL;
 645         }
 646
 647         /* read stm32 device id register */
 648         int retval = target_read_u32(target, device_id_register, device_id);
 649         if (retval != ERROR_OK)
 650                 return retval;
 651
 652         return retval;
 653 }
 654
 655 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
 656 {
 657         struct target *target = bank->target;
 658         uint32_t flash_size_reg;
 659
 660         if (!target_was_examined(target)) {
 661                 LOG_ERROR("Target not examined yet");
 662                 return ERROR_TARGET_NOT_EXAMINED;
 663         }
 664
 665         switch (cortex_m_get_partno_safe(target)) {
 666         case CORTEX_M0_PARTNO: /* STM32F0x devices */
 667                 flash_size_reg = 0x1FFFF7CC;
 668                 break;
 669         case CORTEX_M3_PARTNO: /* STM32F1x devices */
 670                 flash_size_reg = 0x1FFFF7E0;
 671                 break;
 672         case CORTEX_M4_PARTNO: /* STM32F3x devices */
 673                 flash_size_reg = 0x1FFFF7CC;
 674                 break;
 675         case CORTEX_M23_PARTNO: /* GD32E23x devices */
 676                 flash_size_reg = 0x1FFFF7E0;
 677                 break;
 678         default:
 679                 LOG_ERROR("Cannot identify target as a stm32x");
 680                 return ERROR_FAIL;
 681         }
 682
 683         int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
 684         if (retval != ERROR_OK)
 685                 return retval;
 686
 687         return retval;
 688 }
 689
 690 static int stm32x_probe(struct flash_bank *bank)
 691 {
 692         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 693         uint16_t flash_size_in_kb;
 694         uint16_t max_flash_size_in_kb;
 695         uint32_t dbgmcu_idcode;
 696         int page_size;
 697         uint32_t base_address = 0x08000000;
 698
 699         stm32x_info->probed = false;
 700         stm32x_info->register_base = FLASH_REG_BASE_B0;
 701         stm32x_info->user_data_offset = 10;
 702         stm32x_info->option_offset = 0;
 703
 704         /* default factory read protection level 0 */
 705         stm32x_info->default_rdp = 0xA5;
 706
 707         /* read stm32 device id register */
 708         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 709         if (retval != ERROR_OK)
 710                 return retval;
 711
 712         LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
 713
 714         uint16_t device_id = dbgmcu_idcode & 0xfff;
 715         uint16_t rev_id = dbgmcu_idcode >> 16;
 716
 717         /* set page size, protection granularity and max flash size depending on family */
 718         switch (device_id) {
 719         case 0x440: /* stm32f05x */
 720                 page_size = 1024;
 721                 stm32x_info->ppage_size = 4;
 722                 max_flash_size_in_kb = 64;
 723                 stm32x_info->user_data_offset = 16;
 724                 stm32x_info->option_offset = 6;
 725                 stm32x_info->default_rdp = 0xAA;
 726                 stm32x_info->can_load_options = true;
 727                 break;
 728         case 0x444: /* stm32f03x */
 729         case 0x445: /* stm32f04x */
 730                 page_size = 1024;
 731                 stm32x_info->ppage_size = 4;
 732                 max_flash_size_in_kb = 32;
 733                 stm32x_info->user_data_offset = 16;
 734                 stm32x_info->option_offset = 6;
 735                 stm32x_info->default_rdp = 0xAA;
 736                 stm32x_info->can_load_options = true;
 737                 break;
 738         case 0x448: /* stm32f07x */
 739                 page_size = 2048;
 740                 stm32x_info->ppage_size = 4;
 741                 max_flash_size_in_kb = 128;
 742                 stm32x_info->user_data_offset = 16;
 743                 stm32x_info->option_offset = 6;
 744                 stm32x_info->default_rdp = 0xAA;
 745                 stm32x_info->can_load_options = true;
 746                 break;
 747         case 0x442: /* stm32f09x */
 748                 page_size = 2048;
 749                 stm32x_info->ppage_size = 4;
 750                 max_flash_size_in_kb = 256;
 751                 stm32x_info->user_data_offset = 16;
 752                 stm32x_info->option_offset = 6;
 753                 stm32x_info->default_rdp = 0xAA;
 754                 stm32x_info->can_load_options = true;
 755                 break;
 756         case 0x410: /* stm32f1x medium-density */
 757                 page_size = 1024;
 758                 stm32x_info->ppage_size = 4;
 759                 max_flash_size_in_kb = 128;
 760                 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
 761                    share DEV_ID with STM32F101/2/3 medium-density line,
 762                    however they use a REV_ID different from any STM32 device.
 763                    The main difference is another offset of user option bits
 764                    (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
 765                    (FLASH_OBR/FMC_OBSTAT 0x4002201C).
 766                    This caused problems e.g. during flash block programming
 767                    because of unexpected active hardware watchog. */
 768                 switch (rev_id) {
 769                 case 0x1303: /* gd32f1x0 */
 770                         stm32x_info->user_data_offset = 16;
 771                         stm32x_info->option_offset = 6;
 772                         max_flash_size_in_kb = 64;
 773                         break;
 774                 case 0x1704: /* gd32f3x0 */
 775                         stm32x_info->user_data_offset = 16;
 776                         stm32x_info->option_offset = 6;
 777                         break;
 778                 case 0x1909: /* gd32e23x */
 779                         stm32x_info->user_data_offset = 16;
 780                         stm32x_info->option_offset = 6;
 781                         max_flash_size_in_kb = 64;
 782                         break;
 783                 }
 784                 break;
 785         case 0x412: /* stm32f1x low-density */
 786                 page_size = 1024;
 787                 stm32x_info->ppage_size = 4;
 788                 max_flash_size_in_kb = 32;
 789                 break;
 790         case 0x414: /* stm32f1x high-density */
 791                 page_size = 2048;
 792                 stm32x_info->ppage_size = 2;
 793                 max_flash_size_in_kb = 512;
 794                 break;
 795         case 0x418: /* stm32f1x connectivity */
 796                 page_size = 2048;
 797                 stm32x_info->ppage_size = 2;
 798                 max_flash_size_in_kb = 256;
 799                 break;
 800         case 0x430: /* stm32f1 XL-density (dual flash banks) */
 801                 page_size = 2048;
 802                 stm32x_info->ppage_size = 2;
 803                 max_flash_size_in_kb = 1024;
 804                 stm32x_info->has_dual_banks = true;
 805                 break;
 806         case 0x420: /* stm32f100xx low- and medium-density value line */
 807                 page_size = 1024;
 808                 stm32x_info->ppage_size = 4;
 809                 max_flash_size_in_kb = 128;
 810                 break;
 811         case 0x428: /* stm32f100xx high-density value line */
 812                 page_size = 2048;
 813                 stm32x_info->ppage_size = 4;
 814                 max_flash_size_in_kb = 512;
 815                 break;
 816         case 0x422: /* stm32f302/3xb/c */
 817                 page_size = 2048;
 818                 stm32x_info->ppage_size = 2;
 819                 max_flash_size_in_kb = 256;
 820                 stm32x_info->user_data_offset = 16;
 821                 stm32x_info->option_offset = 6;
 822                 stm32x_info->default_rdp = 0xAA;
 823                 stm32x_info->can_load_options = true;
 824                 break;
 825         case 0x446: /* stm32f303xD/E */
 826                 page_size = 2048;
 827                 stm32x_info->ppage_size = 2;
 828                 max_flash_size_in_kb = 512;
 829                 stm32x_info->user_data_offset = 16;
 830                 stm32x_info->option_offset = 6;
 831                 stm32x_info->default_rdp = 0xAA;
 832                 stm32x_info->can_load_options = true;
 833                 break;
 834         case 0x432: /* stm32f37x */
 835                 page_size = 2048;
 836                 stm32x_info->ppage_size = 2;
 837                 max_flash_size_in_kb = 256;
 838                 stm32x_info->user_data_offset = 16;
 839                 stm32x_info->option_offset = 6;
 840                 stm32x_info->default_rdp = 0xAA;
 841                 stm32x_info->can_load_options = true;
 842                 break;
 843         case 0x438: /* stm32f33x */
 844         case 0x439: /* stm32f302x6/8 */
 845                 page_size = 2048;
 846                 stm32x_info->ppage_size = 2;
 847                 max_flash_size_in_kb = 64;
 848                 stm32x_info->user_data_offset = 16;
 849                 stm32x_info->option_offset = 6;
 850                 stm32x_info->default_rdp = 0xAA;
 851                 stm32x_info->can_load_options = true;
 852                 break;
 853         default:
 854                 LOG_WARNING("Cannot identify target as a STM32 family.");
 855                 return ERROR_FAIL;
 856         }
 857
 858         /* get flash size from target. */
 859         retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
 860
 861         /* failed reading flash size or flash size invalid (early silicon),
 862          * default to max target family */
 863         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 864                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 865                         max_flash_size_in_kb);
 866                 flash_size_in_kb = max_flash_size_in_kb;
 867         }
 868
 869         if (stm32x_info->has_dual_banks) {
 870                 /* split reported size into matching bank */
 871                 if (bank->base != 0x08080000) {
 872                         /* bank 0 will be fixed 512k */
 873                         flash_size_in_kb = 512;
 874                 } else {
 875                         flash_size_in_kb -= 512;
 876                         /* bank1 also uses a register offset */
 877                         stm32x_info->register_base = FLASH_REG_BASE_B1;
 878                         base_address = 0x08080000;
 879                 }
 880         }
 881
 882         /* if the user sets the size manually then ignore the probed value
 883          * this allows us to work around devices that have a invalid flash size register value */
 884         if (stm32x_info->user_bank_size) {
 885                 LOG_INFO("ignoring flash probed value, using configured bank size");
 886                 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
 887         }
 888
 889         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 890
 891         /* did we assign flash size? */
 892         assert(flash_size_in_kb != 0xffff);
 893
 894         /* calculate numbers of pages */
 895         int num_pages = flash_size_in_kb * 1024 / page_size;
 896
 897         /* check that calculation result makes sense */
 898         assert(num_pages > 0);
 899
 900         free(bank->sectors);
 901         bank->sectors = NULL;
 902
 903         free(bank->prot_blocks);
 904         bank->prot_blocks = NULL;
 905
 906         bank->base = base_address;
 907         bank->size = (num_pages * page_size);
 908
 909         bank->num_sectors = num_pages;
 910         bank->sectors = alloc_block_array(0, page_size, num_pages);
 911         if (!bank->sectors)
 912                 return ERROR_FAIL;
 913
 914         /* calculate number of write protection blocks */
 915         int num_prot_blocks = num_pages / stm32x_info->ppage_size;
 916         if (num_prot_blocks > 32)
 917                 num_prot_blocks = 32;
 918
 919         bank->num_prot_blocks = num_prot_blocks;
 920         bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
 921         if (!bank->prot_blocks)
 922                 return ERROR_FAIL;
 923
 924         if (num_prot_blocks == 32)
 925                 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
 926
 927         stm32x_info->probed = true;
 928
 929         return ERROR_OK;
 930 }
 931
 932 static int stm32x_auto_probe(struct flash_bank *bank)
 933 {
 934         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 935         if (stm32x_info->probed)
 936                 return ERROR_OK;
 937         return stm32x_probe(bank);
 938 }
 939
 940 #if 0
 941 COMMAND_HANDLER(stm32x_handle_part_id_command)
 942 {
 943         return ERROR_OK;
 944 }
 945 #endif
 946
 947 static const char *get_stm32f0_revision(uint16_t rev_id)
 948 {
 949         const char *rev_str = NULL;
 950
 951         switch (rev_id) {
 952         case 0x1000:
 953                 rev_str = "1.0";
 954                 break;
 955         case 0x2000:
 956                 rev_str = "2.0";
 957                 break;
 958         }
 959         return rev_str;
 960 }
 961
 962 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
 963 {
 964         uint32_t dbgmcu_idcode;
 965
 966         /* read stm32 device id register */
 967         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 968         if (retval != ERROR_OK)
 969                 return retval;
 970
 971         uint16_t device_id = dbgmcu_idcode & 0xfff;
 972         uint16_t rev_id = dbgmcu_idcode >> 16;
 973         const char *device_str;
 974         const char *rev_str = NULL;
 975
 976         switch (device_id) {
 977         case 0x410:
 978                 device_str = "STM32F10x (Medium Density)";
 979
 980                 switch (rev_id) {
 981                 case 0x0000:
 982                         rev_str = "A";
 983                         break;
 984
 985                 case 0x1303: /* gd32f1x0 */
 986                         device_str = "GD32F1x0";
 987                         break;
 988
 989                 case 0x1704: /* gd32f3x0 */
 990                         device_str = "GD32F3x0";
 991                         break;
 992
 993                 case 0x1909: /* gd32e23x */
 994                         device_str = "GD32E23x";
 995                         break;
 996
 997                 case 0x2000:
 998                         rev_str = "B";
 999                         break;
1000
1001                 case 0x2001:
1002                         rev_str = "Z";
1003                         break;
1004
1005                 case 0x2003:
1006                         rev_str = "Y";
1007                         break;
1008                 }
1009                 break;
1010
1011         case 0x412:
1012                 device_str = "STM32F10x (Low Density)";
1013
1014                 switch (rev_id) {
1015                 case 0x1000:
1016                         rev_str = "A";
1017                         break;
1018                 }
1019                 break;
1020
1021         case 0x414:
1022                 device_str = "STM32F10x (High Density)";
1023
1024                 switch (rev_id) {
1025                 case 0x1000:
1026                         rev_str = "A";
1027                         break;
1028
1029                 case 0x1001:
1030                         rev_str = "Z";
1031                         break;
1032
1033                 case 0x1003:
1034                         rev_str = "Y";
1035                         break;
1036                 }
1037                 break;
1038
1039         case 0x418:
1040                 device_str = "STM32F10x (Connectivity)";
1041
1042                 switch (rev_id) {
1043                 case 0x1000:
1044                         rev_str = "A";
1045                         break;
1046
1047                 case 0x1001:
1048                         rev_str = "Z";
1049                         break;
1050                 }
1051                 break;
1052
1053         case 0x420:
1054                 device_str = "STM32F100 (Low/Medium Density)";
1055
1056                 switch (rev_id) {
1057                 case 0x1000:
1058                         rev_str = "A";
1059                         break;
1060
1061                 case 0x1001:
1062                         rev_str = "Z";
1063                         break;
1064                 }
1065                 break;
1066
1067         case 0x422:
1068                 device_str = "STM32F302xB/C";
1069
1070                 switch (rev_id) {
1071                 case 0x1000:
1072                         rev_str = "A";
1073                         break;
1074
1075                 case 0x1001:
1076                         rev_str = "Z";
1077                         break;
1078
1079                 case 0x1003:
1080                         rev_str = "Y";
1081                         break;
1082
1083                 case 0x2000:
1084                         rev_str = "B";
1085                         break;
1086                 }
1087                 break;
1088
1089         case 0x428:
1090                 device_str = "STM32F100 (High Density)";
1091
1092                 switch (rev_id) {
1093                 case 0x1000:
1094                         rev_str = "A";
1095                         break;
1096
1097                 case 0x1001:
1098                         rev_str = "Z";
1099                         break;
1100                 }
1101                 break;
1102
1103         case 0x430:
1104                 device_str = "STM32F10x (XL Density)";
1105
1106                 switch (rev_id) {
1107                 case 0x1000:
1108                         rev_str = "A";
1109                         break;
1110                 }
1111                 break;
1112
1113         case 0x432:
1114                 device_str = "STM32F37x";
1115
1116                 switch (rev_id) {
1117                 case 0x1000:
1118                         rev_str = "A";
1119                         break;
1120
1121                 case 0x2000:
1122                         rev_str = "B";
1123                         break;
1124                 }
1125                 break;
1126
1127         case 0x438:
1128                 device_str = "STM32F33x";
1129
1130                 switch (rev_id) {
1131                 case 0x1000:
1132                         rev_str = "A";
1133                         break;
1134                 }
1135                 break;
1136
1137         case 0x439:
1138                 device_str = "STM32F302x6/8";
1139
1140                 switch (rev_id) {
1141                 case 0x1000:
1142                         rev_str = "A";
1143                         break;
1144
1145                 case 0x1001:
1146                         rev_str = "Z";
1147                         break;
1148                 }
1149                 break;
1150
1151         case 0x444:
1152                 device_str = "STM32F03x";
1153                 rev_str = get_stm32f0_revision(rev_id);
1154                 break;
1155
1156         case 0x440:
1157                 device_str = "STM32F05x";
1158                 rev_str = get_stm32f0_revision(rev_id);
1159                 break;
1160
1161         case 0x445:
1162                 device_str = "STM32F04x";
1163                 rev_str = get_stm32f0_revision(rev_id);
1164                 break;
1165
1166         case 0x446:
1167                 device_str = "STM32F303xD/E";
1168                 switch (rev_id) {
1169                 case 0x1000:
1170                         rev_str = "A";
1171                         break;
1172                 }
1173                 break;
1174
1175         case 0x448:
1176                 device_str = "STM32F07x";
1177                 rev_str = get_stm32f0_revision(rev_id);
1178                 break;
1179
1180         case 0x442:
1181                 device_str = "STM32F09x";
1182                 rev_str = get_stm32f0_revision(rev_id);
1183                 break;
1184
1185         default:
1186                 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1187                 return ERROR_FAIL;
1188         }
1189
1190         if (rev_str)
1191                 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1192         else
1193                 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1194
1195         return ERROR_OK;
1196 }
1197
1198 COMMAND_HANDLER(stm32x_handle_lock_command)
1199 {
1200         struct target *target = NULL;
1201         struct stm32x_flash_bank *stm32x_info = NULL;
1202
1203         if (CMD_ARGC < 1)
1204                 return ERROR_COMMAND_SYNTAX_ERROR;
1205
1206         struct flash_bank *bank;
1207         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1208         if (retval != ERROR_OK)
1209                 return retval;
1210
1211         stm32x_info = bank->driver_priv;
1212
1213         target = bank->target;
1214
1215         if (target->state != TARGET_HALTED) {
1216                 LOG_ERROR("Target not halted");
1217                 return ERROR_TARGET_NOT_HALTED;
1218         }
1219
1220         retval = stm32x_check_operation_supported(bank);
1221         if (retval != ERROR_OK)
1222                 return retval;
1223
1224         if (stm32x_erase_options(bank) != ERROR_OK) {
1225                 command_print(CMD, "stm32x failed to erase options");
1226                 return ERROR_OK;
1227         }
1228
1229         /* set readout protection */
1230         stm32x_info->option_bytes.rdp = 0;
1231
1232         if (stm32x_write_options(bank) != ERROR_OK) {
1233                 command_print(CMD, "stm32x failed to lock device");
1234                 return ERROR_OK;
1235         }
1236
1237         command_print(CMD, "stm32x locked");
1238
1239         return ERROR_OK;
1240 }
1241
1242 COMMAND_HANDLER(stm32x_handle_unlock_command)
1243 {
1244         struct target *target = NULL;
1245
1246         if (CMD_ARGC < 1)
1247                 return ERROR_COMMAND_SYNTAX_ERROR;
1248
1249         struct flash_bank *bank;
1250         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1251         if (retval != ERROR_OK)
1252                 return retval;
1253
1254         target = bank->target;
1255
1256         if (target->state != TARGET_HALTED) {
1257                 LOG_ERROR("Target not halted");
1258                 return ERROR_TARGET_NOT_HALTED;
1259         }
1260
1261         retval = stm32x_check_operation_supported(bank);
1262         if (retval != ERROR_OK)
1263                 return retval;
1264
1265         if (stm32x_erase_options(bank) != ERROR_OK) {
1266                 command_print(CMD, "stm32x failed to erase options");
1267                 return ERROR_OK;
1268         }
1269
1270         if (stm32x_write_options(bank) != ERROR_OK) {
1271                 command_print(CMD, "stm32x failed to unlock device");
1272                 return ERROR_OK;
1273         }
1274
1275         command_print(CMD, "stm32x unlocked.\n"
1276                         "INFO: a reset or power cycle is required "
1277                         "for the new settings to take effect.");
1278
1279         return ERROR_OK;
1280 }
1281
1282 COMMAND_HANDLER(stm32x_handle_options_read_command)
1283 {
1284         uint32_t optionbyte, protection;
1285         struct target *target = NULL;
1286         struct stm32x_flash_bank *stm32x_info = NULL;
1287
1288         if (CMD_ARGC < 1)
1289                 return ERROR_COMMAND_SYNTAX_ERROR;
1290
1291         struct flash_bank *bank;
1292         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1293         if (retval != ERROR_OK)
1294                 return retval;
1295
1296         stm32x_info = bank->driver_priv;
1297
1298         target = bank->target;
1299
1300         if (target->state != TARGET_HALTED) {
1301                 LOG_ERROR("Target not halted");
1302                 return ERROR_TARGET_NOT_HALTED;
1303         }
1304
1305         retval = stm32x_check_operation_supported(bank);
1306         if (retval != ERROR_OK)
1307                 return retval;
1308
1309         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1310         if (retval != ERROR_OK)
1311                 return retval;
1312
1313         uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1314
1315         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1316         if (retval != ERROR_OK)
1317                 return retval;
1318
1319         if (optionbyte & (1 << OPT_ERROR))
1320                 command_print(CMD, "option byte complement error");
1321
1322         command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1323         command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1324
1325         command_print(CMD, "read protection: %s",
1326                                 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1327
1328         /* user option bytes are offset depending on variant */
1329         optionbyte >>= stm32x_info->option_offset;
1330
1331         command_print(CMD, "watchdog: %sware",
1332                                 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1333
1334         command_print(CMD, "stop mode: %sreset generated upon entry",
1335                                 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1336
1337         command_print(CMD, "standby mode: %sreset generated upon entry",
1338                                 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1339
1340         if (stm32x_info->has_dual_banks)
1341                 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1342
1343         command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1344
1345         return ERROR_OK;
1346 }
1347
1348 COMMAND_HANDLER(stm32x_handle_options_write_command)
1349 {
1350         struct target *target = NULL;
1351         struct stm32x_flash_bank *stm32x_info = NULL;
1352         uint8_t optionbyte;
1353         uint16_t useropt;
1354
1355         if (CMD_ARGC < 2)
1356                 return ERROR_COMMAND_SYNTAX_ERROR;
1357
1358         struct flash_bank *bank;
1359         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1360         if (retval != ERROR_OK)
1361                 return retval;
1362
1363         stm32x_info = bank->driver_priv;
1364
1365         target = bank->target;
1366
1367         if (target->state != TARGET_HALTED) {
1368                 LOG_ERROR("Target not halted");
1369                 return ERROR_TARGET_NOT_HALTED;
1370         }
1371
1372         retval = stm32x_check_operation_supported(bank);
1373         if (retval != ERROR_OK)
1374                 return retval;
1375
1376         retval = stm32x_read_options(bank);
1377         if (retval != ERROR_OK)
1378                 return retval;
1379
1380         /* start with current options */
1381         optionbyte = stm32x_info->option_bytes.user;
1382         useropt = stm32x_info->option_bytes.data;
1383
1384         /* skip over flash bank */
1385         CMD_ARGC--;
1386         CMD_ARGV++;
1387
1388         while (CMD_ARGC) {
1389                 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1390                         optionbyte |= (1 << 0);
1391                 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1392                         optionbyte &= ~(1 << 0);
1393                 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1394                         optionbyte |= (1 << 1);
1395                 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1396                         optionbyte &= ~(1 << 1);
1397                 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1398                         optionbyte |= (1 << 2);
1399                 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1400                         optionbyte &= ~(1 << 2);
1401                 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1402                         if (CMD_ARGC < 2)
1403                                 return ERROR_COMMAND_SYNTAX_ERROR;
1404                         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1405                         CMD_ARGC--;
1406                         CMD_ARGV++;
1407                 } else if (stm32x_info->has_dual_banks) {
1408                         if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1409                                 optionbyte |= (1 << 3);
1410                         else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1411                                 optionbyte &= ~(1 << 3);
1412                         else
1413                                 return ERROR_COMMAND_SYNTAX_ERROR;
1414                 } else
1415                         return ERROR_COMMAND_SYNTAX_ERROR;
1416                 CMD_ARGC--;
1417                 CMD_ARGV++;
1418         }
1419
1420         if (stm32x_erase_options(bank) != ERROR_OK) {
1421                 command_print(CMD, "stm32x failed to erase options");
1422                 return ERROR_OK;
1423         }
1424
1425         stm32x_info->option_bytes.user = optionbyte;
1426         stm32x_info->option_bytes.data = useropt;
1427
1428         if (stm32x_write_options(bank) != ERROR_OK) {
1429                 command_print(CMD, "stm32x failed to write options");
1430                 return ERROR_OK;
1431         }
1432
1433         command_print(CMD, "stm32x write options complete.\n"
1434                                 "INFO: %spower cycle is required "
1435                                 "for the new settings to take effect.",
1436                                 stm32x_info->can_load_options
1437                                         ? "'stm32f1x options_load' command or " : "");
1438
1439         return ERROR_OK;
1440 }
1441
1442 COMMAND_HANDLER(stm32x_handle_options_load_command)
1443 {
1444         if (CMD_ARGC < 1)
1445                 return ERROR_COMMAND_SYNTAX_ERROR;
1446
1447         struct flash_bank *bank;
1448         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1449         if (retval != ERROR_OK)
1450                 return retval;
1451
1452         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1453
1454         if (!stm32x_info->can_load_options) {
1455                 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1456                         "required instead.");
1457                 return ERROR_FAIL;
1458         }
1459
1460         struct target *target = bank->target;
1461
1462         if (target->state != TARGET_HALTED) {
1463                 LOG_ERROR("Target not halted");
1464                 return ERROR_TARGET_NOT_HALTED;
1465         }
1466
1467         retval = stm32x_check_operation_supported(bank);
1468         if (retval != ERROR_OK)
1469                 return retval;
1470
1471         /* unlock option flash registers */
1472         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1473         if (retval != ERROR_OK)
1474                 return retval;
1475         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1476         if (retval != ERROR_OK)
1477                 return retval;
1478
1479         /* force re-load of option bytes - generates software reset */
1480         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1481         if (retval != ERROR_OK)
1482                 return retval;
1483
1484         return ERROR_OK;
1485 }
1486
1487 static int stm32x_mass_erase(struct flash_bank *bank)
1488 {
1489         struct target *target = bank->target;
1490
1491         if (target->state != TARGET_HALTED) {
1492                 LOG_ERROR("Target not halted");
1493                 return ERROR_TARGET_NOT_HALTED;
1494         }
1495
1496         /* unlock option flash registers */
1497         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1498         if (retval != ERROR_OK)
1499                 return retval;
1500         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1501         if (retval != ERROR_OK)
1502                 return retval;
1503
1504         /* mass erase flash memory */
1505         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1506         if (retval != ERROR_OK)
1507                 return retval;
1508         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1509                         FLASH_MER | FLASH_STRT);
1510         if (retval != ERROR_OK)
1511                 return retval;
1512
1513         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1514         if (retval != ERROR_OK)
1515                 return retval;
1516
1517         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1518         if (retval != ERROR_OK)
1519                 return retval;
1520
1521         return ERROR_OK;
1522 }
1523
1524 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1525 {
1526         if (CMD_ARGC < 1)
1527                 return ERROR_COMMAND_SYNTAX_ERROR;
1528
1529         struct flash_bank *bank;
1530         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1531         if (retval != ERROR_OK)
1532                 return retval;
1533
1534         retval = stm32x_mass_erase(bank);
1535         if (retval == ERROR_OK)
1536                 command_print(CMD, "stm32x mass erase complete");
1537         else
1538                 command_print(CMD, "stm32x mass erase failed");
1539
1540         return retval;
1541 }
1542
1543 static const struct command_registration stm32f1x_exec_command_handlers[] = {
1544         {
1545                 .name = "lock",
1546                 .handler = stm32x_handle_lock_command,
1547                 .mode = COMMAND_EXEC,
1548                 .usage = "bank_id",
1549                 .help = "Lock entire flash device.",
1550         },
1551         {
1552                 .name = "unlock",
1553                 .handler = stm32x_handle_unlock_command,
1554                 .mode = COMMAND_EXEC,
1555                 .usage = "bank_id",
1556                 .help = "Unlock entire protected flash device.",
1557         },
1558         {
1559                 .name = "mass_erase",
1560                 .handler = stm32x_handle_mass_erase_command,
1561                 .mode = COMMAND_EXEC,
1562                 .usage = "bank_id",
1563                 .help = "Erase entire flash device.",
1564         },
1565         {
1566                 .name = "options_read",
1567                 .handler = stm32x_handle_options_read_command,
1568                 .mode = COMMAND_EXEC,
1569                 .usage = "bank_id",
1570                 .help = "Read and display device option bytes.",
1571         },
1572         {
1573                 .name = "options_write",
1574                 .handler = stm32x_handle_options_write_command,
1575                 .mode = COMMAND_EXEC,
1576                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1577                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1578                         "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1579                 .help = "Replace bits in device option bytes.",
1580         },
1581         {
1582                 .name = "options_load",
1583                 .handler = stm32x_handle_options_load_command,
1584                 .mode = COMMAND_EXEC,
1585                 .usage = "bank_id",
1586                 .help = "Force re-load of device option bytes.",
1587         },
1588         COMMAND_REGISTRATION_DONE
1589 };
1590
1591 static const struct command_registration stm32f1x_command_handlers[] = {
1592         {
1593                 .name = "stm32f1x",
1594                 .mode = COMMAND_ANY,
1595                 .help = "stm32f1x flash command group",
1596                 .usage = "",
1597                 .chain = stm32f1x_exec_command_handlers,
1598         },
1599         COMMAND_REGISTRATION_DONE
1600 };
1601
1602 const struct flash_driver stm32f1x_flash = {
1603         .name = "stm32f1x",
1604         .commands = stm32f1x_command_handlers,
1605         .flash_bank_command = stm32x_flash_bank_command,
1606         .erase = stm32x_erase,
1607         .protect = stm32x_protect,
1608         .write = stm32x_write,
1609         .read = default_flash_read,
1610         .probe = stm32x_probe,
1611         .auto_probe = stm32x_auto_probe,
1612         .erase_check = default_flash_blank_check,
1613         .protect_check = stm32x_protect_check,
1614         .info = get_stm32x_info,
1615         .free_driver_priv = default_flash_free_driver_priv,
1616 };