1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/cortex_m.h>
34 /* stm32x register locations */
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
60 /* option byte location */
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
71 /* FLASH_CR register bits */
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
83 /* FLASH_SR register bits */
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
90 /* STM32_FLASH_OBR bit definitions (reading) */
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
99 /* register unlock keys */
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
109 struct stm32x_options {
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
126 int user_data_offset;
128 uint32_t user_bank_size;
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t count);
136 /* flash bank stm32x <base> <size> 0 0 <target#>
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
140 struct stm32x_flash_bank *stm32x_info;
143 return ERROR_COMMAND_SYNTAX_ERROR;
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = false;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
159 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
160 return reg + stm32x_info->register_base;
163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
165 struct target *target = bank->target;
166 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
171 struct target *target = bank->target;
173 int retval = ERROR_OK;
175 /* wait for busy to clear */
177 retval = stm32x_get_flash_status(bank, &status);
178 if (retval != ERROR_OK)
180 LOG_DEBUG("status: 0x%" PRIx32 "", status);
181 if ((status & FLASH_BSY) == 0)
183 if (timeout-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
190 if (status & FLASH_WRPRTERR) {
191 LOG_ERROR("stm32x device protected");
195 if (status & FLASH_PGERR) {
196 LOG_ERROR("stm32x device programming failed");
200 /* Clear but report errors */
201 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
202 /* If this operation fails, we ignore it and report the original
205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
206 FLASH_WRPRTERR | FLASH_PGERR);
211 static int stm32x_check_operation_supported(struct flash_bank *bank)
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
218 LOG_ERROR("Option byte operations must use bank 0");
219 return ERROR_FLASH_OPERATION_FAILED;
225 static int stm32x_read_options(struct flash_bank *bank)
227 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
228 struct target *target = bank->target;
229 uint32_t option_bytes;
232 /* read user and read protection option bytes, user data option bytes */
233 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
234 if (retval != ERROR_OK)
237 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
238 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
239 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
241 /* read write protection option bytes */
242 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
243 if (retval != ERROR_OK)
249 static int stm32x_erase_options(struct flash_bank *bank)
251 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
252 struct target *target = bank->target;
254 /* read current options */
255 stm32x_read_options(bank);
257 /* unlock flash registers */
258 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
259 if (retval != ERROR_OK)
262 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
263 if (retval != ERROR_OK)
266 /* unlock option flash registers */
267 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
268 if (retval != ERROR_OK)
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
271 if (retval != ERROR_OK)
274 /* erase option bytes */
275 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
276 if (retval != ERROR_OK)
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
282 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
283 if (retval != ERROR_OK)
286 /* clear read protection option byte
287 * this will also force a device unlock if set */
288 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
293 static int stm32x_write_options(struct flash_bank *bank)
295 struct stm32x_flash_bank *stm32x_info = NULL;
296 struct target *target = bank->target;
298 stm32x_info = bank->driver_priv;
300 /* unlock flash registers */
301 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
302 if (retval != ERROR_OK)
304 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
305 if (retval != ERROR_OK)
308 /* unlock option flash registers */
309 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
310 if (retval != ERROR_OK)
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
313 if (retval != ERROR_OK)
316 /* program option bytes */
317 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
318 if (retval != ERROR_OK)
321 uint8_t opt_bytes[16];
323 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
324 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
325 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
326 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
327 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
328 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
329 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
330 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
332 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
333 if (retval != ERROR_OK) {
334 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
335 LOG_ERROR("working area required to erase options bytes");
339 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
340 if (retval != ERROR_OK)
346 static int stm32x_protect_check(struct flash_bank *bank)
348 struct target *target = bank->target;
351 int retval = stm32x_check_operation_supported(bank);
352 if (retval != ERROR_OK)
355 /* medium density - each bit refers to a 4 sector protection block
356 * high density - each bit refers to a 2 sector protection block
357 * bit 31 refers to all remaining sectors in a bank */
358 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
359 if (retval != ERROR_OK)
362 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
363 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
368 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
371 struct target *target = bank->target;
373 if (bank->target->state != TARGET_HALTED) {
374 LOG_ERROR("Target not halted");
375 return ERROR_TARGET_NOT_HALTED;
378 if ((first == 0) && (last == (bank->num_sectors - 1)))
379 return stm32x_mass_erase(bank);
381 /* unlock flash registers */
382 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
383 if (retval != ERROR_OK)
385 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
386 if (retval != ERROR_OK)
389 for (unsigned int i = first; i <= last; i++) {
390 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
391 if (retval != ERROR_OK)
393 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
394 bank->base + bank->sectors[i].offset);
395 if (retval != ERROR_OK)
397 retval = target_write_u32(target,
398 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
399 if (retval != ERROR_OK)
402 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
403 if (retval != ERROR_OK)
407 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
408 if (retval != ERROR_OK)
414 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
417 struct target *target = bank->target;
418 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
420 if (target->state != TARGET_HALTED) {
421 LOG_ERROR("Target not halted");
422 return ERROR_TARGET_NOT_HALTED;
425 int retval = stm32x_check_operation_supported(bank);
426 if (retval != ERROR_OK)
429 retval = stm32x_erase_options(bank);
430 if (retval != ERROR_OK) {
431 LOG_ERROR("stm32x failed to erase options");
435 for (unsigned int i = first; i <= last; i++) {
437 stm32x_info->option_bytes.protection &= ~(1 << i);
439 stm32x_info->option_bytes.protection |= (1 << i);
442 return stm32x_write_options(bank);
445 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
446 uint32_t address, uint32_t count)
448 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
449 struct target *target = bank->target;
450 uint32_t buffer_size = 16384;
451 struct working_area *write_algorithm;
452 struct working_area *source;
453 struct reg_param reg_params[5];
454 struct armv7m_algorithm armv7m_info;
455 int retval = ERROR_OK;
457 static const uint8_t stm32x_flash_write_code[] = {
458 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
461 /* flash write code */
462 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
463 &write_algorithm) != ERROR_OK) {
464 LOG_WARNING("no working area available, can't do block memory writes");
465 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
468 retval = target_write_buffer(target, write_algorithm->address,
469 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
470 if (retval != ERROR_OK) {
471 target_free_working_area(target, write_algorithm);
476 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
478 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
479 if (buffer_size <= 256) {
480 /* we already allocated the writing code, but failed to get a
481 * buffer, free the algorithm */
482 target_free_working_area(target, write_algorithm);
484 LOG_WARNING("no large enough working area available, can't do block memory writes");
485 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
489 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
490 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
491 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer start */
492 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* buffer end */
493 init_reg_param(®_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
495 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
496 buf_set_u32(reg_params[1].value, 0, 32, count);
497 buf_set_u32(reg_params[2].value, 0, 32, source->address);
498 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
499 buf_set_u32(reg_params[4].value, 0, 32, address);
501 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
502 armv7m_info.core_mode = ARM_MODE_THREAD;
504 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
507 source->address, source->size,
508 write_algorithm->address, 0,
511 if (retval == ERROR_FLASH_OPERATION_FAILED) {
512 LOG_ERROR("flash write failed at address 0x%"PRIx32,
513 buf_get_u32(reg_params[4].value, 0, 32));
515 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
516 LOG_ERROR("flash memory not erased before writing");
517 /* Clear but report errors */
518 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
521 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
522 LOG_ERROR("flash memory write protected");
523 /* Clear but report errors */
524 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
528 target_free_working_area(target, source);
529 target_free_working_area(target, write_algorithm);
531 destroy_reg_param(®_params[0]);
532 destroy_reg_param(®_params[1]);
533 destroy_reg_param(®_params[2]);
534 destroy_reg_param(®_params[3]);
535 destroy_reg_param(®_params[4]);
540 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
541 uint32_t offset, uint32_t count)
543 struct target *target = bank->target;
544 uint8_t *new_buffer = NULL;
546 if (bank->target->state != TARGET_HALTED) {
547 LOG_ERROR("Target not halted");
548 return ERROR_TARGET_NOT_HALTED;
552 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
553 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
556 /* If there's an odd number of bytes, the data has to be padded. Duplicate
557 * the buffer and use the normal code path with a single block write since
558 * it's probably cheaper than to special case the last odd write using
559 * discrete accesses. */
561 new_buffer = malloc(count + 1);
563 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
566 LOG_INFO("odd number of bytes to write, padding with 0xff");
567 buffer = memcpy(new_buffer, buffer, count);
568 new_buffer[count++] = 0xff;
571 uint32_t words_remaining = count / 2;
574 /* unlock flash registers */
575 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
576 if (retval != ERROR_OK)
578 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
579 if (retval != ERROR_OK)
582 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
583 if (retval != ERROR_OK)
586 /* try using a block write */
587 retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
589 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
590 /* if block write failed (no sufficient working area),
591 * we use normal (slow) single halfword accesses */
592 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
594 while (words_remaining > 0) {
596 memcpy(&value, buffer, sizeof(uint16_t));
598 retval = target_write_u16(target, bank->base + offset, value);
599 if (retval != ERROR_OK)
600 goto reset_pg_and_lock;
602 retval = stm32x_wait_status_busy(bank, 5);
603 if (retval != ERROR_OK)
604 goto reset_pg_and_lock;
613 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
614 if (retval == ERROR_OK)
622 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
624 struct target *target = bank->target;
625 struct cortex_m_common *cortex_m = target_to_cm(target);
626 uint32_t device_id_register = 0;
628 if (!target_was_examined(target)) {
629 LOG_ERROR("Target not examined yet");
633 switch (cortex_m->core_info->partno) {
634 case CORTEX_M0_PARTNO: /* STM32F0x devices */
635 device_id_register = 0x40015800;
637 case CORTEX_M3_PARTNO: /* STM32F1x devices */
638 device_id_register = 0xE0042000;
640 case CORTEX_M4_PARTNO: /* STM32F3x devices */
641 device_id_register = 0xE0042000;
644 LOG_ERROR("Cannot identify target as a stm32x");
648 /* read stm32 device id register */
649 int retval = target_read_u32(target, device_id_register, device_id);
650 if (retval != ERROR_OK)
656 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
658 struct target *target = bank->target;
659 struct cortex_m_common *cortex_m = target_to_cm(target);
660 uint32_t flash_size_reg;
662 if (!target_was_examined(target)) {
663 LOG_ERROR("Target not examined yet");
667 switch (cortex_m->core_info->partno) {
668 case CORTEX_M0_PARTNO: /* STM32F0x devices */
669 flash_size_reg = 0x1FFFF7CC;
671 case CORTEX_M3_PARTNO: /* STM32F1x devices */
672 flash_size_reg = 0x1FFFF7E0;
674 case CORTEX_M4_PARTNO: /* STM32F3x devices */
675 flash_size_reg = 0x1FFFF7CC;
678 LOG_ERROR("Cannot identify target as a stm32x");
682 int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
683 if (retval != ERROR_OK)
689 static int stm32x_probe(struct flash_bank *bank)
691 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
692 uint16_t flash_size_in_kb;
693 uint16_t max_flash_size_in_kb;
694 uint32_t dbgmcu_idcode;
696 uint32_t base_address = 0x08000000;
698 stm32x_info->probed = false;
699 stm32x_info->register_base = FLASH_REG_BASE_B0;
700 stm32x_info->user_data_offset = 10;
701 stm32x_info->option_offset = 0;
703 /* default factory read protection level 0 */
704 stm32x_info->default_rdp = 0xA5;
706 /* read stm32 device id register */
707 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
708 if (retval != ERROR_OK)
711 LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
713 uint16_t device_id = dbgmcu_idcode & 0xfff;
714 uint16_t rev_id = dbgmcu_idcode >> 16;
716 /* set page size, protection granularity and max flash size depending on family */
718 case 0x440: /* stm32f05x */
720 stm32x_info->ppage_size = 4;
721 max_flash_size_in_kb = 64;
722 stm32x_info->user_data_offset = 16;
723 stm32x_info->option_offset = 6;
724 stm32x_info->default_rdp = 0xAA;
725 stm32x_info->can_load_options = true;
727 case 0x444: /* stm32f03x */
728 case 0x445: /* stm32f04x */
730 stm32x_info->ppage_size = 4;
731 max_flash_size_in_kb = 32;
732 stm32x_info->user_data_offset = 16;
733 stm32x_info->option_offset = 6;
734 stm32x_info->default_rdp = 0xAA;
735 stm32x_info->can_load_options = true;
737 case 0x448: /* stm32f07x */
739 stm32x_info->ppage_size = 4;
740 max_flash_size_in_kb = 128;
741 stm32x_info->user_data_offset = 16;
742 stm32x_info->option_offset = 6;
743 stm32x_info->default_rdp = 0xAA;
744 stm32x_info->can_load_options = true;
746 case 0x442: /* stm32f09x */
748 stm32x_info->ppage_size = 4;
749 max_flash_size_in_kb = 256;
750 stm32x_info->user_data_offset = 16;
751 stm32x_info->option_offset = 6;
752 stm32x_info->default_rdp = 0xAA;
753 stm32x_info->can_load_options = true;
755 case 0x410: /* stm32f1x medium-density */
757 stm32x_info->ppage_size = 4;
758 max_flash_size_in_kb = 128;
759 /* GigaDevice GD32F1x0 & GD32F3x0 series devices share DEV_ID
760 with STM32F101/2/3 medium-density line,
761 however they use a REV_ID different from any STM32 device.
762 The main difference is another offset of user option bits
763 (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
764 (FLASH_OBR/FMC_OBSTAT 0x4002201C).
765 This caused problems e.g. during flash block programming
766 because of unexpected active hardware watchog. */
768 case 0x1303: /* gd32f1x0 */
769 stm32x_info->user_data_offset = 16;
770 stm32x_info->option_offset = 6;
771 max_flash_size_in_kb = 64;
773 case 0x1704: /* gd32f3x0 */
774 stm32x_info->user_data_offset = 16;
775 stm32x_info->option_offset = 6;
779 case 0x412: /* stm32f1x low-density */
781 stm32x_info->ppage_size = 4;
782 max_flash_size_in_kb = 32;
784 case 0x414: /* stm32f1x high-density */
786 stm32x_info->ppage_size = 2;
787 max_flash_size_in_kb = 512;
789 case 0x418: /* stm32f1x connectivity */
791 stm32x_info->ppage_size = 2;
792 max_flash_size_in_kb = 256;
794 case 0x430: /* stm32f1 XL-density (dual flash banks) */
796 stm32x_info->ppage_size = 2;
797 max_flash_size_in_kb = 1024;
798 stm32x_info->has_dual_banks = true;
800 case 0x420: /* stm32f100xx low- and medium-density value line */
802 stm32x_info->ppage_size = 4;
803 max_flash_size_in_kb = 128;
805 case 0x428: /* stm32f100xx high-density value line */
807 stm32x_info->ppage_size = 4;
808 max_flash_size_in_kb = 512;
810 case 0x422: /* stm32f302/3xb/c */
812 stm32x_info->ppage_size = 2;
813 max_flash_size_in_kb = 256;
814 stm32x_info->user_data_offset = 16;
815 stm32x_info->option_offset = 6;
816 stm32x_info->default_rdp = 0xAA;
817 stm32x_info->can_load_options = true;
819 case 0x446: /* stm32f303xD/E */
821 stm32x_info->ppage_size = 2;
822 max_flash_size_in_kb = 512;
823 stm32x_info->user_data_offset = 16;
824 stm32x_info->option_offset = 6;
825 stm32x_info->default_rdp = 0xAA;
826 stm32x_info->can_load_options = true;
828 case 0x432: /* stm32f37x */
830 stm32x_info->ppage_size = 2;
831 max_flash_size_in_kb = 256;
832 stm32x_info->user_data_offset = 16;
833 stm32x_info->option_offset = 6;
834 stm32x_info->default_rdp = 0xAA;
835 stm32x_info->can_load_options = true;
837 case 0x438: /* stm32f33x */
838 case 0x439: /* stm32f302x6/8 */
840 stm32x_info->ppage_size = 2;
841 max_flash_size_in_kb = 64;
842 stm32x_info->user_data_offset = 16;
843 stm32x_info->option_offset = 6;
844 stm32x_info->default_rdp = 0xAA;
845 stm32x_info->can_load_options = true;
848 LOG_WARNING("Cannot identify target as a STM32 family.");
852 /* get flash size from target. */
853 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
855 /* failed reading flash size or flash size invalid (early silicon),
856 * default to max target family */
857 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
858 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
859 max_flash_size_in_kb);
860 flash_size_in_kb = max_flash_size_in_kb;
863 if (stm32x_info->has_dual_banks) {
864 /* split reported size into matching bank */
865 if (bank->base != 0x08080000) {
866 /* bank 0 will be fixed 512k */
867 flash_size_in_kb = 512;
869 flash_size_in_kb -= 512;
870 /* bank1 also uses a register offset */
871 stm32x_info->register_base = FLASH_REG_BASE_B1;
872 base_address = 0x08080000;
876 /* if the user sets the size manually then ignore the probed value
877 * this allows us to work around devices that have a invalid flash size register value */
878 if (stm32x_info->user_bank_size) {
879 LOG_INFO("ignoring flash probed value, using configured bank size");
880 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
883 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
885 /* did we assign flash size? */
886 assert(flash_size_in_kb != 0xffff);
888 /* calculate numbers of pages */
889 int num_pages = flash_size_in_kb * 1024 / page_size;
891 /* check that calculation result makes sense */
892 assert(num_pages > 0);
895 bank->sectors = NULL;
897 free(bank->prot_blocks);
898 bank->prot_blocks = NULL;
900 bank->base = base_address;
901 bank->size = (num_pages * page_size);
903 bank->num_sectors = num_pages;
904 bank->sectors = alloc_block_array(0, page_size, num_pages);
908 /* calculate number of write protection blocks */
909 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
910 if (num_prot_blocks > 32)
911 num_prot_blocks = 32;
913 bank->num_prot_blocks = num_prot_blocks;
914 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
915 if (!bank->prot_blocks)
918 if (num_prot_blocks == 32)
919 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
921 stm32x_info->probed = true;
926 static int stm32x_auto_probe(struct flash_bank *bank)
928 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
929 if (stm32x_info->probed)
931 return stm32x_probe(bank);
935 COMMAND_HANDLER(stm32x_handle_part_id_command)
941 static const char *get_stm32f0_revision(uint16_t rev_id)
943 const char *rev_str = NULL;
956 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
958 uint32_t dbgmcu_idcode;
960 /* read stm32 device id register */
961 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
962 if (retval != ERROR_OK)
965 uint16_t device_id = dbgmcu_idcode & 0xfff;
966 uint16_t rev_id = dbgmcu_idcode >> 16;
967 const char *device_str;
968 const char *rev_str = NULL;
972 device_str = "STM32F10x (Medium Density)";
979 case 0x1303: /* gd32f1x0 */
980 device_str = "GD32F1x0";
983 case 0x1704: /* gd32f3x0 */
984 device_str = "GD32F3x0";
1002 device_str = "STM32F10x (Low Density)";
1012 device_str = "STM32F10x (High Density)";
1030 device_str = "STM32F10x (Connectivity)";
1044 device_str = "STM32F100 (Low/Medium Density)";
1058 device_str = "STM32F302xB/C";
1080 device_str = "STM32F100 (High Density)";
1094 device_str = "STM32F10x (XL Density)";
1104 device_str = "STM32F37x";
1118 device_str = "STM32F33x";
1128 device_str = "STM32F302x6/8";
1142 device_str = "STM32F03x";
1143 rev_str = get_stm32f0_revision(rev_id);
1147 device_str = "STM32F05x";
1148 rev_str = get_stm32f0_revision(rev_id);
1152 device_str = "STM32F04x";
1153 rev_str = get_stm32f0_revision(rev_id);
1157 device_str = "STM32F303xD/E";
1166 device_str = "STM32F07x";
1167 rev_str = get_stm32f0_revision(rev_id);
1171 device_str = "STM32F09x";
1172 rev_str = get_stm32f0_revision(rev_id);
1176 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1181 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1183 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1188 COMMAND_HANDLER(stm32x_handle_lock_command)
1190 struct target *target = NULL;
1191 struct stm32x_flash_bank *stm32x_info = NULL;
1194 return ERROR_COMMAND_SYNTAX_ERROR;
1196 struct flash_bank *bank;
1197 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1198 if (retval != ERROR_OK)
1201 stm32x_info = bank->driver_priv;
1203 target = bank->target;
1205 if (target->state != TARGET_HALTED) {
1206 LOG_ERROR("Target not halted");
1207 return ERROR_TARGET_NOT_HALTED;
1210 retval = stm32x_check_operation_supported(bank);
1211 if (retval != ERROR_OK)
1214 if (stm32x_erase_options(bank) != ERROR_OK) {
1215 command_print(CMD, "stm32x failed to erase options");
1219 /* set readout protection */
1220 stm32x_info->option_bytes.rdp = 0;
1222 if (stm32x_write_options(bank) != ERROR_OK) {
1223 command_print(CMD, "stm32x failed to lock device");
1227 command_print(CMD, "stm32x locked");
1232 COMMAND_HANDLER(stm32x_handle_unlock_command)
1234 struct target *target = NULL;
1237 return ERROR_COMMAND_SYNTAX_ERROR;
1239 struct flash_bank *bank;
1240 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1241 if (retval != ERROR_OK)
1244 target = bank->target;
1246 if (target->state != TARGET_HALTED) {
1247 LOG_ERROR("Target not halted");
1248 return ERROR_TARGET_NOT_HALTED;
1251 retval = stm32x_check_operation_supported(bank);
1252 if (retval != ERROR_OK)
1255 if (stm32x_erase_options(bank) != ERROR_OK) {
1256 command_print(CMD, "stm32x failed to erase options");
1260 if (stm32x_write_options(bank) != ERROR_OK) {
1261 command_print(CMD, "stm32x failed to unlock device");
1265 command_print(CMD, "stm32x unlocked.\n"
1266 "INFO: a reset or power cycle is required "
1267 "for the new settings to take effect.");
1272 COMMAND_HANDLER(stm32x_handle_options_read_command)
1274 uint32_t optionbyte, protection;
1275 struct target *target = NULL;
1276 struct stm32x_flash_bank *stm32x_info = NULL;
1279 return ERROR_COMMAND_SYNTAX_ERROR;
1281 struct flash_bank *bank;
1282 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1283 if (retval != ERROR_OK)
1286 stm32x_info = bank->driver_priv;
1288 target = bank->target;
1290 if (target->state != TARGET_HALTED) {
1291 LOG_ERROR("Target not halted");
1292 return ERROR_TARGET_NOT_HALTED;
1295 retval = stm32x_check_operation_supported(bank);
1296 if (retval != ERROR_OK)
1299 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1300 if (retval != ERROR_OK)
1303 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1305 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1306 if (retval != ERROR_OK)
1309 if (optionbyte & (1 << OPT_ERROR))
1310 command_print(CMD, "option byte complement error");
1312 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1313 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1315 command_print(CMD, "read protection: %s",
1316 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1318 /* user option bytes are offset depending on variant */
1319 optionbyte >>= stm32x_info->option_offset;
1321 command_print(CMD, "watchdog: %sware",
1322 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1324 command_print(CMD, "stop mode: %sreset generated upon entry",
1325 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1327 command_print(CMD, "standby mode: %sreset generated upon entry",
1328 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1330 if (stm32x_info->has_dual_banks)
1331 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1333 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1338 COMMAND_HANDLER(stm32x_handle_options_write_command)
1340 struct target *target = NULL;
1341 struct stm32x_flash_bank *stm32x_info = NULL;
1346 return ERROR_COMMAND_SYNTAX_ERROR;
1348 struct flash_bank *bank;
1349 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1350 if (retval != ERROR_OK)
1353 stm32x_info = bank->driver_priv;
1355 target = bank->target;
1357 if (target->state != TARGET_HALTED) {
1358 LOG_ERROR("Target not halted");
1359 return ERROR_TARGET_NOT_HALTED;
1362 retval = stm32x_check_operation_supported(bank);
1363 if (retval != ERROR_OK)
1366 retval = stm32x_read_options(bank);
1367 if (retval != ERROR_OK)
1370 /* start with current options */
1371 optionbyte = stm32x_info->option_bytes.user;
1372 useropt = stm32x_info->option_bytes.data;
1374 /* skip over flash bank */
1379 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1380 optionbyte |= (1 << 0);
1381 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1382 optionbyte &= ~(1 << 0);
1383 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1384 optionbyte |= (1 << 1);
1385 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1386 optionbyte &= ~(1 << 1);
1387 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1388 optionbyte |= (1 << 2);
1389 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1390 optionbyte &= ~(1 << 2);
1391 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1393 return ERROR_COMMAND_SYNTAX_ERROR;
1394 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1397 } else if (stm32x_info->has_dual_banks) {
1398 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1399 optionbyte |= (1 << 3);
1400 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1401 optionbyte &= ~(1 << 3);
1403 return ERROR_COMMAND_SYNTAX_ERROR;
1405 return ERROR_COMMAND_SYNTAX_ERROR;
1410 if (stm32x_erase_options(bank) != ERROR_OK) {
1411 command_print(CMD, "stm32x failed to erase options");
1415 stm32x_info->option_bytes.user = optionbyte;
1416 stm32x_info->option_bytes.data = useropt;
1418 if (stm32x_write_options(bank) != ERROR_OK) {
1419 command_print(CMD, "stm32x failed to write options");
1423 command_print(CMD, "stm32x write options complete.\n"
1424 "INFO: %spower cycle is required "
1425 "for the new settings to take effect.",
1426 stm32x_info->can_load_options
1427 ? "'stm32f1x options_load' command or " : "");
1432 COMMAND_HANDLER(stm32x_handle_options_load_command)
1435 return ERROR_COMMAND_SYNTAX_ERROR;
1437 struct flash_bank *bank;
1438 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1439 if (retval != ERROR_OK)
1442 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1444 if (!stm32x_info->can_load_options) {
1445 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1446 "required instead.");
1450 struct target *target = bank->target;
1452 if (target->state != TARGET_HALTED) {
1453 LOG_ERROR("Target not halted");
1454 return ERROR_TARGET_NOT_HALTED;
1457 retval = stm32x_check_operation_supported(bank);
1458 if (retval != ERROR_OK)
1461 /* unlock option flash registers */
1462 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1463 if (retval != ERROR_OK)
1465 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1466 if (retval != ERROR_OK)
1469 /* force re-load of option bytes - generates software reset */
1470 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1471 if (retval != ERROR_OK)
1477 static int stm32x_mass_erase(struct flash_bank *bank)
1479 struct target *target = bank->target;
1481 if (target->state != TARGET_HALTED) {
1482 LOG_ERROR("Target not halted");
1483 return ERROR_TARGET_NOT_HALTED;
1486 /* unlock option flash registers */
1487 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1488 if (retval != ERROR_OK)
1490 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1491 if (retval != ERROR_OK)
1494 /* mass erase flash memory */
1495 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1496 if (retval != ERROR_OK)
1498 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1499 FLASH_MER | FLASH_STRT);
1500 if (retval != ERROR_OK)
1503 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1504 if (retval != ERROR_OK)
1507 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1508 if (retval != ERROR_OK)
1514 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1517 return ERROR_COMMAND_SYNTAX_ERROR;
1519 struct flash_bank *bank;
1520 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1521 if (retval != ERROR_OK)
1524 retval = stm32x_mass_erase(bank);
1525 if (retval == ERROR_OK)
1526 command_print(CMD, "stm32x mass erase complete");
1528 command_print(CMD, "stm32x mass erase failed");
1533 static const struct command_registration stm32x_exec_command_handlers[] = {
1536 .handler = stm32x_handle_lock_command,
1537 .mode = COMMAND_EXEC,
1539 .help = "Lock entire flash device.",
1543 .handler = stm32x_handle_unlock_command,
1544 .mode = COMMAND_EXEC,
1546 .help = "Unlock entire protected flash device.",
1549 .name = "mass_erase",
1550 .handler = stm32x_handle_mass_erase_command,
1551 .mode = COMMAND_EXEC,
1553 .help = "Erase entire flash device.",
1556 .name = "options_read",
1557 .handler = stm32x_handle_options_read_command,
1558 .mode = COMMAND_EXEC,
1560 .help = "Read and display device option bytes.",
1563 .name = "options_write",
1564 .handler = stm32x_handle_options_write_command,
1565 .mode = COMMAND_EXEC,
1566 .usage = "bank_id ('SWWDG'|'HWWDG') "
1567 "('RSTSTNDBY'|'NORSTSTNDBY') "
1568 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1569 .help = "Replace bits in device option bytes.",
1572 .name = "options_load",
1573 .handler = stm32x_handle_options_load_command,
1574 .mode = COMMAND_EXEC,
1576 .help = "Force re-load of device option bytes.",
1578 COMMAND_REGISTRATION_DONE
1581 static const struct command_registration stm32x_command_handlers[] = {
1584 .mode = COMMAND_ANY,
1585 .help = "stm32f1x flash command group",
1587 .chain = stm32x_exec_command_handlers,
1589 COMMAND_REGISTRATION_DONE
1592 const struct flash_driver stm32f1x_flash = {
1594 .commands = stm32x_command_handlers,
1595 .flash_bank_command = stm32x_flash_bank_command,
1596 .erase = stm32x_erase,
1597 .protect = stm32x_protect,
1598 .write = stm32x_write,
1599 .read = default_flash_read,
1600 .probe = stm32x_probe,
1601 .auto_probe = stm32x_auto_probe,
1602 .erase_check = default_flash_blank_check,
1603 .protect_check = stm32x_protect_check,
1604 .info = get_stm32x_info,
1605 .free_driver_priv = default_flash_free_driver_priv,