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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "imp.h"
  30 #include <helper/binarybuffer.h>
  31 #include <target/algorithm.h>
  32 #include <target/cortex_m.h>
  33
  34 /* stm32x register locations */
  35
  36 #define FLASH_REG_BASE_B0 0x40022000
  37 #define FLASH_REG_BASE_B1 0x40022040
  38
  39 #define STM32_FLASH_ACR     0x00
  40 #define STM32_FLASH_KEYR    0x04
  41 #define STM32_FLASH_OPTKEYR 0x08
  42 #define STM32_FLASH_SR      0x0C
  43 #define STM32_FLASH_CR      0x10
  44 #define STM32_FLASH_AR      0x14
  45 #define STM32_FLASH_OBR     0x1C
  46 #define STM32_FLASH_WRPR    0x20
  47
  48 /* TODO: Check if code using these really should be hard coded to bank 0.
  49  * There are valid cases, on dual flash devices the protection of the
  50  * second bank is done on the bank0 reg's. */
  51 #define STM32_FLASH_ACR_B0     0x40022000
  52 #define STM32_FLASH_KEYR_B0    0x40022004
  53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  54 #define STM32_FLASH_SR_B0      0x4002200C
  55 #define STM32_FLASH_CR_B0      0x40022010
  56 #define STM32_FLASH_AR_B0      0x40022014
  57 #define STM32_FLASH_OBR_B0     0x4002201C
  58 #define STM32_FLASH_WRPR_B0    0x40022020
  59
  60 /* option byte location */
  61
  62 #define STM32_OB_RDP            0x1FFFF800
  63 #define STM32_OB_USER           0x1FFFF802
  64 #define STM32_OB_DATA0          0x1FFFF804
  65 #define STM32_OB_DATA1          0x1FFFF806
  66 #define STM32_OB_WRP0           0x1FFFF808
  67 #define STM32_OB_WRP1           0x1FFFF80A
  68 #define STM32_OB_WRP2           0x1FFFF80C
  69 #define STM32_OB_WRP3           0x1FFFF80E
  70
  71 /* FLASH_CR register bits */
  72
  73 #define FLASH_PG                        (1 << 0)
  74 #define FLASH_PER                       (1 << 1)
  75 #define FLASH_MER                       (1 << 2)
  76 #define FLASH_OPTPG                     (1 << 4)
  77 #define FLASH_OPTER                     (1 << 5)
  78 #define FLASH_STRT                      (1 << 6)
  79 #define FLASH_LOCK                      (1 << 7)
  80 #define FLASH_OPTWRE            (1 << 9)
  81 #define FLASH_OBL_LAUNCH        (1 << 13)       /* except stm32f1x series */
  82
  83 /* FLASH_SR register bits */
  84
  85 #define FLASH_BSY               (1 << 0)
  86 #define FLASH_PGERR             (1 << 2)
  87 #define FLASH_WRPRTERR  (1 << 4)
  88 #define FLASH_EOP               (1 << 5)
  89
  90 /* STM32_FLASH_OBR bit definitions (reading) */
  91
  92 #define OPT_ERROR               0
  93 #define OPT_READOUT             1
  94 #define OPT_RDWDGSW             2
  95 #define OPT_RDRSTSTOP   3
  96 #define OPT_RDRSTSTDBY  4
  97 #define OPT_BFB2                5       /* dual flash bank only */
  98
  99 /* register unlock keys */
 100
 101 #define KEY1                    0x45670123
 102 #define KEY2                    0xCDEF89AB
 103
 104 /* timeout values */
 105
 106 #define FLASH_WRITE_TIMEOUT 10
 107 #define FLASH_ERASE_TIMEOUT 100
 108
 109 struct stm32x_options {
 110         uint8_t rdp;
 111         uint8_t user;
 112         uint16_t data;
 113         uint32_t protection;
 114 };
 115
 116 struct stm32x_flash_bank {
 117         struct stm32x_options option_bytes;
 118         int ppage_size;
 119         bool probed;
 120
 121         bool has_dual_banks;
 122         /* used to access dual flash bank stm32xl */
 123         bool can_load_options;
 124         uint32_t register_base;
 125         uint8_t default_rdp;
 126         int user_data_offset;
 127         int option_offset;
 128         uint32_t user_bank_size;
 129 };
 130
 131 static int stm32x_mass_erase(struct flash_bank *bank);
 132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
 133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 134                 uint32_t address, uint32_t hwords_count);
 135
 136 /* flash bank stm32x <base> <size> 0 0 <target#>
 137  */
 138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 139 {
 140         struct stm32x_flash_bank *stm32x_info;
 141
 142         if (CMD_ARGC < 6)
 143                 return ERROR_COMMAND_SYNTAX_ERROR;
 144
 145         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 146
 147         bank->driver_priv = stm32x_info;
 148         stm32x_info->probed = false;
 149         stm32x_info->has_dual_banks = false;
 150         stm32x_info->can_load_options = false;
 151         stm32x_info->register_base = FLASH_REG_BASE_B0;
 152         stm32x_info->user_bank_size = bank->size;
 153
 154         return ERROR_OK;
 155 }
 156
 157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 158 {
 159         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 160         return reg + stm32x_info->register_base;
 161 }
 162
 163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 164 {
 165         struct target *target = bank->target;
 166         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 167 }
 168
 169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 170 {
 171         struct target *target = bank->target;
 172         uint32_t status;
 173         int retval = ERROR_OK;
 174
 175         /* wait for busy to clear */
 176         for (;;) {
 177                 retval = stm32x_get_flash_status(bank, &status);
 178                 if (retval != ERROR_OK)
 179                         return retval;
 180                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 181                 if ((status & FLASH_BSY) == 0)
 182                         break;
 183                 if (timeout-- <= 0) {
 184                         LOG_ERROR("timed out waiting for flash");
 185                         return ERROR_FAIL;
 186                 }
 187                 alive_sleep(1);
 188         }
 189
 190         if (status & FLASH_WRPRTERR) {
 191                 LOG_ERROR("stm32x device protected");
 192                 retval = ERROR_FAIL;
 193         }
 194
 195         if (status & FLASH_PGERR) {
 196                 LOG_ERROR("stm32x device programming failed");
 197                 retval = ERROR_FAIL;
 198         }
 199
 200         /* Clear but report errors */
 201         if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
 202                 /* If this operation fails, we ignore it and report the original
 203                  * retval
 204                  */
 205                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 206                                 FLASH_WRPRTERR | FLASH_PGERR);
 207         }
 208         return retval;
 209 }
 210
 211 static int stm32x_check_operation_supported(struct flash_bank *bank)
 212 {
 213         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 214
 215         /* if we have a dual flash bank device then
 216          * we need to perform option byte stuff on bank0 only */
 217         if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
 218                 LOG_ERROR("Option byte operations must use bank 0");
 219                 return ERROR_FLASH_OPERATION_FAILED;
 220         }
 221
 222         return ERROR_OK;
 223 }
 224
 225 static int stm32x_read_options(struct flash_bank *bank)
 226 {
 227         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 228         struct target *target = bank->target;
 229         uint32_t option_bytes;
 230         int retval;
 231
 232         /* read user and read protection option bytes, user data option bytes */
 233         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
 234         if (retval != ERROR_OK)
 235                 return retval;
 236
 237         stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
 238         stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
 239         stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
 240
 241         /* read write protection option bytes */
 242         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
 243         if (retval != ERROR_OK)
 244                 return retval;
 245
 246         return ERROR_OK;
 247 }
 248
 249 static int stm32x_erase_options(struct flash_bank *bank)
 250 {
 251         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 252         struct target *target = bank->target;
 253
 254         /* read current options */
 255         stm32x_read_options(bank);
 256
 257         /* unlock flash registers */
 258         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 259         if (retval != ERROR_OK)
 260                 return retval;
 261
 262         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 263         if (retval != ERROR_OK)
 264                 return retval;
 265
 266         /* unlock option flash registers */
 267         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 268         if (retval != ERROR_OK)
 269                 return retval;
 270         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 271         if (retval != ERROR_OK)
 272                 return retval;
 273
 274         /* erase option bytes */
 275         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 276         if (retval != ERROR_OK)
 277                 return retval;
 278         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 279         if (retval != ERROR_OK)
 280                 return retval;
 281
 282         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 283         if (retval != ERROR_OK)
 284                 return retval;
 285
 286         /* clear read protection option byte
 287          * this will also force a device unlock if set */
 288         stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
 289
 290         return ERROR_OK;
 291 }
 292
 293 static int stm32x_write_options(struct flash_bank *bank)
 294 {
 295         struct stm32x_flash_bank *stm32x_info = NULL;
 296         struct target *target = bank->target;
 297
 298         stm32x_info = bank->driver_priv;
 299
 300         /* unlock flash registers */
 301         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 302         if (retval != ERROR_OK)
 303                 return retval;
 304         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 305         if (retval != ERROR_OK)
 306                 return retval;
 307
 308         /* unlock option flash registers */
 309         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 310         if (retval != ERROR_OK)
 311                 return retval;
 312         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 313         if (retval != ERROR_OK)
 314                 return retval;
 315
 316         /* program option bytes */
 317         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 318         if (retval != ERROR_OK)
 319                 return retval;
 320
 321         uint8_t opt_bytes[16];
 322
 323         target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
 324         target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
 325         target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
 326         target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
 327         target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
 328         target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
 329         target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
 330         target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
 331
 332         /* Block write is preferred in favour of operation with ancient ST-Link
 333          * firmwares without 16-bit memory access. See
 334          * 480: flash: stm32f1x: write option bytes using the loader
 335          * https://review.openocd.org/c/openocd/+/480
 336          */
 337         retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
 338         if (retval != ERROR_OK)
 339                 return retval;
 340
 341         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 342         if (retval != ERROR_OK)
 343                 return retval;
 344
 345         return ERROR_OK;
 346 }
 347
 348 static int stm32x_protect_check(struct flash_bank *bank)
 349 {
 350         struct target *target = bank->target;
 351         uint32_t protection;
 352
 353         int retval = stm32x_check_operation_supported(bank);
 354         if (retval != ERROR_OK)
 355                 return retval;
 356
 357         /* medium density - each bit refers to a 4 sector protection block
 358          * high density - each bit refers to a 2 sector protection block
 359          * bit 31 refers to all remaining sectors in a bank */
 360         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 361         if (retval != ERROR_OK)
 362                 return retval;
 363
 364         for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
 365                 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
 366
 367         return ERROR_OK;
 368 }
 369
 370 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
 371                 unsigned int last)
 372 {
 373         struct target *target = bank->target;
 374
 375         if (bank->target->state != TARGET_HALTED) {
 376                 LOG_ERROR("Target not halted");
 377                 return ERROR_TARGET_NOT_HALTED;
 378         }
 379
 380         if ((first == 0) && (last == (bank->num_sectors - 1)))
 381                 return stm32x_mass_erase(bank);
 382
 383         /* unlock flash registers */
 384         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 385         if (retval != ERROR_OK)
 386                 return retval;
 387         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 388         if (retval != ERROR_OK)
 389                 return retval;
 390
 391         for (unsigned int i = first; i <= last; i++) {
 392                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 393                 if (retval != ERROR_OK)
 394                         return retval;
 395                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 396                                 bank->base + bank->sectors[i].offset);
 397                 if (retval != ERROR_OK)
 398                         return retval;
 399                 retval = target_write_u32(target,
 400                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 401                 if (retval != ERROR_OK)
 402                         return retval;
 403
 404                 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 405                 if (retval != ERROR_OK)
 406                         return retval;
 407         }
 408
 409         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 410         if (retval != ERROR_OK)
 411                 return retval;
 412
 413         return ERROR_OK;
 414 }
 415
 416 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 417                 unsigned int last)
 418 {
 419         struct target *target = bank->target;
 420         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 421
 422         if (target->state != TARGET_HALTED) {
 423                 LOG_ERROR("Target not halted");
 424                 return ERROR_TARGET_NOT_HALTED;
 425         }
 426
 427         int retval = stm32x_check_operation_supported(bank);
 428         if (retval != ERROR_OK)
 429                 return retval;
 430
 431         retval = stm32x_erase_options(bank);
 432         if (retval != ERROR_OK) {
 433                 LOG_ERROR("stm32x failed to erase options");
 434                 return retval;
 435         }
 436
 437         for (unsigned int i = first; i <= last; i++) {
 438                 if (set)
 439                         stm32x_info->option_bytes.protection &= ~(1 << i);
 440                 else
 441                         stm32x_info->option_bytes.protection |= (1 << i);
 442         }
 443
 444         return stm32x_write_options(bank);
 445 }
 446
 447 static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buffer,
 448                 uint32_t address, uint32_t hwords_count)
 449 {
 450         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 451         struct target *target = bank->target;
 452         uint32_t buffer_size = 16384;
 453         struct working_area *write_algorithm;
 454         struct working_area *source;
 455         struct reg_param reg_params[5];
 456         struct armv7m_algorithm armv7m_info;
 457         int retval = ERROR_OK;
 458
 459         static const uint8_t stm32x_flash_write_code[] = {
 460 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
 461         };
 462
 463         /* flash write code */
 464         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 465                         &write_algorithm) != ERROR_OK) {
 466                 LOG_WARNING("no working area available, can't do block memory writes");
 467                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 468         }
 469
 470         retval = target_write_buffer(target, write_algorithm->address,
 471                         sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
 472         if (retval != ERROR_OK) {
 473                 target_free_working_area(target, write_algorithm);
 474                 return retval;
 475         }
 476
 477         /* memory buffer */
 478         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 479                 buffer_size /= 2;
 480                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 481                 if (buffer_size <= 256) {
 482                         /* we already allocated the writing code, but failed to get a
 483                          * buffer, free the algorithm */
 484                         target_free_working_area(target, write_algorithm);
 485
 486                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 487                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 488                 }
 489         }
 490
 491         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 492         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 493         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 494         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 495         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 496
 497         buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
 498         buf_set_u32(reg_params[1].value, 0, 32, hwords_count);
 499         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 500         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 501         buf_set_u32(reg_params[4].value, 0, 32, address);
 502
 503         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 504         armv7m_info.core_mode = ARM_MODE_THREAD;
 505
 506         retval = target_run_flash_async_algorithm(target, buffer, hwords_count, 2,
 507                         0, NULL,
 508                         5, reg_params,
 509                         source->address, source->size,
 510                         write_algorithm->address, 0,
 511                         &armv7m_info);
 512
 513         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 514                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 515                                 buf_get_u32(reg_params[4].value, 0, 32));
 516
 517                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
 518                         LOG_ERROR("flash memory not erased before writing");
 519                         /* Clear but report errors */
 520                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
 521                 }
 522
 523                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
 524                         LOG_ERROR("flash memory write protected");
 525                         /* Clear but report errors */
 526                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
 527                 }
 528         }
 529
 530         target_free_working_area(target, source);
 531         target_free_working_area(target, write_algorithm);
 532
 533         destroy_reg_param(&reg_params[0]);
 534         destroy_reg_param(&reg_params[1]);
 535         destroy_reg_param(&reg_params[2]);
 536         destroy_reg_param(&reg_params[3]);
 537         destroy_reg_param(&reg_params[4]);
 538
 539         return retval;
 540 }
 541
 542 /** Writes a block to flash either using target algorithm
 543  *  or use fallback, host controlled halfword-by-halfword access.
 544  *  Flash controller must be unlocked before this call.
 545  */
 546 static int stm32x_write_block(struct flash_bank *bank,
 547                 const uint8_t *buffer, uint32_t address, uint32_t hwords_count)
 548 {
 549         struct target *target = bank->target;
 550
 551         /* try using a block write - on ARM architecture or... */
 552         int retval = stm32x_write_block_async(bank, buffer, address, hwords_count);
 553
 554         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 555                 /* if block write failed (no sufficient working area),
 556                  * we use normal (slow) single halfword accesses */
 557                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 558
 559                 while (hwords_count > 0) {
 560                         retval = target_write_memory(target, address, 2, 1, buffer);
 561                         if (retval != ERROR_OK)
 562                                 return retval;
 563
 564                         retval = stm32x_wait_status_busy(bank, 5);
 565                         if (retval != ERROR_OK)
 566                                 return retval;
 567
 568                         hwords_count--;
 569                         buffer += 2;
 570                         address += 2;
 571                 }
 572         }
 573         return retval;
 574 }
 575
 576 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 577                 uint32_t offset, uint32_t count)
 578 {
 579         struct target *target = bank->target;
 580         uint8_t *new_buffer = NULL;
 581
 582         if (bank->target->state != TARGET_HALTED) {
 583                 LOG_ERROR("Target not halted");
 584                 return ERROR_TARGET_NOT_HALTED;
 585         }
 586
 587         if (offset & 0x1) {
 588                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 589                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 590         }
 591
 592         /* If there's an odd number of bytes, the data has to be padded. Duplicate
 593          * the buffer and use the normal code path with a single block write since
 594          * it's probably cheaper than to special case the last odd write using
 595          * discrete accesses. */
 596         if (count & 1) {
 597                 new_buffer = malloc(count + 1);
 598                 if (!new_buffer) {
 599                         LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
 600                         return ERROR_FAIL;
 601                 }
 602                 LOG_INFO("odd number of bytes to write, padding with 0xff");
 603                 buffer = memcpy(new_buffer, buffer, count);
 604                 new_buffer[count++] = 0xff;
 605         }
 606
 607         int retval, retval2;
 608
 609         /* unlock flash registers */
 610         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 611         if (retval != ERROR_OK)
 612                 goto cleanup;
 613         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 614         if (retval != ERROR_OK)
 615                 goto reset_pg_and_lock;
 616
 617         /* enable flash programming */
 618         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 619         if (retval != ERROR_OK)
 620                 goto reset_pg_and_lock;
 621
 622         /* write to flash */
 623         retval = stm32x_write_block(bank, buffer, bank->base + offset, count / 2);
 624
 625 reset_pg_and_lock:
 626         retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 627         if (retval == ERROR_OK)
 628                 retval = retval2;
 629
 630 cleanup:
 631         free(new_buffer);
 632         return retval;
 633 }
 634
 635 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 636 {
 637         struct target *target = bank->target;
 638         uint32_t device_id_register = 0;
 639
 640         if (!target_was_examined(target)) {
 641                 LOG_ERROR("Target not examined yet");
 642                 return ERROR_TARGET_NOT_EXAMINED;
 643         }
 644
 645         switch (cortex_m_get_partno_safe(target)) {
 646         case CORTEX_M0_PARTNO: /* STM32F0x devices */
 647                 device_id_register = 0x40015800;
 648                 break;
 649         case CORTEX_M3_PARTNO: /* STM32F1x devices */
 650                 device_id_register = 0xE0042000;
 651                 break;
 652         case CORTEX_M4_PARTNO: /* STM32F3x devices */
 653                 device_id_register = 0xE0042000;
 654                 break;
 655         case CORTEX_M23_PARTNO: /* GD32E23x devices */
 656                 device_id_register = 0x40015800;
 657                 break;
 658         default:
 659                 LOG_ERROR("Cannot identify target as a stm32x");
 660                 return ERROR_FAIL;
 661         }
 662
 663         /* read stm32 device id register */
 664         int retval = target_read_u32(target, device_id_register, device_id);
 665         if (retval != ERROR_OK)
 666                 return retval;
 667
 668         return retval;
 669 }
 670
 671 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
 672 {
 673         struct target *target = bank->target;
 674         uint32_t flash_size_reg;
 675
 676         if (!target_was_examined(target)) {
 677                 LOG_ERROR("Target not examined yet");
 678                 return ERROR_TARGET_NOT_EXAMINED;
 679         }
 680
 681         switch (cortex_m_get_partno_safe(target)) {
 682         case CORTEX_M0_PARTNO: /* STM32F0x devices */
 683                 flash_size_reg = 0x1FFFF7CC;
 684                 break;
 685         case CORTEX_M3_PARTNO: /* STM32F1x devices */
 686                 flash_size_reg = 0x1FFFF7E0;
 687                 break;
 688         case CORTEX_M4_PARTNO: /* STM32F3x devices */
 689                 flash_size_reg = 0x1FFFF7CC;
 690                 break;
 691         case CORTEX_M23_PARTNO: /* GD32E23x devices */
 692                 flash_size_reg = 0x1FFFF7E0;
 693                 break;
 694         default:
 695                 LOG_ERROR("Cannot identify target as a stm32x");
 696                 return ERROR_FAIL;
 697         }
 698
 699         int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
 700         if (retval != ERROR_OK)
 701                 return retval;
 702
 703         return retval;
 704 }
 705
 706 static int stm32x_probe(struct flash_bank *bank)
 707 {
 708         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 709         uint16_t flash_size_in_kb;
 710         uint16_t max_flash_size_in_kb;
 711         uint32_t dbgmcu_idcode;
 712         int page_size;
 713         uint32_t base_address = 0x08000000;
 714
 715         stm32x_info->probed = false;
 716         stm32x_info->register_base = FLASH_REG_BASE_B0;
 717         stm32x_info->user_data_offset = 10;
 718         stm32x_info->option_offset = 0;
 719
 720         /* default factory read protection level 0 */
 721         stm32x_info->default_rdp = 0xA5;
 722
 723         /* read stm32 device id register */
 724         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 725         if (retval != ERROR_OK)
 726                 return retval;
 727
 728         LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
 729
 730         uint16_t device_id = dbgmcu_idcode & 0xfff;
 731         uint16_t rev_id = dbgmcu_idcode >> 16;
 732
 733         /* set page size, protection granularity and max flash size depending on family */
 734         switch (device_id) {
 735         case 0x440: /* stm32f05x */
 736                 page_size = 1024;
 737                 stm32x_info->ppage_size = 4;
 738                 max_flash_size_in_kb = 64;
 739                 stm32x_info->user_data_offset = 16;
 740                 stm32x_info->option_offset = 6;
 741                 stm32x_info->default_rdp = 0xAA;
 742                 stm32x_info->can_load_options = true;
 743                 break;
 744         case 0x444: /* stm32f03x */
 745         case 0x445: /* stm32f04x */
 746                 page_size = 1024;
 747                 stm32x_info->ppage_size = 4;
 748                 max_flash_size_in_kb = 32;
 749                 stm32x_info->user_data_offset = 16;
 750                 stm32x_info->option_offset = 6;
 751                 stm32x_info->default_rdp = 0xAA;
 752                 stm32x_info->can_load_options = true;
 753                 break;
 754         case 0x448: /* stm32f07x */
 755                 page_size = 2048;
 756                 stm32x_info->ppage_size = 4;
 757                 max_flash_size_in_kb = 128;
 758                 stm32x_info->user_data_offset = 16;
 759                 stm32x_info->option_offset = 6;
 760                 stm32x_info->default_rdp = 0xAA;
 761                 stm32x_info->can_load_options = true;
 762                 break;
 763         case 0x442: /* stm32f09x */
 764                 page_size = 2048;
 765                 stm32x_info->ppage_size = 4;
 766                 max_flash_size_in_kb = 256;
 767                 stm32x_info->user_data_offset = 16;
 768                 stm32x_info->option_offset = 6;
 769                 stm32x_info->default_rdp = 0xAA;
 770                 stm32x_info->can_load_options = true;
 771                 break;
 772         case 0x410: /* stm32f1x medium-density */
 773                 page_size = 1024;
 774                 stm32x_info->ppage_size = 4;
 775                 max_flash_size_in_kb = 128;
 776                 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
 777                    share DEV_ID with STM32F101/2/3 medium-density line,
 778                    however they use a REV_ID different from any STM32 device.
 779                    The main difference is another offset of user option bits
 780                    (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
 781                    (FLASH_OBR/FMC_OBSTAT 0x4002201C).
 782                    This caused problems e.g. during flash block programming
 783                    because of unexpected active hardware watchog. */
 784                 switch (rev_id) {
 785                 case 0x1303: /* gd32f1x0 */
 786                         stm32x_info->user_data_offset = 16;
 787                         stm32x_info->option_offset = 6;
 788                         max_flash_size_in_kb = 64;
 789                         break;
 790                 case 0x1704: /* gd32f3x0 */
 791                         stm32x_info->user_data_offset = 16;
 792                         stm32x_info->option_offset = 6;
 793                         break;
 794                 case 0x1909: /* gd32e23x */
 795                         stm32x_info->user_data_offset = 16;
 796                         stm32x_info->option_offset = 6;
 797                         max_flash_size_in_kb = 64;
 798                         break;
 799                 }
 800                 break;
 801         case 0x412: /* stm32f1x low-density */
 802                 page_size = 1024;
 803                 stm32x_info->ppage_size = 4;
 804                 max_flash_size_in_kb = 32;
 805                 break;
 806         case 0x414: /* stm32f1x high-density */
 807                 page_size = 2048;
 808                 stm32x_info->ppage_size = 2;
 809                 max_flash_size_in_kb = 512;
 810                 break;
 811         case 0x418: /* stm32f1x connectivity */
 812                 page_size = 2048;
 813                 stm32x_info->ppage_size = 2;
 814                 max_flash_size_in_kb = 256;
 815                 break;
 816         case 0x430: /* stm32f1 XL-density (dual flash banks) */
 817                 page_size = 2048;
 818                 stm32x_info->ppage_size = 2;
 819                 max_flash_size_in_kb = 1024;
 820                 stm32x_info->has_dual_banks = true;
 821                 break;
 822         case 0x420: /* stm32f100xx low- and medium-density value line */
 823                 page_size = 1024;
 824                 stm32x_info->ppage_size = 4;
 825                 max_flash_size_in_kb = 128;
 826                 break;
 827         case 0x428: /* stm32f100xx high-density value line */
 828                 page_size = 2048;
 829                 stm32x_info->ppage_size = 4;
 830                 max_flash_size_in_kb = 512;
 831                 break;
 832         case 0x422: /* stm32f302/3xb/c */
 833                 page_size = 2048;
 834                 stm32x_info->ppage_size = 2;
 835                 max_flash_size_in_kb = 256;
 836                 stm32x_info->user_data_offset = 16;
 837                 stm32x_info->option_offset = 6;
 838                 stm32x_info->default_rdp = 0xAA;
 839                 stm32x_info->can_load_options = true;
 840                 break;
 841         case 0x446: /* stm32f303xD/E */
 842                 page_size = 2048;
 843                 stm32x_info->ppage_size = 2;
 844                 max_flash_size_in_kb = 512;
 845                 stm32x_info->user_data_offset = 16;
 846                 stm32x_info->option_offset = 6;
 847                 stm32x_info->default_rdp = 0xAA;
 848                 stm32x_info->can_load_options = true;
 849                 break;
 850         case 0x432: /* stm32f37x */
 851                 page_size = 2048;
 852                 stm32x_info->ppage_size = 2;
 853                 max_flash_size_in_kb = 256;
 854                 stm32x_info->user_data_offset = 16;
 855                 stm32x_info->option_offset = 6;
 856                 stm32x_info->default_rdp = 0xAA;
 857                 stm32x_info->can_load_options = true;
 858                 break;
 859         case 0x438: /* stm32f33x */
 860         case 0x439: /* stm32f302x6/8 */
 861                 page_size = 2048;
 862                 stm32x_info->ppage_size = 2;
 863                 max_flash_size_in_kb = 64;
 864                 stm32x_info->user_data_offset = 16;
 865                 stm32x_info->option_offset = 6;
 866                 stm32x_info->default_rdp = 0xAA;
 867                 stm32x_info->can_load_options = true;
 868                 break;
 869         default:
 870                 LOG_WARNING("Cannot identify target as a STM32 family.");
 871                 return ERROR_FAIL;
 872         }
 873
 874         /* get flash size from target. */
 875         retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
 876
 877         /* failed reading flash size or flash size invalid (early silicon),
 878          * default to max target family */
 879         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 880                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 881                         max_flash_size_in_kb);
 882                 flash_size_in_kb = max_flash_size_in_kb;
 883         }
 884
 885         if (stm32x_info->has_dual_banks) {
 886                 /* split reported size into matching bank */
 887                 if (bank->base != 0x08080000) {
 888                         /* bank 0 will be fixed 512k */
 889                         flash_size_in_kb = 512;
 890                 } else {
 891                         flash_size_in_kb -= 512;
 892                         /* bank1 also uses a register offset */
 893                         stm32x_info->register_base = FLASH_REG_BASE_B1;
 894                         base_address = 0x08080000;
 895                 }
 896         }
 897
 898         /* if the user sets the size manually then ignore the probed value
 899          * this allows us to work around devices that have a invalid flash size register value */
 900         if (stm32x_info->user_bank_size) {
 901                 LOG_INFO("ignoring flash probed value, using configured bank size");
 902                 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
 903         }
 904
 905         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 906
 907         /* did we assign flash size? */
 908         assert(flash_size_in_kb != 0xffff);
 909
 910         /* calculate numbers of pages */
 911         int num_pages = flash_size_in_kb * 1024 / page_size;
 912
 913         /* check that calculation result makes sense */
 914         assert(num_pages > 0);
 915
 916         free(bank->sectors);
 917         bank->sectors = NULL;
 918
 919         free(bank->prot_blocks);
 920         bank->prot_blocks = NULL;
 921
 922         bank->base = base_address;
 923         bank->size = (num_pages * page_size);
 924
 925         bank->num_sectors = num_pages;
 926         bank->sectors = alloc_block_array(0, page_size, num_pages);
 927         if (!bank->sectors)
 928                 return ERROR_FAIL;
 929
 930         /* calculate number of write protection blocks */
 931         int num_prot_blocks = num_pages / stm32x_info->ppage_size;
 932         if (num_prot_blocks > 32)
 933                 num_prot_blocks = 32;
 934
 935         bank->num_prot_blocks = num_prot_blocks;
 936         bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
 937         if (!bank->prot_blocks)
 938                 return ERROR_FAIL;
 939
 940         if (num_prot_blocks == 32)
 941                 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
 942
 943         stm32x_info->probed = true;
 944
 945         return ERROR_OK;
 946 }
 947
 948 static int stm32x_auto_probe(struct flash_bank *bank)
 949 {
 950         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 951         if (stm32x_info->probed)
 952                 return ERROR_OK;
 953         return stm32x_probe(bank);
 954 }
 955
 956 #if 0
 957 COMMAND_HANDLER(stm32x_handle_part_id_command)
 958 {
 959         return ERROR_OK;
 960 }
 961 #endif
 962
 963 static const char *get_stm32f0_revision(uint16_t rev_id)
 964 {
 965         const char *rev_str = NULL;
 966
 967         switch (rev_id) {
 968         case 0x1000:
 969                 rev_str = "1.0";
 970                 break;
 971         case 0x2000:
 972                 rev_str = "2.0";
 973                 break;
 974         }
 975         return rev_str;
 976 }
 977
 978 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
 979 {
 980         uint32_t dbgmcu_idcode;
 981
 982         /* read stm32 device id register */
 983         int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
 984         if (retval != ERROR_OK)
 985                 return retval;
 986
 987         uint16_t device_id = dbgmcu_idcode & 0xfff;
 988         uint16_t rev_id = dbgmcu_idcode >> 16;
 989         const char *device_str;
 990         const char *rev_str = NULL;
 991
 992         switch (device_id) {
 993         case 0x410:
 994                 device_str = "STM32F10x (Medium Density)";
 995
 996                 switch (rev_id) {
 997                 case 0x0000:
 998                         rev_str = "A";
 999                         break;
1000
1001                 case 0x1303: /* gd32f1x0 */
1002                         device_str = "GD32F1x0";
1003                         break;
1004
1005                 case 0x1704: /* gd32f3x0 */
1006                         device_str = "GD32F3x0";
1007                         break;
1008
1009                 case 0x1909: /* gd32e23x */
1010                         device_str = "GD32E23x";
1011                         break;
1012
1013                 case 0x2000:
1014                         rev_str = "B";
1015                         break;
1016
1017                 case 0x2001:
1018                         rev_str = "Z";
1019                         break;
1020
1021                 case 0x2003:
1022                         rev_str = "Y";
1023                         break;
1024                 }
1025                 break;
1026
1027         case 0x412:
1028                 device_str = "STM32F10x (Low Density)";
1029
1030                 switch (rev_id) {
1031                 case 0x1000:
1032                         rev_str = "A";
1033                         break;
1034                 }
1035                 break;
1036
1037         case 0x414:
1038                 device_str = "STM32F10x (High Density)";
1039
1040                 switch (rev_id) {
1041                 case 0x1000:
1042                         rev_str = "A";
1043                         break;
1044
1045                 case 0x1001:
1046                         rev_str = "Z";
1047                         break;
1048
1049                 case 0x1003:
1050                         rev_str = "Y";
1051                         break;
1052                 }
1053                 break;
1054
1055         case 0x418:
1056                 device_str = "STM32F10x (Connectivity)";
1057
1058                 switch (rev_id) {
1059                 case 0x1000:
1060                         rev_str = "A";
1061                         break;
1062
1063                 case 0x1001:
1064                         rev_str = "Z";
1065                         break;
1066                 }
1067                 break;
1068
1069         case 0x420:
1070                 device_str = "STM32F100 (Low/Medium Density)";
1071
1072                 switch (rev_id) {
1073                 case 0x1000:
1074                         rev_str = "A";
1075                         break;
1076
1077                 case 0x1001:
1078                         rev_str = "Z";
1079                         break;
1080                 }
1081                 break;
1082
1083         case 0x422:
1084                 device_str = "STM32F302xB/C";
1085
1086                 switch (rev_id) {
1087                 case 0x1000:
1088                         rev_str = "A";
1089                         break;
1090
1091                 case 0x1001:
1092                         rev_str = "Z";
1093                         break;
1094
1095                 case 0x1003:
1096                         rev_str = "Y";
1097                         break;
1098
1099                 case 0x2000:
1100                         rev_str = "B";
1101                         break;
1102                 }
1103                 break;
1104
1105         case 0x428:
1106                 device_str = "STM32F100 (High Density)";
1107
1108                 switch (rev_id) {
1109                 case 0x1000:
1110                         rev_str = "A";
1111                         break;
1112
1113                 case 0x1001:
1114                         rev_str = "Z";
1115                         break;
1116                 }
1117                 break;
1118
1119         case 0x430:
1120                 device_str = "STM32F10x (XL Density)";
1121
1122                 switch (rev_id) {
1123                 case 0x1000:
1124                         rev_str = "A";
1125                         break;
1126                 }
1127                 break;
1128
1129         case 0x432:
1130                 device_str = "STM32F37x";
1131
1132                 switch (rev_id) {
1133                 case 0x1000:
1134                         rev_str = "A";
1135                         break;
1136
1137                 case 0x2000:
1138                         rev_str = "B";
1139                         break;
1140                 }
1141                 break;
1142
1143         case 0x438:
1144                 device_str = "STM32F33x";
1145
1146                 switch (rev_id) {
1147                 case 0x1000:
1148                         rev_str = "A";
1149                         break;
1150                 }
1151                 break;
1152
1153         case 0x439:
1154                 device_str = "STM32F302x6/8";
1155
1156                 switch (rev_id) {
1157                 case 0x1000:
1158                         rev_str = "A";
1159                         break;
1160
1161                 case 0x1001:
1162                         rev_str = "Z";
1163                         break;
1164                 }
1165                 break;
1166
1167         case 0x444:
1168                 device_str = "STM32F03x";
1169                 rev_str = get_stm32f0_revision(rev_id);
1170                 break;
1171
1172         case 0x440:
1173                 device_str = "STM32F05x";
1174                 rev_str = get_stm32f0_revision(rev_id);
1175                 break;
1176
1177         case 0x445:
1178                 device_str = "STM32F04x";
1179                 rev_str = get_stm32f0_revision(rev_id);
1180                 break;
1181
1182         case 0x446:
1183                 device_str = "STM32F303xD/E";
1184                 switch (rev_id) {
1185                 case 0x1000:
1186                         rev_str = "A";
1187                         break;
1188                 }
1189                 break;
1190
1191         case 0x448:
1192                 device_str = "STM32F07x";
1193                 rev_str = get_stm32f0_revision(rev_id);
1194                 break;
1195
1196         case 0x442:
1197                 device_str = "STM32F09x";
1198                 rev_str = get_stm32f0_revision(rev_id);
1199                 break;
1200
1201         default:
1202                 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1203                 return ERROR_FAIL;
1204         }
1205
1206         if (rev_str)
1207                 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1208         else
1209                 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1210
1211         return ERROR_OK;
1212 }
1213
1214 COMMAND_HANDLER(stm32x_handle_lock_command)
1215 {
1216         struct target *target = NULL;
1217         struct stm32x_flash_bank *stm32x_info = NULL;
1218
1219         if (CMD_ARGC < 1)
1220                 return ERROR_COMMAND_SYNTAX_ERROR;
1221
1222         struct flash_bank *bank;
1223         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1224         if (retval != ERROR_OK)
1225                 return retval;
1226
1227         stm32x_info = bank->driver_priv;
1228
1229         target = bank->target;
1230
1231         if (target->state != TARGET_HALTED) {
1232                 LOG_ERROR("Target not halted");
1233                 return ERROR_TARGET_NOT_HALTED;
1234         }
1235
1236         retval = stm32x_check_operation_supported(bank);
1237         if (retval != ERROR_OK)
1238                 return retval;
1239
1240         if (stm32x_erase_options(bank) != ERROR_OK) {
1241                 command_print(CMD, "stm32x failed to erase options");
1242                 return ERROR_OK;
1243         }
1244
1245         /* set readout protection */
1246         stm32x_info->option_bytes.rdp = 0;
1247
1248         if (stm32x_write_options(bank) != ERROR_OK) {
1249                 command_print(CMD, "stm32x failed to lock device");
1250                 return ERROR_OK;
1251         }
1252
1253         command_print(CMD, "stm32x locked");
1254
1255         return ERROR_OK;
1256 }
1257
1258 COMMAND_HANDLER(stm32x_handle_unlock_command)
1259 {
1260         struct target *target = NULL;
1261
1262         if (CMD_ARGC < 1)
1263                 return ERROR_COMMAND_SYNTAX_ERROR;
1264
1265         struct flash_bank *bank;
1266         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1267         if (retval != ERROR_OK)
1268                 return retval;
1269
1270         target = bank->target;
1271
1272         if (target->state != TARGET_HALTED) {
1273                 LOG_ERROR("Target not halted");
1274                 return ERROR_TARGET_NOT_HALTED;
1275         }
1276
1277         retval = stm32x_check_operation_supported(bank);
1278         if (retval != ERROR_OK)
1279                 return retval;
1280
1281         if (stm32x_erase_options(bank) != ERROR_OK) {
1282                 command_print(CMD, "stm32x failed to erase options");
1283                 return ERROR_OK;
1284         }
1285
1286         if (stm32x_write_options(bank) != ERROR_OK) {
1287                 command_print(CMD, "stm32x failed to unlock device");
1288                 return ERROR_OK;
1289         }
1290
1291         command_print(CMD, "stm32x unlocked.\n"
1292                         "INFO: a reset or power cycle is required "
1293                         "for the new settings to take effect.");
1294
1295         return ERROR_OK;
1296 }
1297
1298 COMMAND_HANDLER(stm32x_handle_options_read_command)
1299 {
1300         uint32_t optionbyte, protection;
1301         struct target *target = NULL;
1302         struct stm32x_flash_bank *stm32x_info = NULL;
1303
1304         if (CMD_ARGC < 1)
1305                 return ERROR_COMMAND_SYNTAX_ERROR;
1306
1307         struct flash_bank *bank;
1308         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1309         if (retval != ERROR_OK)
1310                 return retval;
1311
1312         stm32x_info = bank->driver_priv;
1313
1314         target = bank->target;
1315
1316         if (target->state != TARGET_HALTED) {
1317                 LOG_ERROR("Target not halted");
1318                 return ERROR_TARGET_NOT_HALTED;
1319         }
1320
1321         retval = stm32x_check_operation_supported(bank);
1322         if (retval != ERROR_OK)
1323                 return retval;
1324
1325         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1326         if (retval != ERROR_OK)
1327                 return retval;
1328
1329         uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1330
1331         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1332         if (retval != ERROR_OK)
1333                 return retval;
1334
1335         if (optionbyte & (1 << OPT_ERROR))
1336                 command_print(CMD, "option byte complement error");
1337
1338         command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1339         command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1340
1341         command_print(CMD, "read protection: %s",
1342                                 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1343
1344         /* user option bytes are offset depending on variant */
1345         optionbyte >>= stm32x_info->option_offset;
1346
1347         command_print(CMD, "watchdog: %sware",
1348                                 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1349
1350         command_print(CMD, "stop mode: %sreset generated upon entry",
1351                                 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1352
1353         command_print(CMD, "standby mode: %sreset generated upon entry",
1354                                 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1355
1356         if (stm32x_info->has_dual_banks)
1357                 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1358
1359         command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1360
1361         return ERROR_OK;
1362 }
1363
1364 COMMAND_HANDLER(stm32x_handle_options_write_command)
1365 {
1366         struct target *target = NULL;
1367         struct stm32x_flash_bank *stm32x_info = NULL;
1368         uint8_t optionbyte;
1369         uint16_t useropt;
1370
1371         if (CMD_ARGC < 2)
1372                 return ERROR_COMMAND_SYNTAX_ERROR;
1373
1374         struct flash_bank *bank;
1375         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1376         if (retval != ERROR_OK)
1377                 return retval;
1378
1379         stm32x_info = bank->driver_priv;
1380
1381         target = bank->target;
1382
1383         if (target->state != TARGET_HALTED) {
1384                 LOG_ERROR("Target not halted");
1385                 return ERROR_TARGET_NOT_HALTED;
1386         }
1387
1388         retval = stm32x_check_operation_supported(bank);
1389         if (retval != ERROR_OK)
1390                 return retval;
1391
1392         retval = stm32x_read_options(bank);
1393         if (retval != ERROR_OK)
1394                 return retval;
1395
1396         /* start with current options */
1397         optionbyte = stm32x_info->option_bytes.user;
1398         useropt = stm32x_info->option_bytes.data;
1399
1400         /* skip over flash bank */
1401         CMD_ARGC--;
1402         CMD_ARGV++;
1403
1404         while (CMD_ARGC) {
1405                 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1406                         optionbyte |= (1 << 0);
1407                 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1408                         optionbyte &= ~(1 << 0);
1409                 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1410                         optionbyte |= (1 << 1);
1411                 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1412                         optionbyte &= ~(1 << 1);
1413                 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1414                         optionbyte |= (1 << 2);
1415                 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1416                         optionbyte &= ~(1 << 2);
1417                 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1418                         if (CMD_ARGC < 2)
1419                                 return ERROR_COMMAND_SYNTAX_ERROR;
1420                         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1421                         CMD_ARGC--;
1422                         CMD_ARGV++;
1423                 } else if (stm32x_info->has_dual_banks) {
1424                         if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1425                                 optionbyte |= (1 << 3);
1426                         else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1427                                 optionbyte &= ~(1 << 3);
1428                         else
1429                                 return ERROR_COMMAND_SYNTAX_ERROR;
1430                 } else
1431                         return ERROR_COMMAND_SYNTAX_ERROR;
1432                 CMD_ARGC--;
1433                 CMD_ARGV++;
1434         }
1435
1436         if (stm32x_erase_options(bank) != ERROR_OK) {
1437                 command_print(CMD, "stm32x failed to erase options");
1438                 return ERROR_OK;
1439         }
1440
1441         stm32x_info->option_bytes.user = optionbyte;
1442         stm32x_info->option_bytes.data = useropt;
1443
1444         if (stm32x_write_options(bank) != ERROR_OK) {
1445                 command_print(CMD, "stm32x failed to write options");
1446                 return ERROR_OK;
1447         }
1448
1449         command_print(CMD, "stm32x write options complete.\n"
1450                                 "INFO: %spower cycle is required "
1451                                 "for the new settings to take effect.",
1452                                 stm32x_info->can_load_options
1453                                         ? "'stm32f1x options_load' command or " : "");
1454
1455         return ERROR_OK;
1456 }
1457
1458 COMMAND_HANDLER(stm32x_handle_options_load_command)
1459 {
1460         if (CMD_ARGC < 1)
1461                 return ERROR_COMMAND_SYNTAX_ERROR;
1462
1463         struct flash_bank *bank;
1464         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1465         if (retval != ERROR_OK)
1466                 return retval;
1467
1468         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1469
1470         if (!stm32x_info->can_load_options) {
1471                 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1472                         "required instead.");
1473                 return ERROR_FAIL;
1474         }
1475
1476         struct target *target = bank->target;
1477
1478         if (target->state != TARGET_HALTED) {
1479                 LOG_ERROR("Target not halted");
1480                 return ERROR_TARGET_NOT_HALTED;
1481         }
1482
1483         retval = stm32x_check_operation_supported(bank);
1484         if (retval != ERROR_OK)
1485                 return retval;
1486
1487         /* unlock option flash registers */
1488         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1489         if (retval != ERROR_OK)
1490                 return retval;
1491         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1492         if (retval != ERROR_OK)
1493                 return retval;
1494
1495         /* force re-load of option bytes - generates software reset */
1496         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1497         if (retval != ERROR_OK)
1498                 return retval;
1499
1500         return ERROR_OK;
1501 }
1502
1503 static int stm32x_mass_erase(struct flash_bank *bank)
1504 {
1505         struct target *target = bank->target;
1506
1507         if (target->state != TARGET_HALTED) {
1508                 LOG_ERROR("Target not halted");
1509                 return ERROR_TARGET_NOT_HALTED;
1510         }
1511
1512         /* unlock option flash registers */
1513         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1514         if (retval != ERROR_OK)
1515                 return retval;
1516         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1517         if (retval != ERROR_OK)
1518                 return retval;
1519
1520         /* mass erase flash memory */
1521         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1522         if (retval != ERROR_OK)
1523                 return retval;
1524         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1525                         FLASH_MER | FLASH_STRT);
1526         if (retval != ERROR_OK)
1527                 return retval;
1528
1529         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1530         if (retval != ERROR_OK)
1531                 return retval;
1532
1533         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1534         if (retval != ERROR_OK)
1535                 return retval;
1536
1537         return ERROR_OK;
1538 }
1539
1540 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1541 {
1542         if (CMD_ARGC < 1)
1543                 return ERROR_COMMAND_SYNTAX_ERROR;
1544
1545         struct flash_bank *bank;
1546         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1547         if (retval != ERROR_OK)
1548                 return retval;
1549
1550         retval = stm32x_mass_erase(bank);
1551         if (retval == ERROR_OK)
1552                 command_print(CMD, "stm32x mass erase complete");
1553         else
1554                 command_print(CMD, "stm32x mass erase failed");
1555
1556         return retval;
1557 }
1558
1559 static const struct command_registration stm32f1x_exec_command_handlers[] = {
1560         {
1561                 .name = "lock",
1562                 .handler = stm32x_handle_lock_command,
1563                 .mode = COMMAND_EXEC,
1564                 .usage = "bank_id",
1565                 .help = "Lock entire flash device.",
1566         },
1567         {
1568                 .name = "unlock",
1569                 .handler = stm32x_handle_unlock_command,
1570                 .mode = COMMAND_EXEC,
1571                 .usage = "bank_id",
1572                 .help = "Unlock entire protected flash device.",
1573         },
1574         {
1575                 .name = "mass_erase",
1576                 .handler = stm32x_handle_mass_erase_command,
1577                 .mode = COMMAND_EXEC,
1578                 .usage = "bank_id",
1579                 .help = "Erase entire flash device.",
1580         },
1581         {
1582                 .name = "options_read",
1583                 .handler = stm32x_handle_options_read_command,
1584                 .mode = COMMAND_EXEC,
1585                 .usage = "bank_id",
1586                 .help = "Read and display device option bytes.",
1587         },
1588         {
1589                 .name = "options_write",
1590                 .handler = stm32x_handle_options_write_command,
1591                 .mode = COMMAND_EXEC,
1592                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1593                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1594                         "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1595                 .help = "Replace bits in device option bytes.",
1596         },
1597         {
1598                 .name = "options_load",
1599                 .handler = stm32x_handle_options_load_command,
1600                 .mode = COMMAND_EXEC,
1601                 .usage = "bank_id",
1602                 .help = "Force re-load of device option bytes.",
1603         },
1604         COMMAND_REGISTRATION_DONE
1605 };
1606
1607 static const struct command_registration stm32f1x_command_handlers[] = {
1608         {
1609                 .name = "stm32f1x",
1610                 .mode = COMMAND_ANY,
1611                 .help = "stm32f1x flash command group",
1612                 .usage = "",
1613                 .chain = stm32f1x_exec_command_handlers,
1614         },
1615         COMMAND_REGISTRATION_DONE
1616 };
1617
1618 const struct flash_driver stm32f1x_flash = {
1619         .name = "stm32f1x",
1620         .commands = stm32f1x_command_handlers,
1621         .flash_bank_command = stm32x_flash_bank_command,
1622         .erase = stm32x_erase,
1623         .protect = stm32x_protect,
1624         .write = stm32x_write,
1625         .read = default_flash_read,
1626         .probe = stm32x_probe,
1627         .auto_probe = stm32x_auto_probe,
1628         .erase_check = default_flash_blank_check,
1629         .protect_check = stm32x_protect_check,
1630         .info = get_stm32x_info,
1631         .free_driver_priv = default_flash_free_driver_priv,
1632 };