1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2018-2019 by Andreas Bolsch *
5 * andreas.bolsch@mni.thm.de *
7 * Copyright (C) 2012 by George Harris *
8 * george@luminairecoffee.com *
10 * Copyright (C) 2010 by Antonio Borneo *
11 * borneo.antonio@gmail.com *
12 ***************************************************************************/
14 #ifndef OPENOCD_FLASH_NOR_SPI_H
15 #define OPENOCD_FLASH_NOR_SPI_H
19 /* data structure to maintain flash ids from different vendors */
26 uint8_t chip_erase_cmd;
30 uint32_t size_in_bytes;
33 #define FLASH_ID(n, re, qr, pp, es, ces, id, psize, ssize, size) \
40 .chip_erase_cmd = ces, \
43 .sectorsize = ssize, \
44 .size_in_bytes = size, \
47 #define FRAM_ID(n, re, qr, pp, id, size) \
54 .chip_erase_cmd = 0x00, \
58 .size_in_bytes = size, \
61 extern const struct flash_device flash_devices[];
65 /* fields in SPI flash status register */
66 #define SPIFLASH_BSY 0
67 #define SPIFLASH_BSY_BIT (1 << SPIFLASH_BSY) /* WIP Bit of SPI SR */
69 #define SPIFLASH_WE_BIT (1 << SPIFLASH_WE) /* WEL Bit of SPI SR */
71 /* SPI Flash Commands */
72 #define SPIFLASH_READ_ID 0x9F /* Read Flash Identification */
73 #define SPIFLASH_READ_MID 0xAF /* Read Flash Identification, multi-io */
74 #define SPIFLASH_READ_STATUS 0x05 /* Read Status Register */
75 #define SPIFLASH_WRITE_ENABLE 0x06 /* Write Enable */
76 #define SPIFLASH_PAGE_PROGRAM 0x02 /* Page Program */
77 #define SPIFLASH_FAST_READ 0x0B /* Fast Read */
78 #define SPIFLASH_READ 0x03 /* Normal Read */
79 #define SPIFLASH_MASS_ERASE 0xC7 /* Mass Erase */
80 #define SPIFLASH_READ_SFDP 0x5A /* Read Serial Flash Discoverable Parameters */
82 #define SPIFLASH_DEF_PAGESIZE 256 /* default for non-page-oriented devices (FRAMs) */
84 #endif /* OPENOCD_FLASH_NOR_SPI_H */