1 /* SPDX-License-Identifier: GPL-2.0 */
3 * SH QSPI (Quad SPI) driver
4 * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
6 * Based on U-Boot SH QSPI driver
7 * Copyright (C) 2013 Renesas Electronics Corporation
8 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
17 #include <helper/binarybuffer.h>
18 #include <helper/bits.h>
19 #include <helper/time_support.h>
20 #include <helper/types.h>
21 #include <jtag/jtag.h>
22 #include <target/algorithm.h>
23 #include <target/arm.h>
24 #include <target/arm_opcodes.h>
25 #include <target/target.h>
27 /* SH QSPI register bit masks <REG>_<BIT> */
28 #define SPCR_MSTR 0x08
30 #define SPSR_SPRFF 0x80
31 #define SPSR_SPTEF 0x20
32 #define SPPCR_IO3FV 0x04
33 #define SPPCR_IO2FV 0x02
34 #define SPPCR_IO1FV 0x01
35 #define SPBDCR_RXBC0 BIT(0)
36 #define SPCMD_SCKDEN BIT(15)
37 #define SPCMD_SLNDEN BIT(14)
38 #define SPCMD_SPNDEN BIT(13)
39 #define SPCMD_SSLKP BIT(7)
40 #define SPCMD_BRDV0 BIT(2)
41 #define SPCMD_INIT1 (SPCMD_SCKDEN | SPCMD_SLNDEN | \
42 SPCMD_SPNDEN | SPCMD_SSLKP | \
44 #define SPCMD_INIT2 (SPCMD_SPNDEN | SPCMD_SSLKP | \
46 #define SPBFCR_TXRST BIT(7)
47 #define SPBFCR_RXRST BIT(6)
48 #define SPBFCR_TXTRG 0x30
49 #define SPBFCR_RXTRG 0x07
51 /* SH QSPI register set */
52 #define SH_QSPI_SPCR 0x00
53 #define SH_QSPI_SSLP 0x01
54 #define SH_QSPI_SPPCR 0x02
55 #define SH_QSPI_SPSR 0x03
56 #define SH_QSPI_SPDR 0x04
57 #define SH_QSPI_SPSCR 0x08
58 #define SH_QSPI_SPSSR 0x09
59 #define SH_QSPI_SPBR 0x0a
60 #define SH_QSPI_SPDCR 0x0b
61 #define SH_QSPI_SPCKD 0x0c
62 #define SH_QSPI_SSLND 0x0d
63 #define SH_QSPI_SPND 0x0e
64 #define SH_QSPI_DUMMY0 0x0f
65 #define SH_QSPI_SPCMD0 0x10
66 #define SH_QSPI_SPCMD1 0x12
67 #define SH_QSPI_SPCMD2 0x14
68 #define SH_QSPI_SPCMD3 0x16
69 #define SH_QSPI_SPBFCR 0x18
70 #define SH_QSPI_DUMMY1 0x19
71 #define SH_QSPI_SPBDCR 0x1a
72 #define SH_QSPI_SPBMUL0 0x1c
73 #define SH_QSPI_SPBMUL1 0x20
74 #define SH_QSPI_SPBMUL2 0x24
75 #define SH_QSPI_SPBMUL3 0x28
77 struct sh_qspi_flash_bank {
78 const struct flash_device *dev;
81 struct working_area *io_algorithm;
82 struct working_area *source;
83 unsigned int buffer_size;
86 struct sh_qspi_target {
92 static const struct sh_qspi_target target_devices[] = {
93 /* name, tap_idcode, io_base */
94 { "SH QSPI", 0x4ba00477, 0xe6b10000 },
98 static int sh_qspi_init(struct flash_bank *bank)
100 struct target *target = bank->target;
101 struct sh_qspi_flash_bank *info = bank->driver_priv;
105 /* QSPI initialize */
106 /* Set master mode only */
107 ret = target_write_u8(target, info->io_base + SH_QSPI_SPCR, SPCR_MSTR);
111 /* Set SSL signal level */
112 ret = target_write_u8(target, info->io_base + SH_QSPI_SSLP, 0x00);
116 /* Set MOSI signal value when transfer is in idle state */
117 ret = target_write_u8(target, info->io_base + SH_QSPI_SPPCR,
118 SPPCR_IO3FV | SPPCR_IO2FV);
122 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
123 ret = target_write_u8(target, info->io_base + SH_QSPI_SPBR, 0x01);
127 /* Disable Dummy Data Transmission */
128 ret = target_write_u8(target, info->io_base + SH_QSPI_SPDCR, 0x00);
132 /* Set clock delay value */
133 ret = target_write_u8(target, info->io_base + SH_QSPI_SPCKD, 0x00);
137 /* Set SSL negation delay value */
138 ret = target_write_u8(target, info->io_base + SH_QSPI_SSLND, 0x00);
142 /* Set next-access delay value */
143 ret = target_write_u8(target, info->io_base + SH_QSPI_SPND, 0x00);
147 /* Set equence command */
148 ret = target_write_u16(target, info->io_base + SH_QSPI_SPCMD0,
153 /* Reset transfer and receive Buffer */
154 ret = target_read_u8(target, info->io_base + SH_QSPI_SPBFCR, &val);
158 val |= SPBFCR_TXRST | SPBFCR_RXRST;
160 ret = target_write_u8(target, info->io_base + SH_QSPI_SPBFCR, val);
164 /* Clear transfer and receive Buffer control bit */
165 ret = target_read_u8(target, info->io_base + SH_QSPI_SPBFCR, &val);
169 val &= ~(SPBFCR_TXRST | SPBFCR_RXRST);
171 ret = target_write_u8(target, info->io_base + SH_QSPI_SPBFCR, val);
175 /* Set equence control method. Use equence0 only */
176 ret = target_write_u8(target, info->io_base + SH_QSPI_SPSCR, 0x00);
180 /* Enable SPI function */
181 ret = target_read_u8(target, info->io_base + SH_QSPI_SPCR, &val);
187 return target_write_u8(target, info->io_base + SH_QSPI_SPCR, val);
190 static int sh_qspi_cs_activate(struct flash_bank *bank)
192 struct target *target = bank->target;
193 struct sh_qspi_flash_bank *info = bank->driver_priv;
197 /* Set master mode only */
198 ret = target_write_u8(target, info->io_base + SH_QSPI_SPCR, SPCR_MSTR);
203 ret = target_write_u16(target, info->io_base + SH_QSPI_SPCMD0,
208 /* Reset transfer and receive Buffer */
209 ret = target_read_u8(target, info->io_base + SH_QSPI_SPBFCR, &val);
213 val |= SPBFCR_TXRST | SPBFCR_RXRST;
215 ret = target_write_u8(target, info->io_base + SH_QSPI_SPBFCR, val);
219 /* Clear transfer and receive Buffer control bit */
220 ret = target_read_u8(target, info->io_base + SH_QSPI_SPBFCR, &val);
224 val &= ~(SPBFCR_TXRST | SPBFCR_RXRST);
226 ret = target_write_u8(target, info->io_base + SH_QSPI_SPBFCR, val);
230 /* Set equence control method. Use equence0 only */
231 ret = target_write_u8(target, info->io_base + SH_QSPI_SPSCR, 0x00);
235 /* Enable SPI function */
236 ret = target_read_u8(target, info->io_base + SH_QSPI_SPCR, &val);
242 return target_write_u8(target, info->io_base + SH_QSPI_SPCR, val);
245 static int sh_qspi_cs_deactivate(struct flash_bank *bank)
247 struct target *target = bank->target;
248 struct sh_qspi_flash_bank *info = bank->driver_priv;
252 /* Disable SPI Function */
253 ret = target_read_u8(target, info->io_base + SH_QSPI_SPCR, &val);
259 return target_write_u8(target, info->io_base + SH_QSPI_SPCR, val);
262 static int sh_qspi_wait_for_bit(struct flash_bank *bank, uint8_t reg,
263 uint32_t mask, bool set,
264 unsigned long timeout)
266 struct target *target = bank->target;
267 struct sh_qspi_flash_bank *info = bank->driver_priv;
272 endtime = timeval_ms() + timeout;
274 ret = target_read_u8(target, info->io_base + reg, &val);
281 if ((val & mask) == mask)
285 } while (timeval_ms() < endtime);
287 LOG_ERROR("timeout");
288 return ERROR_TIMEOUT_REACHED;
291 static int sh_qspi_xfer_common(struct flash_bank *bank,
292 const uint8_t *dout, unsigned int outlen,
293 uint8_t *din, unsigned int inlen,
294 bool xfer_start, bool xfer_end)
296 struct target *target = bank->target;
297 struct sh_qspi_flash_bank *info = bank->driver_priv;
298 uint8_t tdata, rdata;
300 unsigned int nbyte = outlen + inlen;
304 ret = sh_qspi_cs_activate(bank);
308 ret = target_write_u32(target, info->io_base + SH_QSPI_SPBMUL0,
313 ret = target_read_u8(target, info->io_base + SH_QSPI_SPBFCR,
318 val &= ~(SPBFCR_TXTRG | SPBFCR_RXTRG);
320 ret = target_write_u8(target, info->io_base + SH_QSPI_SPBFCR,
327 ret = sh_qspi_wait_for_bit(bank, SH_QSPI_SPSR, SPSR_SPTEF,
332 tdata = outlen ? *dout++ : 0;
333 ret = target_write_u8(target, info->io_base + SH_QSPI_SPDR,
338 ret = sh_qspi_wait_for_bit(bank, SH_QSPI_SPSR, SPSR_SPRFF,
343 ret = target_read_u8(target, info->io_base + SH_QSPI_SPDR,
347 if (!outlen && inlen) {
359 return sh_qspi_cs_deactivate(bank);
364 /* Send "write enable" command to SPI flash chip. */
365 static int sh_qspi_write_enable(struct flash_bank *bank)
367 uint8_t dout = SPIFLASH_WRITE_ENABLE;
369 return sh_qspi_xfer_common(bank, &dout, 1, NULL, 0, 1, 1);
372 /* Read the status register of the external SPI flash chip. */
373 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
375 uint8_t dout = SPIFLASH_READ_STATUS;
379 ret = sh_qspi_xfer_common(bank, &dout, 1, &din, 1, 1, 1);
383 *status = din & 0xff;
388 /* check for WIP (write in progress) bit in status register */
390 static int wait_till_ready(struct flash_bank *bank, int timeout)
396 endtime = timeval_ms() + timeout;
398 /* read flash status register */
399 ret = read_status_reg(bank, &status);
403 if ((status & SPIFLASH_BSY_BIT) == 0)
406 } while (timeval_ms() < endtime);
408 LOG_ERROR("timeout");
409 return ERROR_TIMEOUT_REACHED;
412 static int sh_qspi_erase_sector(struct flash_bank *bank, int sector)
414 struct sh_qspi_flash_bank *info = bank->driver_priv;
415 bool addr4b = info->dev->size_in_bytes > (1UL << 24);
416 uint32_t address = (sector * info->dev->sectorsize) <<
419 info->dev->erase_cmd,
420 (address >> 24) & 0xff, (address >> 16) & 0xff,
421 (address >> 8) & 0xff, (address >> 0) & 0xff
423 unsigned int doutlen = addr4b ? 5 : 4;
427 ret = sh_qspi_write_enable(bank);
432 ret = sh_qspi_xfer_common(bank, dout, doutlen, NULL, 0, 1, 1);
436 /* Poll status register */
437 return wait_till_ready(bank, 3000);
440 static int sh_qspi_erase(struct flash_bank *bank, unsigned int first,
443 struct target *target = bank->target;
444 struct sh_qspi_flash_bank *info = bank->driver_priv;
445 int retval = ERROR_OK;
447 LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
449 if (target->state != TARGET_HALTED) {
450 LOG_ERROR("Target not halted");
451 return ERROR_TARGET_NOT_HALTED;
454 if ((last < first) || (last >= bank->num_sectors)) {
455 LOG_ERROR("Flash sector invalid");
456 return ERROR_FLASH_SECTOR_INVALID;
460 LOG_ERROR("Flash bank not probed");
461 return ERROR_FLASH_BANK_NOT_PROBED;
464 if (info->dev->erase_cmd == 0x00)
465 return ERROR_FLASH_OPER_UNSUPPORTED;
467 for (unsigned int sector = first; sector <= last; sector++) {
468 if (bank->sectors[sector].is_protected) {
469 LOG_ERROR("Flash sector %u protected", sector);
474 for (unsigned int sector = first; sector <= last; sector++) {
475 retval = sh_qspi_erase_sector(bank, sector);
476 if (retval != ERROR_OK)
484 static int sh_qspi_write(struct flash_bank *bank, const uint8_t *buffer,
485 uint32_t offset, uint32_t count)
487 struct target *target = bank->target;
488 struct sh_qspi_flash_bank *info = bank->driver_priv;
489 struct reg_param reg_params[4];
490 struct arm_algorithm arm_algo;
491 uint32_t io_base = (uint32_t)(info->io_base);
492 uint32_t src_base = (uint32_t)(info->source->address);
494 bool addr4b = !!(info->dev->size_in_bytes > (1UL << 24));
497 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
498 __func__, offset, count);
500 if (target->state != TARGET_HALTED) {
501 LOG_ERROR("Target not halted");
502 return ERROR_TARGET_NOT_HALTED;
505 if (offset + count > bank->size) {
506 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
507 count = bank->size - offset;
511 LOG_ERROR("sh_qspi_write_page: unaligned write address: %08" PRIx32,
516 /* Check sector protection */
517 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
518 /* Start offset in or before this sector? */
519 /* End offset in or behind this sector? */
520 struct flash_sector *bs = &bank->sectors[sector];
522 if ((offset < (bs->offset + bs->size)) &&
523 ((offset + count - 1) >= bs->offset) &&
525 LOG_ERROR("Flash sector %u protected", sector);
530 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
531 __func__, offset, count);
533 if (target->state != TARGET_HALTED) {
534 LOG_ERROR("Target not halted");
535 return ERROR_TARGET_NOT_HALTED;
538 if (offset + count > bank->size) {
539 LOG_WARNING("Reads past end of flash. Extra data discarded.");
540 count = bank->size - offset;
543 arm_algo.common_magic = ARM_COMMON_MAGIC;
544 arm_algo.core_mode = ARM_MODE_SVC;
545 arm_algo.core_state = ARM_STATE_ARM;
547 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
548 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
549 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
550 init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
553 chunk = (count > info->buffer_size) ?
554 info->buffer_size : count;
556 target_write_buffer(target, info->source->address,
559 buf_set_u32(reg_params[0].value, 0, 32, io_base);
560 buf_set_u32(reg_params[1].value, 0, 32, src_base);
561 buf_set_u32(reg_params[2].value, 0, 32,
562 (1 << 31) | (addr4b << 30) |
563 (info->dev->pprog_cmd << 20) | chunk);
564 buf_set_u32(reg_params[3].value, 0, 32, offset);
566 ret = target_run_algorithm(target, 0, NULL, 4, reg_params,
567 info->io_algorithm->address,
568 0, 10000, &arm_algo);
569 if (ret != ERROR_OK) {
570 LOG_ERROR("error executing SH QSPI flash IO algorithm");
571 ret = ERROR_FLASH_OPERATION_FAILED;
580 destroy_reg_param(®_params[0]);
581 destroy_reg_param(®_params[1]);
582 destroy_reg_param(®_params[2]);
583 destroy_reg_param(®_params[3]);
588 static int sh_qspi_read(struct flash_bank *bank, uint8_t *buffer,
589 uint32_t offset, uint32_t count)
591 struct target *target = bank->target;
592 struct sh_qspi_flash_bank *info = bank->driver_priv;
593 struct reg_param reg_params[4];
594 struct arm_algorithm arm_algo;
595 uint32_t io_base = (uint32_t)(info->io_base);
596 uint32_t src_base = (uint32_t)(info->source->address);
598 bool addr4b = !!(info->dev->size_in_bytes > (1UL << 24));
601 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
602 __func__, offset, count);
604 if (target->state != TARGET_HALTED) {
605 LOG_ERROR("Target not halted");
606 return ERROR_TARGET_NOT_HALTED;
609 if (offset + count > bank->size) {
610 LOG_WARNING("Reads past end of flash. Extra data discarded.");
611 count = bank->size - offset;
614 arm_algo.common_magic = ARM_COMMON_MAGIC;
615 arm_algo.core_mode = ARM_MODE_SVC;
616 arm_algo.core_state = ARM_STATE_ARM;
618 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
619 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
620 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
621 init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
624 chunk = (count > info->buffer_size) ?
625 info->buffer_size : count;
627 buf_set_u32(reg_params[0].value, 0, 32, io_base);
628 buf_set_u32(reg_params[1].value, 0, 32, src_base);
629 buf_set_u32(reg_params[2].value, 0, 32,
630 (addr4b << 30) | (info->dev->read_cmd << 20) |
632 buf_set_u32(reg_params[3].value, 0, 32, offset);
634 ret = target_run_algorithm(target, 0, NULL, 4, reg_params,
635 info->io_algorithm->address,
636 0, 10000, &arm_algo);
637 if (ret != ERROR_OK) {
638 LOG_ERROR("error executing SH QSPI flash IO algorithm");
639 ret = ERROR_FLASH_OPERATION_FAILED;
643 target_read_buffer(target, info->source->address,
651 destroy_reg_param(®_params[0]);
652 destroy_reg_param(®_params[1]);
653 destroy_reg_param(®_params[2]);
654 destroy_reg_param(®_params[3]);
659 /* Return ID of flash device */
660 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
662 struct target *target = bank->target;
663 uint8_t dout = SPIFLASH_READ_ID;
664 uint8_t din[3] = { 0, 0, 0 };
667 if (target->state != TARGET_HALTED) {
668 LOG_ERROR("Target not halted");
669 return ERROR_TARGET_NOT_HALTED;
672 ret = sh_qspi_xfer_common(bank, &dout, 1, din, 3, 1, 1);
676 *id = (din[0] << 0) | (din[1] << 8) | (din[2] << 16);
678 if (*id == 0xffffff) {
679 LOG_ERROR("No SPI flash found");
686 static int sh_qspi_protect(struct flash_bank *bank, int set,
687 unsigned int first, unsigned int last)
689 for (unsigned int sector = first; sector <= last; sector++)
690 bank->sectors[sector].is_protected = set;
695 static int sh_qspi_upload_helper(struct flash_bank *bank)
697 struct target *target = bank->target;
698 struct sh_qspi_flash_bank *info = bank->driver_priv;
700 /* see contrib/loaders/flash/sh_qspi.s for src */
701 static const uint8_t sh_qspi_io_code[] = {
702 #include "../../../contrib/loaders/flash/sh_qspi/sh_qspi.inc"
707 target_free_working_area(target, info->source);
708 if (info->io_algorithm)
709 target_free_working_area(target, info->io_algorithm);
711 /* flash write code */
712 if (target_alloc_working_area(target, sizeof(sh_qspi_io_code),
713 &info->io_algorithm) != ERROR_OK) {
714 LOG_WARNING("no working area available, can't do block memory writes");
715 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
718 target_write_buffer(target, info->io_algorithm->address,
719 sizeof(sh_qspi_io_code), sh_qspi_io_code);
722 * Try to allocate as big work area buffer as possible, start
723 * with 32 kiB and count down. If there is less than 256 Bytes
724 * of work area available, abort.
726 info->buffer_size = 32768;
728 ret = target_alloc_working_area_try(target, info->buffer_size,
733 info->buffer_size /= 2;
734 if (info->buffer_size <= 256) {
735 target_free_working_area(target, info->io_algorithm);
737 LOG_WARNING("no large enough working area available, can't do block memory writes");
738 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
745 static int sh_qspi_probe(struct flash_bank *bank)
747 struct target *target = bank->target;
748 struct sh_qspi_flash_bank *info = bank->driver_priv;
749 struct flash_sector *sectors;
750 uint32_t id = 0; /* silence uninitialized warning */
752 const struct sh_qspi_target *target_device;
758 info->probed = false;
760 for (target_device = target_devices; target_device->name;
762 if (target_device->tap_idcode == target->tap->idcode)
764 if (!target_device->name) {
765 LOG_ERROR("Device ID 0x%" PRIx32 " is not known",
766 target->tap->idcode);
770 info->io_base = target_device->io_base;
772 LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT,
773 target_device->name, bank->base);
775 ret = sh_qspi_upload_helper(bank);
779 ret = sh_qspi_init(bank);
783 ret = read_flash_id(bank, &id);
788 for (const struct flash_device *p = flash_devices; p->name; p++)
789 if (p->device_id == id) {
795 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
799 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
800 info->dev->name, info->dev->device_id);
802 /* Set correct size value */
803 bank->size = info->dev->size_in_bytes;
804 if (bank->size <= (1UL << 16))
805 LOG_WARNING("device needs 2-byte addresses - not implemented");
807 /* if no sectors, treat whole bank as single sector */
808 sectorsize = info->dev->sectorsize ?
809 info->dev->sectorsize :
810 info->dev->size_in_bytes;
812 /* create and fill sectors array */
813 bank->num_sectors = info->dev->size_in_bytes / sectorsize;
814 sectors = calloc(1, sizeof(*sectors) * bank->num_sectors);
816 LOG_ERROR("not enough memory");
820 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
821 sectors[sector].offset = sector * sectorsize;
822 sectors[sector].size = sectorsize;
823 sectors[sector].is_erased = 0;
824 sectors[sector].is_protected = 0;
827 bank->sectors = sectors;
832 static int sh_qspi_auto_probe(struct flash_bank *bank)
834 struct sh_qspi_flash_bank *info = bank->driver_priv;
839 return sh_qspi_probe(bank);
842 static int sh_qspi_flash_blank_check(struct flash_bank *bank)
844 /* Not implemented */
848 static int sh_qspi_protect_check(struct flash_bank *bank)
850 /* Not implemented */
854 static int sh_qspi_get_info(struct flash_bank *bank, struct command_invocation *cmd)
856 struct sh_qspi_flash_bank *info = bank->driver_priv;
859 command_print_sameline(cmd, "\nSH QSPI flash bank not probed yet\n");
863 command_print_sameline(cmd, "\nSH QSPI flash information:\n"
864 " Device \'%s\' (ID 0x%08" PRIx32 ")\n",
865 info->dev->name, info->dev->device_id);
870 FLASH_BANK_COMMAND_HANDLER(sh_qspi_flash_bank_command)
872 struct sh_qspi_flash_bank *info;
874 LOG_DEBUG("%s", __func__);
876 if (CMD_ARGC < 6 || CMD_ARGC > 7)
877 return ERROR_COMMAND_SYNTAX_ERROR;
879 if ((CMD_ARGC == 7) && strcmp(CMD_ARGV[6], "cs0")) {
880 LOG_ERROR("Unknown arg: %s", CMD_ARGV[6]);
881 return ERROR_COMMAND_SYNTAX_ERROR;
884 info = calloc(1, sizeof(struct sh_qspi_flash_bank));
886 LOG_ERROR("not enough memory");
890 bank->driver_priv = info;
895 const struct flash_driver sh_qspi_flash = {
897 .flash_bank_command = sh_qspi_flash_bank_command,
898 .erase = sh_qspi_erase,
899 .protect = sh_qspi_protect,
900 .write = sh_qspi_write,
901 .read = sh_qspi_read,
902 .probe = sh_qspi_probe,
903 .auto_probe = sh_qspi_auto_probe,
904 .erase_check = sh_qspi_flash_blank_check,
905 .protect_check = sh_qspi_protect_check,
906 .info = sh_qspi_get_info,
907 .free_driver_priv = default_flash_free_driver_priv,