flash/nor/psoc4: adjust flash size limited by wounding
[fw/openocd] / src / flash / nor / psoc4.c
1 /***************************************************************************
2  *   Copyright (C) 2005 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   Copyright (C) 2008 by Spencer Oliver                                  *
6  *   spen@spen-soft.co.uk                                                  *
7  *                                                                         *
8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
9  *   andreas.fritiofson@gmail.com                                          *
10  *                                                                         *
11  *   Copyright (C) 2014 by Tomas Vanek (PSoC 4 support derived from STM32) *
12  *   vanekt@fbl.cz                                                         *
13  *                                                                         *
14  *   This program is free software; you can redistribute it and/or modify  *
15  *   it under the terms of the GNU General Public License as published by  *
16  *   the Free Software Foundation; either version 2 of the License, or     *
17  *   (at your option) any later version.                                   *
18  *                                                                         *
19  *   This program is distributed in the hope that it will be useful,       *
20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
22  *   GNU General Public License for more details.                          *
23  *                                                                         *
24  *   You should have received a copy of the GNU General Public License     *
25  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
26  ***************************************************************************/
27
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "imp.h"
33 #include <helper/binarybuffer.h>
34 #include <jtag/jtag.h>
35 #include <target/algorithm.h>
36 #include <target/armv7m.h>
37
38 /* device documets:
39
40  PSoC(R) 4: PSoC 4200 Family Datasheet
41         Document Number: 001-87197 Rev. *B  Revised August 29, 2013
42
43  PSoC 4100/4200 Family PSoC(R) 4 Architecture TRM
44         Document No. 001-85634 Rev. *E June 28, 2016
45
46  PSoC(R) 4 Registers TRM Spec.
47         Document No. 001-85847 Rev. *A June 25, 2013
48
49  PSoC 4000 Family PSoC(R) 4 Technical Reference Manual
50         Document No. 001-89309 Rev. *B May 9, 2016
51
52  PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM
53         Document No. 001-92738 Rev. *C February 12, 2016
54
55  PSoC 4200L Family PSoC 4 Architecture TRM
56         Document No. 001-97952 Rev. *A December 15, 2015
57
58  PSoC 4200L Family PSoC 4 Registers TRM
59         Document No. 001-98126 Rev. *A December 16, 2015
60
61  PSoC 4100M/4200M Family PSoC 4 Architecture TRM
62         Document No. 001-95223 Rev. *B July 29, 2015
63
64  PSoC 4100S Family PSoC 4 Architecture TRM
65         Document No. 002-10621 Rev. *A July 29, 2016
66
67  PSoC 4100S Family PSoC 4 Registers TRM
68         Document No. 002-10523 Rev. *A July 20, 2016
69
70  PSoC Analog Coprocessor Architecture TRM
71         Document No. 002-10404 Rev. ** December 18, 2015
72
73  CY8C4Axx PSoC Analog Coprocessor Registers TRM
74         Document No. 002-10405 Rev. ** December 18, 2015
75
76  CY8C41xx, CY8C42xx Programming Specifications
77         Document No. 001-81799 Rev. *C March 4, 2014
78
79  CYBL10x6x, CY8C4127_BL, CY8C4247_BL Programming Specifications
80         Document No. 001-91508 Rev. *B September 22, 2014
81
82  http://dmitry.gr/index.php?r=05.Projects&proj=24.%20PSoC4%20confidential
83 */
84
85 /* register locations */
86 #define PSOC4_SFLASH_MACRO0             0x0FFFF000
87
88 #define PSOC4_CPUSS_SYSREQ_LEGACY       0x40000004
89 #define PSOC4_CPUSS_SYSARG_LEGACY       0x40000008
90 #define PSOC4_SPCIF_GEOMETRY_LEGACY     0x400E0000
91
92 #define PSOC4_CPUSS_SYSREQ_NEW          0x40100004
93 #define PSOC4_CPUSS_SYSARG_NEW          0x40100008
94 #define PSOC4_SPCIF_GEOMETRY_NEW        0x40110000
95
96 #define PSOC4_TEST_MODE                 0x40030014
97
98 #define PSOC4_ROMTABLE_PID0             0xF0000FE0
99
100
101 /* constants */
102 #define PSOC4_SFLASH_MACRO_SIZE         0x400
103 #define PSOC4_ROWS_PER_MACRO            512
104
105 #define PSOC4_SROM_KEY1                 0xb6
106 #define PSOC4_SROM_KEY2                 0xd3
107 #define PSOC4_SROM_SYSREQ_BIT           (1<<31)
108 #define PSOC4_SROM_HMASTER_BIT          (1<<30)
109 #define PSOC4_SROM_PRIVILEGED_BIT       (1<<28)
110 #define PSOC4_SROM_STATUS_SUCCEEDED     0xa0000000
111 #define PSOC4_SROM_STATUS_FAILED        0xf0000000
112 #define PSOC4_SROM_STATUS_MASK          0xf0000000
113
114 /* not documented in any TRM */
115 #define PSOC4_SROM_ERR_IMO_NOT_IMPLEM   0xf0000013
116
117 #define PSOC4_CMD_GET_SILICON_ID        0
118 #define PSOC4_CMD_LOAD_LATCH            4
119 #define PSOC4_CMD_WRITE_ROW             5
120 #define PSOC4_CMD_PROGRAM_ROW           6
121 #define PSOC4_CMD_ERASE_ALL             0xa
122 #define PSOC4_CMD_CHECKSUM              0xb
123 #define PSOC4_CMD_WRITE_PROTECTION      0xd
124 #define PSOC4_CMD_SET_IMO48             0x15
125 #define PSOC4_CMD_WRITE_SFLASH_ROW      0x18
126
127 #define PSOC4_CHIP_PROT_VIRGIN          0x0
128 #define PSOC4_CHIP_PROT_OPEN            0x1
129 #define PSOC4_CHIP_PROT_PROTECTED       0x2
130 #define PSOC4_CHIP_PROT_KILL            0x4
131
132 #define PSOC4_ROMTABLE_DESIGNER_CHECK   0xb4
133
134 #define PSOC4_FAMILY_FLAG_LEGACY        1
135
136 struct psoc4_chip_family {
137         uint16_t id;
138         const char *name;
139         uint32_t flags;
140 };
141
142 const struct psoc4_chip_family psoc4_families[] = {
143         { 0x93, "PSoC4100/4200",           .flags = PSOC4_FAMILY_FLAG_LEGACY },
144         { 0x9A, "PSoC4000",                .flags = 0 },
145         { 0x9E, "PSoC/PRoC BLE (119E)",    .flags = 0 },
146         { 0xA0, "PSoC4200L",               .flags = 0 },
147         { 0xA1, "PSoC4100M/4200M",         .flags = 0 },
148         { 0xA3, "PSoC/PRoC BLE (11A3)",    .flags = 0 },
149         { 0xA9, "PSoC4000S",               .flags = 0 },
150         { 0xAA, "PSoC/PRoC BLE (11AA)",    .flags = 0 },
151         { 0xAB, "PSoC4100S",               .flags = 0 },
152         { 0xAC, "PSoC Analog Coprocessor", .flags = 0 },
153         { 0,    "Unknown",                 .flags = 0 }
154 };
155
156
157 struct psoc4_flash_bank {
158         uint32_t row_size;
159         uint32_t user_bank_size;
160         int num_macros;
161         bool probed;
162         uint8_t cmd_program_row;
163         uint16_t family_id;
164         bool legacy_family;
165         uint32_t cpuss_sysreq_addr;
166         uint32_t cpuss_sysarg_addr;
167         uint32_t spcif_geometry_addr;
168 };
169
170
171 static const struct psoc4_chip_family *psoc4_family_by_id(uint16_t family_id)
172 {
173         const struct psoc4_chip_family *p = psoc4_families;
174         while (p->id && p->id != family_id)
175                 p++;
176
177         return p;
178 }
179
180 static const char *psoc4_decode_chip_protection(uint8_t protection)
181 {
182         switch (protection) {
183         case PSOC4_CHIP_PROT_VIRGIN:
184                 return "protection VIRGIN";
185         case PSOC4_CHIP_PROT_OPEN:
186                 return "protection open";
187         case PSOC4_CHIP_PROT_PROTECTED:
188                 return "PROTECTED";
189         case PSOC4_CHIP_PROT_KILL:
190                 return "protection KILL";
191         default:
192                 LOG_WARNING("Unknown protection state 0x%02" PRIx8 "", protection);
193                 return "";
194         }
195 }
196
197
198 /* flash bank <name> psoc <base> <size> 0 0 <target#>
199  */
200 FLASH_BANK_COMMAND_HANDLER(psoc4_flash_bank_command)
201 {
202         struct psoc4_flash_bank *psoc4_info;
203
204         if (CMD_ARGC < 6)
205                 return ERROR_COMMAND_SYNTAX_ERROR;
206
207         psoc4_info = calloc(1, sizeof(struct psoc4_flash_bank));
208
209         bank->driver_priv = psoc4_info;
210         bank->default_padded_value = bank->erased_value = 0x00;
211         psoc4_info->user_bank_size = bank->size;
212         psoc4_info->cmd_program_row = PSOC4_CMD_WRITE_ROW;
213
214         return ERROR_OK;
215 }
216
217
218 /* PSoC 4 system ROM request
219  *  Setting SROM_SYSREQ_BIT in CPUSS_SYSREQ register runs NMI service
220  *  in sysrem ROM. Algorithm just waits for NMI to finish.
221  *  When sysreq_params_size == 0 only one parameter is passed in CPUSS_SYSARG register.
222  *  Otherwise address of memory parameter block is set in CPUSS_SYSARG
223  *  and the first parameter is written to the first word of parameter block
224  */
225 static int psoc4_sysreq(struct flash_bank *bank, uint8_t cmd,
226                 uint16_t cmd_param,
227                 uint32_t *sysreq_params, uint32_t sysreq_params_size,
228                 uint32_t *sysarg_out)
229 {
230         struct target *target = bank->target;
231         struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
232
233         struct working_area *sysreq_wait_algorithm;
234         struct working_area *sysreq_mem;
235
236         struct reg_param reg_params[1];
237         struct armv7m_algorithm armv7m_info;
238
239         int retval = ERROR_OK;
240
241         uint32_t param1 = PSOC4_SROM_KEY1
242                          | ((PSOC4_SROM_KEY2 + cmd) << 8)
243                          | (cmd_param << 16);
244
245         static uint8_t psoc4_sysreq_wait_code[] = {
246                 /* system request NMI is served immediately after algo run
247        now we are done: break */
248                 0x00, 0xbe,             /* bkpt 0 */
249         };
250
251         const int code_words = (sizeof(psoc4_sysreq_wait_code) + 3) / 4;
252                                         /* stack must be aligned */
253         const int stack_size = 256;
254         /* tested stack sizes on PSoC4200:
255                 ERASE_ALL       144
256                 PROGRAM_ROW     112
257                 other sysreq     68
258         */
259
260         /* allocate area for sysreq wait code and stack */
261         if (target_alloc_working_area(target, code_words * 4 + stack_size,
262                         &sysreq_wait_algorithm) != ERROR_OK) {
263                 LOG_DEBUG("no working area for sysreq code");
264                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
265         }
266
267         /* Write the code */
268         retval = target_write_buffer(target,
269                         sysreq_wait_algorithm->address,
270                         sizeof(psoc4_sysreq_wait_code),
271                         psoc4_sysreq_wait_code);
272         if (retval != ERROR_OK) {
273                 /* we already allocated the writing code, but failed to get a
274                  * buffer, free the algorithm */
275                 goto cleanup_algo;
276         }
277
278         if (sysreq_params_size) {
279                 LOG_DEBUG("SYSREQ %02" PRIx8 " %04" PRIx16 " %08" PRIx32 " %08" PRIx32 " size %" PRIu32,
280                         cmd, cmd_param, param1, sysreq_params[0], sysreq_params_size);
281                 /* Allocate memory for sysreq_params */
282                 retval = target_alloc_working_area(target, sysreq_params_size, &sysreq_mem);
283                 if (retval != ERROR_OK) {
284                         LOG_WARNING("no working area for sysreq parameters");
285
286                         /* we already allocated the writing code, but failed to get a
287                          * buffer, free the algorithm */
288                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
289                         goto cleanup_algo;
290                 }
291
292                 /* Write sysreq_params */
293                 target_buffer_set_u32(target, (uint8_t *)sysreq_params, param1);
294                 retval = target_write_buffer(target, sysreq_mem->address,
295                                 sysreq_params_size, (uint8_t *)sysreq_params);
296                 if (retval != ERROR_OK)
297                         goto cleanup_mem;
298
299                 /* Set address of sysreq parameters block */
300                 retval = target_write_u32(target, psoc4_info->cpuss_sysarg_addr, sysreq_mem->address);
301                 if (retval != ERROR_OK)
302                         goto cleanup_mem;
303
304         } else {
305                 /* Sysreq without memory block of parameters */
306                 LOG_DEBUG("SYSREQ %02" PRIx8 " %04" PRIx16 " %08" PRIx32,
307                         cmd, cmd_param, param1);
308                 /* Set register parameter */
309                 retval = target_write_u32(target, psoc4_info->cpuss_sysarg_addr, param1);
310                 if (retval != ERROR_OK)
311                         goto cleanup_mem;
312         }
313
314         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
315         armv7m_info.core_mode = ARM_MODE_THREAD;
316
317         /* sysreq stack */
318         init_reg_param(&reg_params[0], "sp", 32, PARAM_OUT);
319         buf_set_u32(reg_params[0].value, 0, 32,
320                     sysreq_wait_algorithm->address + sysreq_wait_algorithm->size);
321
322         struct armv7m_common *armv7m = target_to_armv7m(target);
323         if (armv7m == NULL) {
324                 /* something is very wrong if armv7m is NULL */
325                 LOG_ERROR("unable to get armv7m target");
326                 goto cleanup;
327         }
328
329         /* Set SROM request */
330         retval = target_write_u32(target, psoc4_info->cpuss_sysreq_addr,
331                                   PSOC4_SROM_SYSREQ_BIT | PSOC4_SROM_HMASTER_BIT | cmd);
332         if (retval != ERROR_OK)
333                 goto cleanup;
334
335         /* Execute wait code */
336         retval = target_run_algorithm(target, 0, NULL,
337                                 sizeof(reg_params) / sizeof(*reg_params), reg_params,
338                                 sysreq_wait_algorithm->address, 0, 1000, &armv7m_info);
339         if (retval != ERROR_OK) {
340                 LOG_ERROR("sysreq wait code execution failed");
341                 goto cleanup;
342         }
343
344         uint32_t sysarg_out_tmp;
345         retval = target_read_u32(target, psoc4_info->cpuss_sysarg_addr, &sysarg_out_tmp);
346         if (retval != ERROR_OK)
347                 goto cleanup;
348
349         if (sysarg_out) {
350                 *sysarg_out = sysarg_out_tmp;
351                 /* If result is an error, do not show now, let caller to decide */
352         } else if ((sysarg_out_tmp & PSOC4_SROM_STATUS_MASK) != PSOC4_SROM_STATUS_SUCCEEDED) {
353                 LOG_ERROR("sysreq error 0x%" PRIx32, sysarg_out_tmp);
354                 retval = ERROR_FAIL;
355         }
356 cleanup:
357         destroy_reg_param(&reg_params[0]);
358
359 cleanup_mem:
360         if (sysreq_params_size)
361                 target_free_working_area(target, sysreq_mem);
362
363 cleanup_algo:
364         target_free_working_area(target, sysreq_wait_algorithm);
365
366         return retval;
367 }
368
369
370 /* helper routine to get silicon ID from a PSoC 4 chip */
371 static int psoc4_get_silicon_id(struct flash_bank *bank, uint32_t *silicon_id, uint16_t *family_id, uint8_t *protection)
372 {
373         struct target *target = bank->target;
374         struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
375
376         uint32_t part0, part1;
377
378         int retval = psoc4_sysreq(bank, PSOC4_CMD_GET_SILICON_ID, 0, NULL, 0, &part0);
379         if (retval != ERROR_OK)
380                 return retval;
381
382         if ((part0 & PSOC4_SROM_STATUS_MASK) != PSOC4_SROM_STATUS_SUCCEEDED) {
383                 LOG_ERROR("sysreq error 0x%" PRIx32, part0);
384                 return ERROR_FAIL;
385         }
386
387         retval = target_read_u32(target, psoc4_info->cpuss_sysreq_addr, &part1);
388         if (retval != ERROR_OK)
389                 return retval;
390
391         /* build ID as Cypress sw does:
392          * bit 31..16 silicon ID
393          * bit 15..8  revision ID (so far 0x11 for all devices)
394          * bit 7..0   family ID (lowes 8 bits)
395          */
396         if (silicon_id)
397                         *silicon_id = ((part0 & 0x0000ffff) << 16)
398                                     | ((part0 & 0x00ff0000) >> 8)
399                                     | (part1 & 0x000000ff);
400
401         if (family_id)
402                         *family_id = part1 & 0x0fff;
403
404         if (protection)
405                         *protection = (part1 >> 12) & 0x0f;
406
407         return ERROR_OK;
408 }
409
410
411 static int psoc4_get_family(struct target *target, uint16_t *family_id)
412 {
413         int retval, i;
414         uint32_t pidbf[3];
415         uint8_t pid[3];
416
417         retval = target_read_memory(target, PSOC4_ROMTABLE_PID0, 4, 3, (uint8_t *)pidbf);
418         if (retval != ERROR_OK)
419                 return retval;
420
421         for (i = 0; i < 3; i++) {
422                 uint32_t tmp = target_buffer_get_u32(target, (uint8_t *)(pidbf + i));
423                 if (tmp & 0xffffff00) {
424                         LOG_ERROR("Unexpected data in ROMTABLE");
425                         return ERROR_FAIL;
426                 }
427                 pid[i] = tmp & 0xff;
428         }
429
430         uint16_t family = pid[0] | ((pid[1] & 0xf) << 8);
431         uint32_t designer = ((pid[1] & 0xf0) >> 4) | ((pid[2] & 0xf) << 4);
432
433         if (designer != PSOC4_ROMTABLE_DESIGNER_CHECK) {
434                 LOG_ERROR("ROMTABLE designer is not Cypress");
435                 return ERROR_FAIL;
436         }
437
438         *family_id = family;
439         return ERROR_OK;
440 }
441
442
443 static int psoc4_flash_prepare(struct flash_bank *bank)
444 {
445         struct target *target = bank->target;
446         struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
447
448         if (target->state != TARGET_HALTED) {
449                 LOG_ERROR("Target not halted");
450                 return ERROR_TARGET_NOT_HALTED;
451         }
452
453         uint16_t family_id;
454         int retval;
455
456         /* get family ID from SROM call */
457         retval = psoc4_get_silicon_id(bank, NULL, &family_id, NULL);
458         if (retval != ERROR_OK)
459                 return retval;
460
461         /* and check with family ID from ROMTABLE */
462         if (family_id != psoc4_info->family_id) {
463                 LOG_ERROR("Family mismatch");
464                 return ERROR_FAIL;
465         }
466
467         if (!psoc4_info->legacy_family) {
468                 uint32_t sysreq_status;
469                 retval = psoc4_sysreq(bank, PSOC4_CMD_SET_IMO48, 0, NULL, 0, &sysreq_status);
470                 if (retval != ERROR_OK)
471                         return retval;
472
473                 if ((sysreq_status & PSOC4_SROM_STATUS_MASK) != PSOC4_SROM_STATUS_SUCCEEDED) {
474                         /* This undocumented error code is returned probably when
475                          * PSOC4_CMD_SET_IMO48 command is not implemented.
476                          * Can be safely ignored, programming works.
477                          */
478                         if (sysreq_status == PSOC4_SROM_ERR_IMO_NOT_IMPLEM)
479                                 LOG_INFO("PSOC4_CMD_SET_IMO48 is not implemented on this device.");
480                         else {
481                                 LOG_ERROR("sysreq error 0x%" PRIx32, sysreq_status);
482                                 return ERROR_FAIL;
483                         }
484                 }
485         }
486
487         return ERROR_OK;
488 }
489
490
491 static int psoc4_protect_check(struct flash_bank *bank)
492 {
493         struct target *target = bank->target;
494         struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
495
496         uint32_t prot_addr = PSOC4_SFLASH_MACRO0;
497         int retval;
498         int s = 0;
499         int m, i;
500         uint8_t bf[PSOC4_ROWS_PER_MACRO/8];
501
502         for (m = 0; m < psoc4_info->num_macros; m++, prot_addr += PSOC4_SFLASH_MACRO_SIZE) {
503                 retval = target_read_memory(target, prot_addr, 4, PSOC4_ROWS_PER_MACRO/32, bf);
504                 if (retval != ERROR_OK)
505                         return retval;
506
507                 for (i = 0; i < PSOC4_ROWS_PER_MACRO && s < bank->num_sectors; i++, s++)
508                         bank->sectors[s].is_protected = bf[i/8] & (1 << (i%8)) ? 1 : 0;
509         }
510
511         return ERROR_OK;
512 }
513
514
515 static int psoc4_mass_erase(struct flash_bank *bank)
516 {
517         int i;
518         int retval = psoc4_flash_prepare(bank);
519         if (retval != ERROR_OK)
520                 return retval;
521
522         /* Call "Erase All" system ROM API */
523         uint32_t param = 0;
524         retval = psoc4_sysreq(bank, PSOC4_CMD_ERASE_ALL,
525                         0,
526                         &param, sizeof(param), NULL);
527
528         if (retval == ERROR_OK)
529                 /* set all sectors as erased */
530                 for (i = 0; i < bank->num_sectors; i++)
531                         bank->sectors[i].is_erased = 1;
532
533         return retval;
534 }
535
536
537 static int psoc4_erase(struct flash_bank *bank, int first, int last)
538 {
539         struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
540         if (psoc4_info->cmd_program_row == PSOC4_CMD_WRITE_ROW) {
541                 LOG_INFO("Autoerase enabled, erase command ignored");
542                 return ERROR_OK;
543         }
544
545         if ((first == 0) && (last == (bank->num_sectors - 1)))
546                 return psoc4_mass_erase(bank);
547
548         LOG_ERROR("Only mass erase available! Consider using 'psoc4 flash_autoerase 0 on'");
549
550         return ERROR_FAIL;
551 }
552
553
554 static int psoc4_protect(struct flash_bank *bank, int set, int first, int last)
555 {
556         struct target *target = bank->target;
557         struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
558
559         if (!psoc4_info->probed)
560                 return ERROR_FAIL;
561
562         int retval = psoc4_flash_prepare(bank);
563         if (retval != ERROR_OK)
564                 return retval;
565
566         uint32_t *sysrq_buffer = NULL;
567         const int param_sz = 8;
568         int chip_prot = PSOC4_CHIP_PROT_OPEN;
569         int i, m;
570         int num_bits = bank->num_sectors;
571
572         if (num_bits > PSOC4_ROWS_PER_MACRO)
573                 num_bits = PSOC4_ROWS_PER_MACRO;
574
575         int prot_sz = num_bits / 8;
576
577         sysrq_buffer = calloc(1, param_sz + prot_sz);
578         if (sysrq_buffer == NULL) {
579                 LOG_ERROR("no memory for row buffer");
580                 return ERROR_FAIL;
581         }
582
583         for (i = first; i <= last && i < bank->num_sectors; i++)
584                 bank->sectors[i].is_protected = set;
585
586         for (m = 0; m < psoc4_info->num_macros; m++) {
587                 uint8_t *p = (uint8_t *)(sysrq_buffer + 2);
588                 for (i = 0; i < num_bits && i < bank->num_sectors; i++) {
589                         if (bank->sectors[i].is_protected)
590                                 p[i/8] |= 1 << (i%8);
591                 }
592
593                 /* Call "Load Latch" system ROM API */
594                 target_buffer_set_u32(target, (uint8_t *)(sysrq_buffer + 1),
595                                         prot_sz - 1);
596                 retval = psoc4_sysreq(bank, PSOC4_CMD_LOAD_LATCH,
597                         0       /* Byte number in latch from what to write */
598                           | (m << 8), /* flash macro index */
599                         sysrq_buffer, param_sz + psoc4_info->row_size,
600                         NULL);
601                 if (retval != ERROR_OK)
602                         break;
603
604                 /* Call "Write Protection" system ROM API */
605                 retval = psoc4_sysreq(bank, PSOC4_CMD_WRITE_PROTECTION,
606                         chip_prot | (m << 8), NULL, 0, NULL);
607                 if (retval != ERROR_OK)
608                         break;
609         }
610
611         if (sysrq_buffer)
612                 free(sysrq_buffer);
613
614         psoc4_protect_check(bank);
615         return retval;
616 }
617
618
619 COMMAND_HANDLER(psoc4_handle_flash_autoerase_command)
620 {
621         if (CMD_ARGC < 1)
622                 return ERROR_COMMAND_SYNTAX_ERROR;
623
624         struct flash_bank *bank;
625         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
626         if (ERROR_OK != retval)
627                 return retval;
628
629         struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
630         bool enable = psoc4_info->cmd_program_row == PSOC4_CMD_WRITE_ROW;
631
632         if (CMD_ARGC >= 2)
633                 COMMAND_PARSE_ON_OFF(CMD_ARGV[1], enable);
634
635         if (enable) {
636                 psoc4_info->cmd_program_row = PSOC4_CMD_WRITE_ROW;
637                 LOG_INFO("Flash auto-erase enabled, non mass erase commands will be ignored.");
638         } else {
639                 psoc4_info->cmd_program_row = PSOC4_CMD_PROGRAM_ROW;
640                 LOG_INFO("Flash auto-erase disabled. Use psoc mass_erase before flash programming.");
641         }
642
643         return retval;
644 }
645
646
647 static int psoc4_write(struct flash_bank *bank, const uint8_t *buffer,
648                 uint32_t offset, uint32_t count)
649 {
650         struct target *target = bank->target;
651         struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
652         uint32_t *sysrq_buffer = NULL;
653         const int param_sz = 8;
654
655         int retval = psoc4_flash_prepare(bank);
656         if (retval != ERROR_OK)
657                 return retval;
658
659         sysrq_buffer = malloc(param_sz + psoc4_info->row_size);
660         if (sysrq_buffer == NULL) {
661                 LOG_ERROR("no memory for row buffer");
662                 return ERROR_FAIL;
663         }
664
665         uint8_t *row_buffer = (uint8_t *)sysrq_buffer + param_sz;
666         uint32_t row_num = offset / psoc4_info->row_size;
667         uint32_t row_offset = offset - row_num * psoc4_info->row_size;
668         if (row_offset)
669                 memset(row_buffer, bank->default_padded_value, row_offset);
670
671         bool save_poll = jtag_poll_get_enabled();
672         jtag_poll_set_enabled(false);
673
674         while (count) {
675                 uint32_t chunk_size = psoc4_info->row_size - row_offset;
676                 if (chunk_size > count) {
677                         chunk_size = count;
678                         memset(row_buffer + chunk_size, bank->default_padded_value, psoc4_info->row_size - chunk_size);
679                 }
680                 memcpy(row_buffer + row_offset, buffer, chunk_size);
681                 LOG_DEBUG("offset / row: 0x%08" PRIx32 " / %" PRIu32 ", size %" PRIu32 "",
682                                 offset, row_offset, chunk_size);
683
684                 uint32_t macro_idx = row_num / PSOC4_ROWS_PER_MACRO;
685
686                 /* Call "Load Latch" system ROM API */
687                 target_buffer_set_u32(target, (uint8_t *)(sysrq_buffer + 1),
688                                         psoc4_info->row_size - 1);
689                 retval = psoc4_sysreq(bank, PSOC4_CMD_LOAD_LATCH,
690                                 0       /* Byte number in latch from what to write */
691                                   | (macro_idx << 8),
692                                 sysrq_buffer, param_sz + psoc4_info->row_size,
693                                 NULL);
694                 if (retval != ERROR_OK)
695                         goto cleanup;
696
697                 /* Call "Program Row" or "Write Row" system ROM API */
698                 uint32_t sysrq_param;
699                 retval = psoc4_sysreq(bank, psoc4_info->cmd_program_row,
700                                 row_num & 0xffff,
701                                 &sysrq_param, sizeof(sysrq_param),
702                                 NULL);
703                 if (retval != ERROR_OK)
704                         goto cleanup;
705
706                 buffer += chunk_size;
707                 row_num++;
708                 row_offset = 0;
709                 count -= chunk_size;
710         }
711
712 cleanup:
713         jtag_poll_set_enabled(save_poll);
714
715         if (sysrq_buffer)
716                 free(sysrq_buffer);
717
718         return retval;
719 }
720
721
722 /* Due to Cypress's method of market segmentation some devices
723  * have accessible only 1/2, 1/4 or 1/8 of SPCIF described flash */
724 static int psoc4_test_flash_wounding(struct target *target, uint32_t flash_size)
725 {
726         int retval, i;
727         for (i = 3; i >= 1; i--) {
728                 uint32_t addr = flash_size >> i;
729                 uint32_t dummy;
730                 retval = target_read_u32(target, addr, &dummy);
731                 if (retval != ERROR_OK)
732                         return i;
733         }
734         return 0;
735 }
736
737
738 static int psoc4_probe(struct flash_bank *bank)
739 {
740         struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
741         struct target *target = bank->target;
742
743         int retval;
744         uint16_t family_id;
745
746         psoc4_info->probed = false;
747
748         retval = psoc4_get_family(target, &family_id);
749         if (retval != ERROR_OK)
750                 return retval;
751
752         const struct psoc4_chip_family *family = psoc4_family_by_id(family_id);
753
754         if (family->id == 0) {
755                 LOG_ERROR("Cannot identify PSoC 4 family.");
756                 return ERROR_FAIL;
757         }
758
759         if (family->flags & PSOC4_FAMILY_FLAG_LEGACY) {
760                 LOG_INFO("%s legacy family detected.", family->name);
761                 psoc4_info->legacy_family = true;
762                 psoc4_info->cpuss_sysreq_addr = PSOC4_CPUSS_SYSREQ_LEGACY;
763                 psoc4_info->cpuss_sysarg_addr = PSOC4_CPUSS_SYSARG_LEGACY;
764                 psoc4_info->spcif_geometry_addr = PSOC4_SPCIF_GEOMETRY_LEGACY;
765         } else {
766                 LOG_INFO("%s family detected.", family->name);
767                 psoc4_info->legacy_family = false;
768                 psoc4_info->cpuss_sysreq_addr = PSOC4_CPUSS_SYSREQ_NEW;
769                 psoc4_info->cpuss_sysarg_addr = PSOC4_CPUSS_SYSARG_NEW;
770                 psoc4_info->spcif_geometry_addr = PSOC4_SPCIF_GEOMETRY_NEW;
771         }
772
773         uint32_t spcif_geometry;
774         retval = target_read_u32(target, psoc4_info->spcif_geometry_addr, &spcif_geometry);
775         if (retval != ERROR_OK)
776                 return retval;
777
778         uint32_t flash_size_in_kb = spcif_geometry & 0x3fff;
779         /* TRM of legacy, M and L version describes FLASH field as 16-bit.
780          * S-series and PSoC Analog Coprocessor changes spec to 14-bit only.
781          * Impose PSoC Analog Coprocessor limit to all devices as it
782          * does not make any harm: flash size is safely below 4 MByte limit
783          */
784         uint32_t row_size = (spcif_geometry >> 22) & 3;
785         uint32_t num_macros = (spcif_geometry >> 20) & 3;
786
787         if (psoc4_info->legacy_family) {
788                 flash_size_in_kb = flash_size_in_kb * 256 / 1024;
789                 row_size *= 128;
790         } else {
791                 flash_size_in_kb = (flash_size_in_kb + 1) * 256 / 1024;
792                 row_size = 64 * (row_size + 1);
793                 num_macros++;
794         }
795
796         LOG_DEBUG("SPCIF geometry: %" PRIu32 " kb flash, row %" PRIu32 " bytes.",
797                  flash_size_in_kb, row_size);
798
799         /* if the user sets the size manually then ignore the probed value
800          * this allows us to work around devices that have a invalid flash size register value */
801         if (psoc4_info->user_bank_size) {
802                 LOG_INFO("ignoring flash probed value, using configured bank size");
803                 flash_size_in_kb = psoc4_info->user_bank_size / 1024;
804         }
805
806         char macros_txt[20] = "";
807         if (num_macros > 1)
808                 snprintf(macros_txt, sizeof(macros_txt), " in %" PRIu32 " macros", num_macros);
809
810         LOG_INFO("flash size = %" PRIu32 " kbytes%s", flash_size_in_kb, macros_txt);
811
812         /* calculate number of pages */
813         uint32_t num_rows = flash_size_in_kb * 1024 / row_size;
814
815         /* check number of flash macros */
816         if (num_macros != (num_rows + PSOC4_ROWS_PER_MACRO - 1) / PSOC4_ROWS_PER_MACRO)
817                 LOG_WARNING("Number of macros does not correspond with flash size!");
818
819         if (!psoc4_info->legacy_family) {
820                 int wounding = psoc4_test_flash_wounding(target, num_rows * row_size);
821                 if (wounding > 0) {
822                         flash_size_in_kb = flash_size_in_kb >> wounding;
823                         num_rows = num_rows >> wounding;
824                         LOG_INFO("WOUNDING detected: accessible flash size %" PRIu32 " kbytes", flash_size_in_kb);
825                 }
826         }
827
828         if (bank->sectors) {
829                 free(bank->sectors);
830         }
831
832         psoc4_info->family_id = family_id;
833         psoc4_info->num_macros = num_macros;
834         psoc4_info->row_size = row_size;
835         bank->base = 0x00000000;
836         bank->size = num_rows * row_size;
837         bank->num_sectors = num_rows;
838         bank->sectors = alloc_block_array(0, row_size, num_rows);
839         if (bank->sectors == NULL)
840                 return ERROR_FAIL;
841
842         LOG_DEBUG("flash bank set %" PRIu32 " rows", num_rows);
843         psoc4_info->probed = true;
844
845         return ERROR_OK;
846 }
847
848 static int psoc4_auto_probe(struct flash_bank *bank)
849 {
850         struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
851         if (psoc4_info->probed)
852                 return ERROR_OK;
853         return psoc4_probe(bank);
854 }
855
856
857 static int get_psoc4_info(struct flash_bank *bank, char *buf, int buf_size)
858 {
859         struct target *target = bank->target;
860         struct psoc4_flash_bank *psoc4_info = bank->driver_priv;
861
862         if (!psoc4_info->probed)
863                 return ERROR_FAIL;
864
865         const struct psoc4_chip_family *family = psoc4_family_by_id(psoc4_info->family_id);
866         uint32_t size_in_kb = bank->size / 1024;
867
868         if (target->state != TARGET_HALTED) {
869                 snprintf(buf, buf_size, "%s, flash %" PRIu32 " kb"
870                         " (halt target to see details)", family->name, size_in_kb);
871                 return ERROR_OK;
872         }
873
874         int retval;
875         int printed = 0;
876         uint32_t silicon_id;
877         uint16_t family_id;
878         uint8_t protection;
879
880         retval = psoc4_get_silicon_id(bank, &silicon_id, &family_id, &protection);
881         if (retval != ERROR_OK)
882                 return retval;
883
884         if (family_id != psoc4_info->family_id)
885                 printed = snprintf(buf, buf_size, "Family id mismatch 0x%02" PRIx16
886                         "/0x%02" PRIx16 ", silicon id 0x%08" PRIx32,
887                         psoc4_info->family_id, family_id, silicon_id);
888         else {
889                 printed = snprintf(buf, buf_size, "%s silicon id 0x%08" PRIx32 "",
890                         family->name, silicon_id);
891         }
892
893         buf += printed;
894         buf_size -= printed;
895
896         const char *prot_txt = psoc4_decode_chip_protection(protection);
897         snprintf(buf, buf_size, ", flash %" PRIu32 " kb %s", size_in_kb, prot_txt);
898         return ERROR_OK;
899 }
900
901
902 COMMAND_HANDLER(psoc4_handle_mass_erase_command)
903 {
904         if (CMD_ARGC < 1)
905                 return ERROR_COMMAND_SYNTAX_ERROR;
906
907         struct flash_bank *bank;
908         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
909         if (ERROR_OK != retval)
910                 return retval;
911
912         retval = psoc4_mass_erase(bank);
913         if (retval == ERROR_OK)
914                 command_print(CMD_CTX, "psoc mass erase complete");
915         else
916                 command_print(CMD_CTX, "psoc mass erase failed");
917
918         return retval;
919 }
920
921
922 static const struct command_registration psoc4_exec_command_handlers[] = {
923         {
924                 .name = "mass_erase",
925                 .handler = psoc4_handle_mass_erase_command,
926                 .mode = COMMAND_EXEC,
927                 .usage = "bank_id",
928                 .help = "Erase entire flash device.",
929         },
930         {
931                 .name = "flash_autoerase",
932                 .handler = psoc4_handle_flash_autoerase_command,
933                 .mode = COMMAND_EXEC,
934                 .usage = "bank_id on|off",
935                 .help = "Set autoerase mode for flash bank.",
936         },
937         COMMAND_REGISTRATION_DONE
938 };
939
940 static const struct command_registration psoc4_command_handlers[] = {
941         {
942                 .name = "psoc4",
943                 .mode = COMMAND_ANY,
944                 .help = "PSoC 4 flash command group",
945                 .usage = "",
946                 .chain = psoc4_exec_command_handlers,
947         },
948         COMMAND_REGISTRATION_DONE
949 };
950
951 struct flash_driver psoc4_flash = {
952         .name = "psoc4",
953         .commands = psoc4_command_handlers,
954         .flash_bank_command = psoc4_flash_bank_command,
955         .erase = psoc4_erase,
956         .protect = psoc4_protect,
957         .write = psoc4_write,
958         .read = default_flash_read,
959         .probe = psoc4_probe,
960         .auto_probe = psoc4_auto_probe,
961         .erase_check = default_flash_blank_check,
962         .protect_check = psoc4_protect_check,
963         .info = get_psoc4_info,
964 };