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   1 /***************************************************************************
   2  *   Copyright (C) 2013 Synapse Product Development                        *
   3  *   Andrey Smirnov <andrew.smironv@gmail.com>                             *
   4  *   Angus Gratton <gus@projectgus.com>                                    *
   5  *   Erdem U. Altunyurt <spamjunkeater@gmail.com>                          *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include "imp.h"
  26 #include <target/algorithm.h>
  27 #include <target/armv7m.h>
  28 #include <helper/types.h>
  29
  30 enum {
  31         NRF51_FLASH_BASE = 0x00000000,
  32 };
  33
  34 enum nrf51_ficr_registers {
  35         NRF51_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
  36
  37 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
  38
  39         NRF51_FICR_CODEPAGESIZE         = NRF51_FICR_REG(0x010),
  40         NRF51_FICR_CODESIZE             = NRF51_FICR_REG(0x014),
  41         NRF51_FICR_CLENR0               = NRF51_FICR_REG(0x028),
  42         NRF51_FICR_PPFC                 = NRF51_FICR_REG(0x02C),
  43         NRF51_FICR_NUMRAMBLOCK          = NRF51_FICR_REG(0x034),
  44         NRF51_FICR_SIZERAMBLOCK0        = NRF51_FICR_REG(0x038),
  45         NRF51_FICR_SIZERAMBLOCK1        = NRF51_FICR_REG(0x03C),
  46         NRF51_FICR_SIZERAMBLOCK2        = NRF51_FICR_REG(0x040),
  47         NRF51_FICR_SIZERAMBLOCK3        = NRF51_FICR_REG(0x044),
  48         NRF51_FICR_CONFIGID             = NRF51_FICR_REG(0x05C),
  49         NRF51_FICR_DEVICEID0            = NRF51_FICR_REG(0x060),
  50         NRF51_FICR_DEVICEID1            = NRF51_FICR_REG(0x064),
  51         NRF51_FICR_ER0                  = NRF51_FICR_REG(0x080),
  52         NRF51_FICR_ER1                  = NRF51_FICR_REG(0x084),
  53         NRF51_FICR_ER2                  = NRF51_FICR_REG(0x088),
  54         NRF51_FICR_ER3                  = NRF51_FICR_REG(0x08C),
  55         NRF51_FICR_IR0                  = NRF51_FICR_REG(0x090),
  56         NRF51_FICR_IR1                  = NRF51_FICR_REG(0x094),
  57         NRF51_FICR_IR2                  = NRF51_FICR_REG(0x098),
  58         NRF51_FICR_IR3                  = NRF51_FICR_REG(0x09C),
  59         NRF51_FICR_DEVICEADDRTYPE       = NRF51_FICR_REG(0x0A0),
  60         NRF51_FICR_DEVICEADDR0          = NRF51_FICR_REG(0x0A4),
  61         NRF51_FICR_DEVICEADDR1          = NRF51_FICR_REG(0x0A8),
  62         NRF51_FICR_OVERRIDEN            = NRF51_FICR_REG(0x0AC),
  63         NRF51_FICR_NRF_1MBIT0           = NRF51_FICR_REG(0x0B0),
  64         NRF51_FICR_NRF_1MBIT1           = NRF51_FICR_REG(0x0B4),
  65         NRF51_FICR_NRF_1MBIT2           = NRF51_FICR_REG(0x0B8),
  66         NRF51_FICR_NRF_1MBIT3           = NRF51_FICR_REG(0x0BC),
  67         NRF51_FICR_NRF_1MBIT4           = NRF51_FICR_REG(0x0C0),
  68         NRF51_FICR_BLE_1MBIT0           = NRF51_FICR_REG(0x0EC),
  69         NRF51_FICR_BLE_1MBIT1           = NRF51_FICR_REG(0x0F0),
  70         NRF51_FICR_BLE_1MBIT2           = NRF51_FICR_REG(0x0F4),
  71         NRF51_FICR_BLE_1MBIT3           = NRF51_FICR_REG(0x0F8),
  72         NRF51_FICR_BLE_1MBIT4           = NRF51_FICR_REG(0x0FC),
  73 };
  74
  75 enum nrf51_uicr_registers {
  76         NRF51_UICR_BASE = 0x10001000, /* User Information
  77                                        * Configuration Regsters */
  78
  79         NRF51_UICR_SIZE = 0x100,
  80
  81 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
  82
  83         NRF51_UICR_CLENR0       = NRF51_UICR_REG(0x000),
  84         NRF51_UICR_RBPCONF      = NRF51_UICR_REG(0x004),
  85         NRF51_UICR_XTALFREQ     = NRF51_UICR_REG(0x008),
  86         NRF51_UICR_FWID         = NRF51_UICR_REG(0x010),
  87 };
  88
  89 enum nrf51_nvmc_registers {
  90         NRF51_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
  91                                        * Controller Regsters */
  92
  93 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
  94
  95         NRF51_NVMC_READY        = NRF51_NVMC_REG(0x400),
  96         NRF51_NVMC_CONFIG       = NRF51_NVMC_REG(0x504),
  97         NRF51_NVMC_ERASEPAGE    = NRF51_NVMC_REG(0x508),
  98         NRF51_NVMC_ERASEALL     = NRF51_NVMC_REG(0x50C),
  99         NRF51_NVMC_ERASEUICR    = NRF51_NVMC_REG(0x514),
 100 };
 101
 102 enum nrf51_nvmc_config_bits {
 103         NRF51_NVMC_CONFIG_REN = 0x00,
 104         NRF51_NVMC_CONFIG_WEN = 0x01,
 105         NRF51_NVMC_CONFIG_EEN = 0x02,
 106
 107 };
 108
 109 struct nrf51_info {
 110         uint32_t code_page_size;
 111
 112         struct {
 113                 bool probed;
 114                 int (*write) (struct flash_bank *bank,
 115                               struct nrf51_info *chip,
 116                               const uint8_t *buffer, uint32_t offset, uint32_t count);
 117         } bank[2];
 118         struct target *target;
 119 };
 120
 121 struct nrf51_device_spec {
 122         uint16_t hwid;
 123         const char *part;
 124         const char *variant;
 125         const char *build_code;
 126         unsigned int flash_size_kb;
 127 };
 128
 129 /* The known devices table below is derived from the "nRF51 Series
 130  * Compatibility Matrix" document, which can be found by searching for
 131  * ATTN-51 on the Nordic Semi website:
 132  *
 133  * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
 134  *
 135  * Up to date with Matrix v2.0, plus some additional HWIDs.
 136  *
 137  * The additional HWIDs apply where the build code in the matrix is
 138  * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
 139  * for x==0, x!=0 means different (unspecified) HWIDs.
 140  */
 141 static const struct nrf51_device_spec nrf51_known_devices_table[] = {
 142         /* nRF51822 Devices (IC rev 1). */
 143         {
 144                 .hwid           = 0x001D,
 145                 .part           = "51822",
 146                 .variant        = "QFAA",
 147                 .build_code     = "CA/C0",
 148                 .flash_size_kb  = 256,
 149         },
 150         {
 151                 .hwid           = 0x0026,
 152                 .part           = "51822",
 153                 .variant        = "QFAB",
 154                 .build_code     = "AA",
 155                 .flash_size_kb  = 128,
 156         },
 157         {
 158                 .hwid           = 0x0027,
 159                 .part           = "51822",
 160                 .variant        = "QFAB",
 161                 .build_code     = "A0",
 162                 .flash_size_kb  = 128,
 163         },
 164         {
 165                 .hwid           = 0x0020,
 166                 .part           = "51822",
 167                 .variant        = "CEAA",
 168                 .build_code     = "BA",
 169                 .flash_size_kb  = 256,
 170         },
 171         {
 172                 .hwid           = 0x002F,
 173                 .part           = "51822",
 174                 .variant        = "CEAA",
 175                 .build_code     = "B0",
 176                 .flash_size_kb  = 256,
 177         },
 178
 179         /* nRF51822 Devices (IC rev 2). */
 180         {
 181                 .hwid           = 0x002A,
 182                 .part           = "51822",
 183                 .variant        = "QFAA",
 184                 .build_code     = "FA0",
 185                 .flash_size_kb  = 256,
 186         },
 187         {
 188                 .hwid           = 0x0044,
 189                 .part           = "51822",
 190                 .variant        = "QFAA",
 191                 .build_code     = "GC0",
 192                 .flash_size_kb  = 256,
 193         },
 194         {
 195                 .hwid           = 0x003C,
 196                 .part           = "51822",
 197                 .variant        = "QFAA",
 198                 .build_code     = "G0",
 199                 .flash_size_kb  = 256,
 200         },
 201         {
 202                 .hwid           = 0x0057,
 203                 .part           = "51822",
 204                 .variant        = "QFAA",
 205                 .build_code     = "G2",
 206                 .flash_size_kb  = 256,
 207         },
 208         {
 209                 .hwid           = 0x0058,
 210                 .part           = "51822",
 211                 .variant        = "QFAA",
 212                 .build_code     = "G3",
 213                 .flash_size_kb  = 256,
 214         },
 215         {
 216                 .hwid           = 0x004C,
 217                 .part           = "51822",
 218                 .variant        = "QFAB",
 219                 .build_code     = "B0",
 220                 .flash_size_kb  = 128,
 221         },
 222         {
 223                 .hwid           = 0x0040,
 224                 .part           = "51822",
 225                 .variant        = "CEAA",
 226                 .build_code     = "CA0",
 227                 .flash_size_kb  = 256,
 228         },
 229         {
 230                 .hwid           = 0x0047,
 231                 .part           = "51822",
 232                 .variant        = "CEAA",
 233                 .build_code     = "DA0",
 234                 .flash_size_kb  = 256,
 235         },
 236         {
 237                 .hwid           = 0x004D,
 238                 .part           = "51822",
 239                 .variant        = "CEAA",
 240                 .build_code     = "D00",
 241                 .flash_size_kb  = 256,
 242         },
 243
 244         /* nRF51822 Devices (IC rev 3). */
 245         {
 246                 .hwid           = 0x0072,
 247                 .part           = "51822",
 248                 .variant        = "QFAA",
 249                 .build_code     = "H0",
 250                 .flash_size_kb  = 256,
 251         },
 252         {
 253                 .hwid           = 0x007B,
 254                 .part           = "51822",
 255                 .variant        = "QFAB",
 256                 .build_code     = "C0",
 257                 .flash_size_kb  = 128,
 258         },
 259         {
 260                 .hwid           = 0x0083,
 261                 .part           = "51822",
 262                 .variant        = "QFAC",
 263                 .build_code     = "A0",
 264                 .flash_size_kb  = 256,
 265         },
 266         {
 267                 .hwid           = 0x0084,
 268                 .part           = "51822",
 269                 .variant        = "QFAC",
 270                 .build_code     = "A1",
 271                 .flash_size_kb  = 256,
 272         },
 273         {
 274                 .hwid           = 0x007D,
 275                 .part           = "51822",
 276                 .variant        = "CDAB",
 277                 .build_code     = "A0",
 278                 .flash_size_kb  = 128,
 279         },
 280         {
 281                 .hwid           = 0x0079,
 282                 .part           = "51822",
 283                 .variant        = "CEAA",
 284                 .build_code     = "E0",
 285                 .flash_size_kb  = 256,
 286         },
 287         {
 288                 .hwid           = 0x0087,
 289                 .part           = "51822",
 290                 .variant        = "CFAC",
 291                 .build_code     = "A0",
 292                 .flash_size_kb  = 256,
 293         },
 294
 295         /* nRF51422 Devices (IC rev 1). */
 296         {
 297                 .hwid           = 0x001E,
 298                 .part           = "51422",
 299                 .variant        = "QFAA",
 300                 .build_code     = "CA",
 301                 .flash_size_kb  = 256,
 302         },
 303         {
 304                 .hwid           = 0x0024,
 305                 .part           = "51422",
 306                 .variant        = "QFAA",
 307                 .build_code     = "C0",
 308                 .flash_size_kb  = 256,
 309         },
 310         {
 311                 .hwid           = 0x0031,
 312                 .part           = "51422",
 313                 .variant        = "CEAA",
 314                 .build_code     = "A0A",
 315                 .flash_size_kb  = 256,
 316         },
 317
 318         /* nRF51422 Devices (IC rev 2). */
 319         {
 320                 .hwid           = 0x002D,
 321                 .part           = "51422",
 322                 .variant        = "QFAA",
 323                 .build_code     = "DAA",
 324                 .flash_size_kb  = 256,
 325         },
 326         {
 327                 .hwid           = 0x002E,
 328                 .part           = "51422",
 329                 .variant        = "QFAA",
 330                 .build_code     = "E0",
 331                 .flash_size_kb  = 256,
 332         },
 333         {
 334                 .hwid           = 0x0061,
 335                 .part           = "51422",
 336                 .variant        = "QFAB",
 337                 .build_code     = "A00",
 338                 .flash_size_kb  = 128,
 339         },
 340         {
 341                 .hwid           = 0x0050,
 342                 .part           = "51422",
 343                 .variant        = "CEAA",
 344                 .build_code     = "B0",
 345                 .flash_size_kb  = 256,
 346         },
 347
 348         /* nRF51422 Devices (IC rev 3). */
 349         {
 350                 .hwid           = 0x0073,
 351                 .part           = "51422",
 352                 .variant        = "QFAA",
 353                 .build_code     = "F0",
 354                 .flash_size_kb  = 256,
 355         },
 356         {
 357                 .hwid           = 0x007C,
 358                 .part           = "51422",
 359                 .variant        = "QFAB",
 360                 .build_code     = "B0",
 361                 .flash_size_kb  = 128,
 362         },
 363         {
 364                 .hwid           = 0x0085,
 365                 .part           = "51422",
 366                 .variant        = "QFAC",
 367                 .build_code     = "A0",
 368                 .flash_size_kb  = 256,
 369         },
 370         {
 371                 .hwid           = 0x0086,
 372                 .part           = "51422",
 373                 .variant        = "QFAC",
 374                 .build_code     = "A1",
 375                 .flash_size_kb  = 256,
 376         },
 377         {
 378                 .hwid           = 0x007E,
 379                 .part           = "51422",
 380                 .variant        = "CDAB",
 381                 .build_code     = "A0",
 382                 .flash_size_kb  = 128,
 383         },
 384         {
 385                 .hwid           = 0x007A,
 386                 .part           = "51422",
 387                 .variant        = "CEAA",
 388                 .build_code     = "C0",
 389                 .flash_size_kb  = 256,
 390         },
 391         {
 392                 .hwid           = 0x0088,
 393                 .part           = "51422",
 394                 .variant        = "CFAC",
 395                 .build_code     = "A0",
 396                 .flash_size_kb  = 256,
 397         },
 398
 399         /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
 400            with built-in jlink seem to use engineering samples not listed
 401            in the nRF51 Series Compatibility Matrix V1.0. */
 402         {
 403                 .hwid           = 0x0071,
 404                 .part           = "51822",
 405                 .variant        = "QFAC",
 406                 .build_code     = "AB",
 407                 .flash_size_kb  = 256,
 408         },
 409 };
 410
 411 static int nrf51_bank_is_probed(struct flash_bank *bank)
 412 {
 413         struct nrf51_info *chip = bank->driver_priv;
 414
 415         assert(chip != NULL);
 416
 417         return chip->bank[bank->bank_number].probed;
 418 }
 419 static int nrf51_probe(struct flash_bank *bank);
 420
 421 static int nrf51_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf51_info **chip)
 422 {
 423         if (bank->target->state != TARGET_HALTED) {
 424                 LOG_ERROR("Target not halted");
 425                 return ERROR_TARGET_NOT_HALTED;
 426         }
 427
 428         *chip = bank->driver_priv;
 429
 430         int probed = nrf51_bank_is_probed(bank);
 431         if (probed < 0)
 432                 return probed;
 433         else if (!probed)
 434                 return nrf51_probe(bank);
 435         else
 436                 return ERROR_OK;
 437 }
 438
 439 static int nrf51_wait_for_nvmc(struct nrf51_info *chip)
 440 {
 441         uint32_t ready;
 442         int res;
 443         int timeout = 100;
 444
 445         do {
 446                 res = target_read_u32(chip->target, NRF51_NVMC_READY, &ready);
 447                 if (res != ERROR_OK) {
 448                         LOG_ERROR("Couldn't read NVMC_READY register");
 449                         return res;
 450                 }
 451
 452                 if (ready == 0x00000001)
 453                         return ERROR_OK;
 454
 455                 alive_sleep(1);
 456         } while (timeout--);
 457
 458         LOG_DEBUG("Timed out waiting for NVMC_READY");
 459         return ERROR_FLASH_BUSY;
 460 }
 461
 462 static int nrf51_nvmc_erase_enable(struct nrf51_info *chip)
 463 {
 464         int res;
 465         res = target_write_u32(chip->target,
 466                                NRF51_NVMC_CONFIG,
 467                                NRF51_NVMC_CONFIG_EEN);
 468
 469         if (res != ERROR_OK) {
 470                 LOG_ERROR("Failed to enable erase operation");
 471                 return res;
 472         }
 473
 474         /*
 475           According to NVMC examples in Nordic SDK busy status must be
 476           checked after writing to NVMC_CONFIG
 477          */
 478         res = nrf51_wait_for_nvmc(chip);
 479         if (res != ERROR_OK)
 480                 LOG_ERROR("Erase enable did not complete");
 481
 482         return res;
 483 }
 484
 485 static int nrf51_nvmc_write_enable(struct nrf51_info *chip)
 486 {
 487         int res;
 488         res = target_write_u32(chip->target,
 489                                NRF51_NVMC_CONFIG,
 490                                NRF51_NVMC_CONFIG_WEN);
 491
 492         if (res != ERROR_OK) {
 493                 LOG_ERROR("Failed to enable write operation");
 494                 return res;
 495         }
 496
 497         /*
 498           According to NVMC examples in Nordic SDK busy status must be
 499           checked after writing to NVMC_CONFIG
 500          */
 501         res = nrf51_wait_for_nvmc(chip);
 502         if (res != ERROR_OK)
 503                 LOG_ERROR("Write enable did not complete");
 504
 505         return res;
 506 }
 507
 508 static int nrf51_nvmc_read_only(struct nrf51_info *chip)
 509 {
 510         int res;
 511         res = target_write_u32(chip->target,
 512                                NRF51_NVMC_CONFIG,
 513                                NRF51_NVMC_CONFIG_REN);
 514
 515         if (res != ERROR_OK) {
 516                 LOG_ERROR("Failed to enable read-only operation");
 517                 return res;
 518         }
 519         /*
 520           According to NVMC examples in Nordic SDK busy status must be
 521           checked after writing to NVMC_CONFIG
 522          */
 523         res = nrf51_wait_for_nvmc(chip);
 524         if (res != ERROR_OK)
 525                 LOG_ERROR("Read only enable did not complete");
 526
 527         return res;
 528 }
 529
 530 static int nrf51_nvmc_generic_erase(struct nrf51_info *chip,
 531                                uint32_t erase_register, uint32_t erase_value)
 532 {
 533         int res;
 534
 535         res = nrf51_nvmc_erase_enable(chip);
 536         if (res != ERROR_OK)
 537                 goto error;
 538
 539         res = target_write_u32(chip->target,
 540                                erase_register,
 541                                erase_value);
 542         if (res != ERROR_OK)
 543                 goto set_read_only;
 544
 545         res = nrf51_wait_for_nvmc(chip);
 546         if (res != ERROR_OK)
 547                 goto set_read_only;
 548
 549         return nrf51_nvmc_read_only(chip);
 550
 551 set_read_only:
 552         nrf51_nvmc_read_only(chip);
 553 error:
 554         LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
 555                   erase_register, erase_value);
 556         return ERROR_FAIL;
 557 }
 558
 559 static int nrf51_protect_check(struct flash_bank *bank)
 560 {
 561         int res;
 562         uint32_t clenr0;
 563
 564         /* UICR cannot be write protected so just return early */
 565         if (bank->base == NRF51_UICR_BASE)
 566                 return ERROR_OK;
 567
 568         struct nrf51_info *chip = bank->driver_priv;
 569
 570         assert(chip != NULL);
 571
 572         res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
 573                               &clenr0);
 574         if (res != ERROR_OK) {
 575                 LOG_ERROR("Couldn't read code region 0 size[FICR]");
 576                 return res;
 577         }
 578
 579         if (clenr0 == 0xFFFFFFFF) {
 580                 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 581                                       &clenr0);
 582                 if (res != ERROR_OK) {
 583                         LOG_ERROR("Couldn't read code region 0 size[UICR]");
 584                         return res;
 585                 }
 586         }
 587
 588         for (int i = 0; i < bank->num_sectors; i++)
 589                 bank->sectors[i].is_protected =
 590                         clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
 591
 592         return ERROR_OK;
 593 }
 594
 595 static int nrf51_protect(struct flash_bank *bank, int set, int first, int last)
 596 {
 597         int res;
 598         uint32_t clenr0, ppfc;
 599         struct nrf51_info *chip;
 600
 601         /* UICR cannot be write protected so just bail out early */
 602         if (bank->base == NRF51_UICR_BASE)
 603                 return ERROR_FAIL;
 604
 605         res = nrf51_get_probed_chip_if_halted(bank, &chip);
 606         if (res != ERROR_OK)
 607                 return res;
 608
 609         if (first != 0) {
 610                 LOG_ERROR("Code region 0 must start at the begining of the bank");
 611                 return ERROR_FAIL;
 612         }
 613
 614         res = target_read_u32(chip->target, NRF51_FICR_PPFC,
 615                               &ppfc);
 616         if (res != ERROR_OK) {
 617                 LOG_ERROR("Couldn't read PPFC register");
 618                 return res;
 619         }
 620
 621         if ((ppfc & 0xFF) == 0x00) {
 622                 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
 623                 return ERROR_FAIL;
 624         }
 625
 626         res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 627                               &clenr0);
 628         if (res != ERROR_OK) {
 629                 LOG_ERROR("Couldn't read code region 0 size[UICR]");
 630                 return res;
 631         }
 632
 633         if (clenr0 == 0xFFFFFFFF) {
 634                 res = target_write_u32(chip->target, NRF51_UICR_CLENR0,
 635                                        clenr0);
 636                 if (res != ERROR_OK) {
 637                         LOG_ERROR("Couldn't write code region 0 size[UICR]");
 638                         return res;
 639                 }
 640
 641         } else {
 642                 LOG_ERROR("You need to perform chip erase before changing the protection settings");
 643         }
 644
 645         nrf51_protect_check(bank);
 646
 647         return ERROR_OK;
 648 }
 649
 650 static int nrf51_probe(struct flash_bank *bank)
 651 {
 652         uint32_t hwid;
 653         int res;
 654         struct nrf51_info *chip = bank->driver_priv;
 655
 656         res = target_read_u32(chip->target, NRF51_FICR_CONFIGID, &hwid);
 657         if (res != ERROR_OK) {
 658                 LOG_ERROR("Couldn't read CONFIGID register");
 659                 return res;
 660         }
 661
 662         hwid &= 0xFFFF; /* HWID is stored in the lower two
 663                          * bytes of the CONFIGID register */
 664
 665         const struct nrf51_device_spec *spec = NULL;
 666         for (size_t i = 0; i < ARRAY_SIZE(nrf51_known_devices_table); i++) {
 667                 if (hwid == nrf51_known_devices_table[i].hwid) {
 668                         spec = &nrf51_known_devices_table[i];
 669                         break;
 670                 }
 671         }
 672
 673         if (!chip->bank[0].probed && !chip->bank[1].probed) {
 674                 if (spec)
 675                         LOG_INFO("nRF%s-%s(build code: %s) %ukB Flash",
 676                                  spec->part, spec->variant, spec->build_code,
 677                                  spec->flash_size_kb);
 678                 else
 679                         LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
 680         }
 681
 682         if (bank->base == NRF51_FLASH_BASE) {
 683                 /* The value stored in NRF51_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
 684                 res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE,
 685                                 &chip->code_page_size);
 686                 if (res != ERROR_OK) {
 687                         LOG_ERROR("Couldn't read code page size");
 688                         return res;
 689                 }
 690
 691                 /* Note the register name is misleading,
 692                  * NRF51_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
 693                 uint32_t num_sectors;
 694                 res = target_read_u32(chip->target, NRF51_FICR_CODESIZE, &num_sectors);
 695                 if (res != ERROR_OK) {
 696                         LOG_ERROR("Couldn't read code memory size");
 697                         return res;
 698                 }
 699
 700                 bank->num_sectors = num_sectors;
 701                 bank->size = num_sectors * chip->code_page_size;
 702
 703                 if (spec && bank->size / 1024 != spec->flash_size_kb)
 704                         LOG_WARNING("Chip's reported Flash capacity does not match expected one");
 705
 706                 bank->sectors = calloc(bank->num_sectors,
 707                                        sizeof((bank->sectors)[0]));
 708                 if (!bank->sectors)
 709                         return ERROR_FLASH_BANK_NOT_PROBED;
 710
 711                 /* Fill out the sector information: all NRF51 sectors are the same size and
 712                  * there is always a fixed number of them. */
 713                 for (int i = 0; i < bank->num_sectors; i++) {
 714                         bank->sectors[i].size = chip->code_page_size;
 715                         bank->sectors[i].offset = i * chip->code_page_size;
 716
 717                         /* mark as unknown */
 718                         bank->sectors[i].is_erased = -1;
 719                         bank->sectors[i].is_protected = -1;
 720                 }
 721
 722                 nrf51_protect_check(bank);
 723
 724                 chip->bank[0].probed = true;
 725         } else {
 726                 bank->size = NRF51_UICR_SIZE;
 727                 bank->num_sectors = 1;
 728                 bank->sectors = calloc(bank->num_sectors,
 729                                        sizeof((bank->sectors)[0]));
 730                 if (!bank->sectors)
 731                         return ERROR_FLASH_BANK_NOT_PROBED;
 732
 733                 bank->sectors[0].size = bank->size;
 734                 bank->sectors[0].offset = 0;
 735
 736                 /* mark as unknown */
 737                 bank->sectors[0].is_erased = 0;
 738                 bank->sectors[0].is_protected = 0;
 739
 740                 chip->bank[1].probed = true;
 741         }
 742
 743         return ERROR_OK;
 744 }
 745
 746 static int nrf51_auto_probe(struct flash_bank *bank)
 747 {
 748         int probed = nrf51_bank_is_probed(bank);
 749
 750         if (probed < 0)
 751                 return probed;
 752         else if (probed)
 753                 return ERROR_OK;
 754         else
 755                 return nrf51_probe(bank);
 756 }
 757
 758 static struct flash_sector *nrf51_find_sector_by_address(struct flash_bank *bank, uint32_t address)
 759 {
 760         struct nrf51_info *chip = bank->driver_priv;
 761
 762         for (int i = 0; i < bank->num_sectors; i++)
 763                 if (bank->sectors[i].offset <= address &&
 764                     address < (bank->sectors[i].offset + chip->code_page_size))
 765                         return &bank->sectors[i];
 766         return NULL;
 767 }
 768
 769 static int nrf51_erase_all(struct nrf51_info *chip)
 770 {
 771         LOG_DEBUG("Erasing all non-volatile memory");
 772         return nrf51_nvmc_generic_erase(chip,
 773                                         NRF51_NVMC_ERASEALL,
 774                                         0x00000001);
 775 }
 776
 777 static int nrf51_erase_page(struct flash_bank *bank,
 778                                                         struct nrf51_info *chip,
 779                                                         struct flash_sector *sector)
 780 {
 781         int res;
 782
 783         LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
 784         if (sector->is_protected) {
 785                 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
 786                 return ERROR_FAIL;
 787         }
 788
 789         if (bank->base == NRF51_UICR_BASE) {
 790                 uint32_t ppfc;
 791                 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
 792                                       &ppfc);
 793                 if (res != ERROR_OK) {
 794                         LOG_ERROR("Couldn't read PPFC register");
 795                         return res;
 796                 }
 797
 798                 if ((ppfc & 0xFF) == 0xFF) {
 799                         /* We can't erase the UICR.  Double-check to
 800                            see if it's already erased before complaining. */
 801                         default_flash_blank_check(bank);
 802                         if (sector->is_erased == 1)
 803                                 return ERROR_OK;
 804
 805                         LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
 806                         return ERROR_FAIL;
 807                 }
 808
 809                 res = nrf51_nvmc_generic_erase(chip,
 810                                                NRF51_NVMC_ERASEUICR,
 811                                                0x00000001);
 812
 813
 814         } else {
 815                 res = nrf51_nvmc_generic_erase(chip,
 816                                                NRF51_NVMC_ERASEPAGE,
 817                                                sector->offset);
 818         }
 819
 820         if (res == ERROR_OK)
 821                 sector->is_erased = 1;
 822
 823         return res;
 824 }
 825
 826 static const uint8_t nrf51_flash_write_code[] = {
 827         /* See contrib/loaders/flash/cortex-m0.S */
 828 /* <wait_fifo>: */
 829         0x0d, 0x68,             /* ldr  r5,     [r1,    #0] */
 830         0x00, 0x2d,             /* cmp  r5,     #0 */
 831         0x0b, 0xd0,             /* beq.n        1e <exit> */
 832         0x4c, 0x68,             /* ldr  r4,     [r1,    #4] */
 833         0xac, 0x42,             /* cmp  r4,     r5 */
 834         0xf9, 0xd0,             /* beq.n        0 <wait_fifo> */
 835         0x20, 0xcc,             /* ldmia        r4!,    {r5} */
 836         0x20, 0xc3,             /* stmia        r3!,    {r5} */
 837         0x94, 0x42,             /* cmp  r4,     r2 */
 838         0x01, 0xd3,             /* bcc.n        18 <no_wrap> */
 839         0x0c, 0x46,             /* mov  r4,     r1 */
 840         0x08, 0x34,             /* adds r4,     #8 */
 841 /* <no_wrap>: */
 842         0x4c, 0x60,             /* str  r4, [r1,        #4] */
 843         0x04, 0x38,             /* subs r0, #4 */
 844         0xf0, 0xd1,             /* bne.n        0 <wait_fifo> */
 845 /* <exit>: */
 846         0x00, 0xbe              /* bkpt 0x0000 */
 847 };
 848
 849
 850 /* Start a low level flash write for the specified region */
 851 static int nrf51_ll_flash_write(struct nrf51_info *chip, uint32_t offset, const uint8_t *buffer, uint32_t bytes)
 852 {
 853         struct target *target = chip->target;
 854         uint32_t buffer_size = 8192;
 855         struct working_area *write_algorithm;
 856         struct working_area *source;
 857         uint32_t address = NRF51_FLASH_BASE + offset;
 858         struct reg_param reg_params[4];
 859         struct armv7m_algorithm armv7m_info;
 860         int retval = ERROR_OK;
 861
 862
 863         LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32" bytes=0x%"PRIx32, offset, bytes);
 864         assert(bytes % 4 == 0);
 865
 866         /* allocate working area with flash programming code */
 867         if (target_alloc_working_area(target, sizeof(nrf51_flash_write_code),
 868                         &write_algorithm) != ERROR_OK) {
 869                 LOG_WARNING("no working area available, falling back to slow memory writes");
 870
 871                 for (; bytes > 0; bytes -= 4) {
 872                         retval = target_write_memory(chip->target, offset, 4, 1, buffer);
 873                         if (retval != ERROR_OK)
 874                                 return retval;
 875
 876                         retval = nrf51_wait_for_nvmc(chip);
 877                         if (retval != ERROR_OK)
 878                                 return retval;
 879
 880                         offset += 4;
 881                         buffer += 4;
 882                 }
 883
 884                 return ERROR_OK;
 885         }
 886
 887         LOG_WARNING("using fast async flash loader. This is currently supported");
 888         LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
 889         LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg to disable it");
 890
 891         retval = target_write_buffer(target, write_algorithm->address,
 892                                 sizeof(nrf51_flash_write_code),
 893                                 nrf51_flash_write_code);
 894         if (retval != ERROR_OK)
 895                 return retval;
 896
 897         /* memory buffer */
 898         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
 899                 buffer_size /= 2;
 900                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 901                 if (buffer_size <= 256) {
 902                         /* free working area, write algorithm already allocated */
 903                         target_free_working_area(target, write_algorithm);
 904
 905                         LOG_WARNING("No large enough working area available, can't do block memory writes");
 906                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 907                 }
 908         }
 909
 910         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 911         armv7m_info.core_mode = ARM_MODE_THREAD;
 912
 913         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
 914         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* buffer start */
 915         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer end */
 916         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
 917
 918         buf_set_u32(reg_params[0].value, 0, 32, bytes);
 919         buf_set_u32(reg_params[1].value, 0, 32, source->address);
 920         buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
 921         buf_set_u32(reg_params[3].value, 0, 32, address);
 922
 923         retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
 924                         0, NULL,
 925                         4, reg_params,
 926                         source->address, source->size,
 927                         write_algorithm->address, 0,
 928                         &armv7m_info);
 929
 930         target_free_working_area(target, source);
 931         target_free_working_area(target, write_algorithm);
 932
 933         destroy_reg_param(&reg_params[0]);
 934         destroy_reg_param(&reg_params[1]);
 935         destroy_reg_param(&reg_params[2]);
 936         destroy_reg_param(&reg_params[3]);
 937
 938         return retval;
 939 }
 940
 941 /* Check and erase flash sectors in specified range then start a low level page write.
 942    start/end must be sector aligned.
 943 */
 944 static int nrf51_write_pages(struct flash_bank *bank, uint32_t start, uint32_t end, const uint8_t *buffer)
 945 {
 946         int res = ERROR_FAIL;
 947         struct nrf51_info *chip = bank->driver_priv;
 948         struct flash_sector *sector;
 949         uint32_t offset;
 950
 951         assert(start % chip->code_page_size == 0);
 952         assert(end % chip->code_page_size == 0);
 953
 954         /* Erase all sectors */
 955         for (offset = start; offset < end; offset += chip->code_page_size) {
 956                 sector = nrf51_find_sector_by_address(bank, offset);
 957                 if (!sector) {
 958                         LOG_ERROR("Invalid sector @ 0x%08"PRIx32, offset);
 959                         return ERROR_FLASH_SECTOR_INVALID;
 960                 }
 961
 962                 if (sector->is_protected) {
 963                         LOG_ERROR("Can't erase protected sector @ 0x%08"PRIx32, offset);
 964                         goto error;
 965                 }
 966
 967                 if (sector->is_erased != 1) {   /* 1 = erased, 0= not erased, -1 = unknown */
 968                         res = nrf51_erase_page(bank, chip, sector);
 969                         if (res != ERROR_OK) {
 970                                 LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32, sector->offset);
 971                                 goto error;
 972                         }
 973                 }
 974                 sector->is_erased = 0;
 975         }
 976
 977         res = nrf51_nvmc_write_enable(chip);
 978         if (res != ERROR_OK)
 979                 goto error;
 980
 981         res = nrf51_ll_flash_write(chip, start, buffer, (end - start));
 982         if (res != ERROR_OK)
 983                 goto set_read_only;
 984
 985         return nrf51_nvmc_read_only(chip);
 986
 987 set_read_only:
 988         nrf51_nvmc_read_only(chip);
 989 error:
 990         LOG_ERROR("Failed to write to nrf51 flash");
 991         return res;
 992 }
 993
 994 static int nrf51_erase(struct flash_bank *bank, int first, int last)
 995 {
 996         int res;
 997         struct nrf51_info *chip;
 998
 999         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1000         if (res != ERROR_OK)
1001                 return res;
1002
1003         /* For each sector to be erased */
1004         for (int s = first; s <= last && res == ERROR_OK; s++)
1005                 res = nrf51_erase_page(bank, chip, &bank->sectors[s]);
1006
1007         return res;
1008 }
1009
1010 static int nrf51_code_flash_write(struct flash_bank *bank,
1011                                   struct nrf51_info *chip,
1012                                   const uint8_t *buffer, uint32_t offset, uint32_t count)
1013 {
1014
1015         int res;
1016         /* Need to perform reads to fill any gaps we need to preserve in the first page,
1017            before the start of buffer, or in the last page, after the end of buffer */
1018         uint32_t first_page = offset/chip->code_page_size;
1019         uint32_t last_page = DIV_ROUND_UP(offset+count, chip->code_page_size);
1020
1021         uint32_t first_page_offset = first_page * chip->code_page_size;
1022         uint32_t last_page_offset = last_page * chip->code_page_size;
1023
1024         LOG_DEBUG("Padding write from 0x%08"PRIx32"-0x%08"PRIx32" as 0x%08"PRIx32"-0x%08"PRIx32,
1025                 offset, offset+count, first_page_offset, last_page_offset);
1026
1027         uint32_t page_cnt = last_page - first_page;
1028         uint8_t buffer_to_flash[page_cnt*chip->code_page_size];
1029
1030         /* Fill in any space between start of first page and start of buffer */
1031         uint32_t pre = offset - first_page_offset;
1032         if (pre > 0) {
1033                 res = target_read_memory(bank->target,
1034                                         first_page_offset,
1035                                         1,
1036                                         pre,
1037                                         buffer_to_flash);
1038                 if (res != ERROR_OK)
1039                         return res;
1040         }
1041
1042         /* Fill in main contents of buffer */
1043         memcpy(buffer_to_flash+pre, buffer, count);
1044
1045         /* Fill in any space between end of buffer and end of last page */
1046         uint32_t post = last_page_offset - (offset+count);
1047         if (post > 0) {
1048                 /* Retrieve the full row contents from Flash */
1049                 res = target_read_memory(bank->target,
1050                                         offset + count,
1051                                         1,
1052                                         post,
1053                                         buffer_to_flash+pre+count);
1054                 if (res != ERROR_OK)
1055                         return res;
1056         }
1057
1058         return nrf51_write_pages(bank, first_page_offset, last_page_offset, buffer_to_flash);
1059 }
1060
1061 static int nrf51_uicr_flash_write(struct flash_bank *bank,
1062                                   struct nrf51_info *chip,
1063                                   const uint8_t *buffer, uint32_t offset, uint32_t count)
1064 {
1065         int res;
1066         uint8_t uicr[NRF51_UICR_SIZE];
1067         struct flash_sector *sector = &bank->sectors[0];
1068
1069         if ((offset + count) > NRF51_UICR_SIZE)
1070                 return ERROR_FAIL;
1071
1072         res = target_read_memory(bank->target,
1073                                  NRF51_UICR_BASE,
1074                                  1,
1075                                  NRF51_UICR_SIZE,
1076                                  uicr);
1077
1078         if (res != ERROR_OK)
1079                 return res;
1080
1081         if (sector->is_erased != 1) {
1082                 res = nrf51_erase_page(bank, chip, sector);
1083                 if (res != ERROR_OK)
1084                         return res;
1085         }
1086
1087         res = nrf51_nvmc_write_enable(chip);
1088         if (res != ERROR_OK)
1089                 return res;
1090
1091         memcpy(&uicr[offset], buffer, count);
1092
1093         res = nrf51_ll_flash_write(chip, NRF51_UICR_BASE, uicr, NRF51_UICR_SIZE);
1094         if (res != ERROR_OK) {
1095                 nrf51_nvmc_read_only(chip);
1096                 return res;
1097         }
1098
1099         return nrf51_nvmc_read_only(chip);
1100 }
1101
1102
1103 static int nrf51_write(struct flash_bank *bank, const uint8_t *buffer,
1104                        uint32_t offset, uint32_t count)
1105 {
1106         int res;
1107         struct nrf51_info *chip;
1108
1109         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1110         if (res != ERROR_OK)
1111                 return res;
1112
1113         return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, count);
1114 }
1115
1116
1117 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command)
1118 {
1119         static struct nrf51_info *chip;
1120
1121         switch (bank->base) {
1122         case NRF51_FLASH_BASE:
1123                 bank->bank_number = 0;
1124                 break;
1125         case NRF51_UICR_BASE:
1126                 bank->bank_number = 1;
1127                 break;
1128         default:
1129                 LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
1130                 return ERROR_FAIL;
1131         }
1132
1133         if (!chip) {
1134                 /* Create a new chip */
1135                 chip = calloc(1, sizeof(*chip));
1136                 if (!chip)
1137                         return ERROR_FAIL;
1138
1139                 chip->target = bank->target;
1140         }
1141
1142         switch (bank->base) {
1143         case NRF51_FLASH_BASE:
1144                 chip->bank[bank->bank_number].write = nrf51_code_flash_write;
1145                 break;
1146         case NRF51_UICR_BASE:
1147                 chip->bank[bank->bank_number].write = nrf51_uicr_flash_write;
1148                 break;
1149         }
1150
1151         chip->bank[bank->bank_number].probed = false;
1152         bank->driver_priv = chip;
1153
1154         return ERROR_OK;
1155 }
1156
1157 COMMAND_HANDLER(nrf51_handle_mass_erase_command)
1158 {
1159         int res;
1160         struct flash_bank *bank = NULL;
1161         struct target *target = get_current_target(CMD_CTX);
1162
1163         res = get_flash_bank_by_addr(target, NRF51_FLASH_BASE, true, &bank);
1164         if (res != ERROR_OK)
1165                 return res;
1166
1167         assert(bank != NULL);
1168
1169         struct nrf51_info *chip;
1170
1171         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1172         if (res != ERROR_OK)
1173                 return res;
1174
1175         uint32_t ppfc;
1176
1177         res = target_read_u32(target, NRF51_FICR_PPFC,
1178                               &ppfc);
1179         if (res != ERROR_OK) {
1180                 LOG_ERROR("Couldn't read PPFC register");
1181                 return res;
1182         }
1183
1184         if ((ppfc & 0xFF) == 0x00) {
1185                 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1186                           "mass erase command won't work.");
1187                 return ERROR_FAIL;
1188         }
1189
1190         res = nrf51_erase_all(chip);
1191         if (res != ERROR_OK) {
1192                 LOG_ERROR("Failed to erase the chip");
1193                 nrf51_protect_check(bank);
1194                 return res;
1195         }
1196
1197         for (int i = 0; i < bank->num_sectors; i++)
1198                 bank->sectors[i].is_erased = 1;
1199
1200         res = nrf51_protect_check(bank);
1201         if (res != ERROR_OK) {
1202                 LOG_ERROR("Failed to check chip's write protection");
1203                 return res;
1204         }
1205
1206         res = get_flash_bank_by_addr(target, NRF51_UICR_BASE, true, &bank);
1207         if (res != ERROR_OK)
1208                 return res;
1209
1210         bank->sectors[0].is_erased = 1;
1211
1212         return ERROR_OK;
1213 }
1214
1215 static int nrf51_info(struct flash_bank *bank, char *buf, int buf_size)
1216 {
1217         int res;
1218
1219         struct nrf51_info *chip;
1220
1221         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1222         if (res != ERROR_OK)
1223                 return res;
1224
1225         static struct {
1226                 const uint32_t address;
1227                 uint32_t value;
1228         } ficr[] = {
1229                 { .address = NRF51_FICR_CODEPAGESIZE    },
1230                 { .address = NRF51_FICR_CODESIZE        },
1231                 { .address = NRF51_FICR_CLENR0          },
1232                 { .address = NRF51_FICR_PPFC            },
1233                 { .address = NRF51_FICR_NUMRAMBLOCK     },
1234                 { .address = NRF51_FICR_SIZERAMBLOCK0   },
1235                 { .address = NRF51_FICR_SIZERAMBLOCK1   },
1236                 { .address = NRF51_FICR_SIZERAMBLOCK2   },
1237                 { .address = NRF51_FICR_SIZERAMBLOCK3   },
1238                 { .address = NRF51_FICR_CONFIGID        },
1239                 { .address = NRF51_FICR_DEVICEID0       },
1240                 { .address = NRF51_FICR_DEVICEID1       },
1241                 { .address = NRF51_FICR_ER0             },
1242                 { .address = NRF51_FICR_ER1             },
1243                 { .address = NRF51_FICR_ER2             },
1244                 { .address = NRF51_FICR_ER3             },
1245                 { .address = NRF51_FICR_IR0             },
1246                 { .address = NRF51_FICR_IR1             },
1247                 { .address = NRF51_FICR_IR2             },
1248                 { .address = NRF51_FICR_IR3             },
1249                 { .address = NRF51_FICR_DEVICEADDRTYPE  },
1250                 { .address = NRF51_FICR_DEVICEADDR0     },
1251                 { .address = NRF51_FICR_DEVICEADDR1     },
1252                 { .address = NRF51_FICR_OVERRIDEN       },
1253                 { .address = NRF51_FICR_NRF_1MBIT0      },
1254                 { .address = NRF51_FICR_NRF_1MBIT1      },
1255                 { .address = NRF51_FICR_NRF_1MBIT2      },
1256                 { .address = NRF51_FICR_NRF_1MBIT3      },
1257                 { .address = NRF51_FICR_NRF_1MBIT4      },
1258                 { .address = NRF51_FICR_BLE_1MBIT0      },
1259                 { .address = NRF51_FICR_BLE_1MBIT1      },
1260                 { .address = NRF51_FICR_BLE_1MBIT2      },
1261                 { .address = NRF51_FICR_BLE_1MBIT3      },
1262                 { .address = NRF51_FICR_BLE_1MBIT4      },
1263         }, uicr[] = {
1264                 { .address = NRF51_UICR_CLENR0,         },
1265                 { .address = NRF51_UICR_RBPCONF         },
1266                 { .address = NRF51_UICR_XTALFREQ        },
1267                 { .address = NRF51_UICR_FWID            },
1268         };
1269
1270         for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1271                 res = target_read_u32(chip->target, ficr[i].address,
1272                                       &ficr[i].value);
1273                 if (res != ERROR_OK) {
1274                         LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1275                         return res;
1276                 }
1277         }
1278
1279         for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1280                 res = target_read_u32(chip->target, uicr[i].address,
1281                                       &uicr[i].value);
1282                 if (res != ERROR_OK) {
1283                         LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1284                         return res;
1285                 }
1286         }
1287
1288         snprintf(buf, buf_size,
1289                  "\n[factory information control block]\n\n"
1290                  "code page size: %"PRIu32"B\n"
1291                  "code memory size: %"PRIu32"kB\n"
1292                  "code region 0 size: %"PRIu32"kB\n"
1293                  "pre-programmed code: %s\n"
1294                  "number of ram blocks: %"PRIu32"\n"
1295                  "ram block 0 size: %"PRIu32"B\n"
1296                  "ram block 1 size: %"PRIu32"B\n"
1297                  "ram block 2 size: %"PRIu32"B\n"
1298                  "ram block 3 size: %"PRIu32 "B\n"
1299                  "config id: %" PRIx32 "\n"
1300                  "device id: 0x%"PRIx32"%08"PRIx32"\n"
1301                  "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1302                  "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1303                  "device address type: 0x%"PRIx32"\n"
1304                  "device address: 0x%"PRIx32"%08"PRIx32"\n"
1305                  "override enable: %"PRIx32"\n"
1306                  "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1307                  "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1308                  "\n[user information control block]\n\n"
1309                  "code region 0 size: %"PRIu32"kB\n"
1310                  "read back protection configuration: %"PRIx32"\n"
1311                  "reset value for XTALFREQ: %"PRIx32"\n"
1312                  "firmware id: 0x%04"PRIx32,
1313                  ficr[0].value,
1314                  (ficr[1].value * ficr[0].value) / 1024,
1315                  (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1316                  ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1317                  ficr[4].value,
1318                  ficr[5].value,
1319                  (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1320                  (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1321                  (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1322                  ficr[9].value,
1323                  ficr[10].value, ficr[11].value,
1324                  ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1325                  ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1326                  ficr[20].value,
1327                  ficr[21].value, ficr[22].value,
1328                  ficr[23].value,
1329                  ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1330                  ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1331                  (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1332                  uicr[1].value & 0xFFFF,
1333                  uicr[2].value & 0xFF,
1334                  uicr[3].value & 0xFFFF);
1335
1336         return ERROR_OK;
1337 }
1338
1339 static const struct command_registration nrf51_exec_command_handlers[] = {
1340         {
1341                 .name           = "mass_erase",
1342                 .handler        = nrf51_handle_mass_erase_command,
1343                 .mode           = COMMAND_EXEC,
1344                 .help           = "Erase all flash contents of the chip.",
1345         },
1346         COMMAND_REGISTRATION_DONE
1347 };
1348
1349 static const struct command_registration nrf51_command_handlers[] = {
1350         {
1351                 .name   = "nrf51",
1352                 .mode   = COMMAND_ANY,
1353                 .help   = "nrf51 flash command group",
1354                 .usage  = "",
1355                 .chain  = nrf51_exec_command_handlers,
1356         },
1357         COMMAND_REGISTRATION_DONE
1358 };
1359
1360 struct flash_driver nrf51_flash = {
1361         .name                   = "nrf51",
1362         .commands               = nrf51_command_handlers,
1363         .flash_bank_command     = nrf51_flash_bank_command,
1364         .info                   = nrf51_info,
1365         .erase                  = nrf51_erase,
1366         .protect                = nrf51_protect,
1367         .write                  = nrf51_write,
1368         .read                   = default_flash_read,
1369         .probe                  = nrf51_probe,
1370         .auto_probe             = nrf51_auto_probe,
1371         .erase_check            = default_flash_blank_check,
1372         .protect_check          = nrf51_protect_check,
1373 };