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   1 /***************************************************************************
   2  *   Copyright (C) 2013 Synapse Product Development                        *
   3  *   Andrey Smirnov <andrew.smironv@gmail.com>                             *
   4  *   Angus Gratton <gus@projectgus.com>                                    *
   5  *   Erdem U. Altunyurt <spamjunkeater@gmail.com>                          *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include "imp.h"
  26 #include <target/algorithm.h>
  27 #include <target/armv7m.h>
  28 #include <helper/types.h>
  29
  30 enum {
  31         NRF51_FLASH_BASE = 0x00000000,
  32 };
  33
  34 enum nrf51_ficr_registers {
  35         NRF51_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
  36
  37 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
  38
  39         NRF51_FICR_CODEPAGESIZE         = NRF51_FICR_REG(0x010),
  40         NRF51_FICR_CODESIZE             = NRF51_FICR_REG(0x014),
  41         NRF51_FICR_CLENR0               = NRF51_FICR_REG(0x028),
  42         NRF51_FICR_PPFC                 = NRF51_FICR_REG(0x02C),
  43         NRF51_FICR_NUMRAMBLOCK          = NRF51_FICR_REG(0x034),
  44         NRF51_FICR_SIZERAMBLOCK0        = NRF51_FICR_REG(0x038),
  45         NRF51_FICR_SIZERAMBLOCK1        = NRF51_FICR_REG(0x03C),
  46         NRF51_FICR_SIZERAMBLOCK2        = NRF51_FICR_REG(0x040),
  47         NRF51_FICR_SIZERAMBLOCK3        = NRF51_FICR_REG(0x044),
  48         NRF51_FICR_CONFIGID             = NRF51_FICR_REG(0x05C),
  49         NRF51_FICR_DEVICEID0            = NRF51_FICR_REG(0x060),
  50         NRF51_FICR_DEVICEID1            = NRF51_FICR_REG(0x064),
  51         NRF51_FICR_ER0                  = NRF51_FICR_REG(0x080),
  52         NRF51_FICR_ER1                  = NRF51_FICR_REG(0x084),
  53         NRF51_FICR_ER2                  = NRF51_FICR_REG(0x088),
  54         NRF51_FICR_ER3                  = NRF51_FICR_REG(0x08C),
  55         NRF51_FICR_IR0                  = NRF51_FICR_REG(0x090),
  56         NRF51_FICR_IR1                  = NRF51_FICR_REG(0x094),
  57         NRF51_FICR_IR2                  = NRF51_FICR_REG(0x098),
  58         NRF51_FICR_IR3                  = NRF51_FICR_REG(0x09C),
  59         NRF51_FICR_DEVICEADDRTYPE       = NRF51_FICR_REG(0x0A0),
  60         NRF51_FICR_DEVICEADDR0          = NRF51_FICR_REG(0x0A4),
  61         NRF51_FICR_DEVICEADDR1          = NRF51_FICR_REG(0x0A8),
  62         NRF51_FICR_OVERRIDEN            = NRF51_FICR_REG(0x0AC),
  63         NRF51_FICR_NRF_1MBIT0           = NRF51_FICR_REG(0x0B0),
  64         NRF51_FICR_NRF_1MBIT1           = NRF51_FICR_REG(0x0B4),
  65         NRF51_FICR_NRF_1MBIT2           = NRF51_FICR_REG(0x0B8),
  66         NRF51_FICR_NRF_1MBIT3           = NRF51_FICR_REG(0x0BC),
  67         NRF51_FICR_NRF_1MBIT4           = NRF51_FICR_REG(0x0C0),
  68         NRF51_FICR_BLE_1MBIT0           = NRF51_FICR_REG(0x0EC),
  69         NRF51_FICR_BLE_1MBIT1           = NRF51_FICR_REG(0x0F0),
  70         NRF51_FICR_BLE_1MBIT2           = NRF51_FICR_REG(0x0F4),
  71         NRF51_FICR_BLE_1MBIT3           = NRF51_FICR_REG(0x0F8),
  72         NRF51_FICR_BLE_1MBIT4           = NRF51_FICR_REG(0x0FC),
  73 };
  74
  75 enum nrf51_uicr_registers {
  76         NRF51_UICR_BASE = 0x10001000, /* User Information
  77                                        * Configuration Regsters */
  78
  79         NRF51_UICR_SIZE = 0x100,
  80
  81 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
  82
  83         NRF51_UICR_CLENR0       = NRF51_UICR_REG(0x000),
  84         NRF51_UICR_RBPCONF      = NRF51_UICR_REG(0x004),
  85         NRF51_UICR_XTALFREQ     = NRF51_UICR_REG(0x008),
  86         NRF51_UICR_FWID         = NRF51_UICR_REG(0x010),
  87 };
  88
  89 enum nrf51_nvmc_registers {
  90         NRF51_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
  91                                        * Controller Regsters */
  92
  93 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
  94
  95         NRF51_NVMC_READY        = NRF51_NVMC_REG(0x400),
  96         NRF51_NVMC_CONFIG       = NRF51_NVMC_REG(0x504),
  97         NRF51_NVMC_ERASEPAGE    = NRF51_NVMC_REG(0x508),
  98         NRF51_NVMC_ERASEALL     = NRF51_NVMC_REG(0x50C),
  99         NRF51_NVMC_ERASEUICR    = NRF51_NVMC_REG(0x514),
 100 };
 101
 102 enum nrf51_nvmc_config_bits {
 103         NRF51_NVMC_CONFIG_REN = 0x00,
 104         NRF51_NVMC_CONFIG_WEN = 0x01,
 105         NRF51_NVMC_CONFIG_EEN = 0x02,
 106
 107 };
 108
 109 struct nrf51_info {
 110         uint32_t code_page_size;
 111         uint32_t code_memory_size;
 112
 113         struct {
 114                 bool probed;
 115                 int (*write) (struct flash_bank *bank,
 116                               struct nrf51_info *chip,
 117                               const uint8_t *buffer, uint32_t offset, uint32_t count);
 118         } bank[2];
 119         struct target *target;
 120 };
 121
 122 struct nrf51_device_spec {
 123         uint16_t hwid;
 124         const char *variant;
 125         const char *build_code;
 126         unsigned int flash_size_kb;
 127 };
 128
 129 /* The known devices table below is derived from the "nRF51 Series
 130  * Compatibility Matrix" document, which can be found by searching for
 131  * ATTN-51 on the Nordic Semi website:
 132  *
 133  * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
 134  *
 135  * Up to date with Matrix v2.0, plus some additional HWIDs.
 136  *
 137  * The additional HWIDs apply where the build code in the matrix is
 138  * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
 139  * for x==0, x!=0 means different (unspecified) HWIDs.
 140  */
 141 static const struct nrf51_device_spec nrf51_known_devices_table[] = {
 142         /* nRF51822 Devices (IC rev 1). */
 143         {
 144                 .hwid           = 0x001D,
 145                 .variant        = "QFAA",
 146                 .build_code     = "CA/C0",
 147                 .flash_size_kb  = 256,
 148         },
 149         {
 150                 .hwid           = 0x0026,
 151                 .variant        = "QFAB",
 152                 .build_code     = "AA",
 153                 .flash_size_kb  = 128,
 154         },
 155         {
 156                 .hwid           = 0x0027,
 157                 .variant        = "QFAB",
 158                 .build_code     = "A0",
 159                 .flash_size_kb  = 128,
 160         },
 161         {
 162                 .hwid           = 0x0020,
 163                 .variant        = "CEAA",
 164                 .build_code     = "BA",
 165                 .flash_size_kb  = 256,
 166         },
 167         {
 168                 .hwid           = 0x002F,
 169                 .variant        = "CEAA",
 170                 .build_code     = "B0",
 171                 .flash_size_kb  = 256,
 172         },
 173
 174         /* nRF51822 Devices (IC rev 2). */
 175         {
 176                 .hwid           = 0x002A,
 177                 .variant        = "QFAA",
 178                 .build_code     = "FA0",
 179                 .flash_size_kb  = 256,
 180         },
 181         {
 182                 .hwid           = 0x0044,
 183                 .variant        = "QFAA",
 184                 .build_code     = "GC0",
 185                 .flash_size_kb  = 256,
 186         },
 187         {
 188                 .hwid           = 0x003C,
 189                 .variant        = "QFAA",
 190                 .build_code     = "G0",
 191                 .flash_size_kb  = 256,
 192         },
 193         {
 194                 .hwid           = 0x0057,
 195                 .variant        = "QFAA",
 196                 .build_code     = "G2",
 197                 .flash_size_kb  = 256,
 198         },
 199         {
 200                 .hwid           = 0x0058,
 201                 .variant        = "QFAA",
 202                 .build_code     = "G3",
 203                 .flash_size_kb  = 256,
 204         },
 205         {
 206                 .hwid           = 0x004C,
 207                 .variant        = "QFAB",
 208                 .build_code     = "B0",
 209                 .flash_size_kb  = 128,
 210         },
 211         {
 212                 .hwid           = 0x0040,
 213                 .variant        = "CEAA",
 214                 .build_code     = "CA0",
 215                 .flash_size_kb  = 256,
 216         },
 217         {
 218                 .hwid           = 0x0047,
 219                 .variant        = "CEAA",
 220                 .build_code     = "DA0",
 221                 .flash_size_kb  = 256,
 222         },
 223         {
 224                 .hwid           = 0x004D,
 225                 .variant        = "CEAA",
 226                 .build_code     = "D00",
 227                 .flash_size_kb  = 256,
 228         },
 229
 230         /* nRF51822 Devices (IC rev 3). */
 231         {
 232                 .hwid           = 0x0072,
 233                 .variant        = "QFAA",
 234                 .build_code     = "H0",
 235                 .flash_size_kb  = 256,
 236         },
 237         {
 238                 .hwid           = 0x007B,
 239                 .variant        = "QFAB",
 240                 .build_code     = "C0",
 241                 .flash_size_kb  = 128,
 242         },
 243         {
 244                 .hwid           = 0x0083,
 245                 .variant        = "QFAC",
 246                 .build_code     = "A0",
 247                 .flash_size_kb  = 256,
 248         },
 249         {
 250                 .hwid           = 0x0084,
 251                 .variant        = "QFAC",
 252                 .build_code     = "A1",
 253                 .flash_size_kb  = 256,
 254         },
 255         {
 256                 .hwid           = 0x007D,
 257                 .variant        = "CDAB",
 258                 .build_code     = "A0",
 259                 .flash_size_kb  = 128,
 260         },
 261         {
 262                 .hwid           = 0x0079,
 263                 .variant        = "CEAA",
 264                 .build_code     = "E0",
 265                 .flash_size_kb  = 256,
 266         },
 267         {
 268                 .hwid           = 0x0087,
 269                 .variant        = "CFAC",
 270                 .build_code     = "A0",
 271                 .flash_size_kb  = 256,
 272         },
 273
 274         /* nRF51422 Devices (IC rev 1). */
 275         {
 276                 .hwid           = 0x001E,
 277                 .variant        = "QFAA",
 278                 .build_code     = "CA",
 279                 .flash_size_kb  = 256,
 280         },
 281         {
 282                 .hwid           = 0x0024,
 283                 .variant        = "QFAA",
 284                 .build_code     = "C0",
 285                 .flash_size_kb  = 256,
 286         },
 287         {
 288                 .hwid           = 0x0031,
 289                 .variant        = "CEAA",
 290                 .build_code     = "A0A",
 291                 .flash_size_kb  = 256,
 292         },
 293
 294         /* nRF51422 Devices (IC rev 2). */
 295         {
 296                 .hwid           = 0x002D,
 297                 .variant        = "QFAA",
 298                 .build_code     = "DAA",
 299                 .flash_size_kb  = 256,
 300         },
 301         {
 302                 .hwid           = 0x002E,
 303                 .variant        = "QFAA",
 304                 .build_code     = "E0",
 305                 .flash_size_kb  = 256,
 306         },
 307         {
 308                 .hwid           = 0x0061,
 309                 .variant        = "QFAB",
 310                 .build_code     = "A00",
 311                 .flash_size_kb  = 128,
 312         },
 313         {
 314                 .hwid           = 0x0050,
 315                 .variant        = "CEAA",
 316                 .build_code     = "B0",
 317                 .flash_size_kb  = 256,
 318         },
 319
 320         /* nRF51422 Devices (IC rev 3). */
 321         {
 322                 .hwid           = 0x0073,
 323                 .variant        = "QFAA",
 324                 .build_code     = "F0",
 325                 .flash_size_kb  = 256,
 326         },
 327         {
 328                 .hwid           = 0x007C,
 329                 .variant        = "QFAB",
 330                 .build_code     = "B0",
 331                 .flash_size_kb  = 128,
 332         },
 333         {
 334                 .hwid           = 0x0085,
 335                 .variant        = "QFAC",
 336                 .build_code     = "A0",
 337                 .flash_size_kb  = 256,
 338         },
 339         {
 340                 .hwid           = 0x0086,
 341                 .variant        = "QFAC",
 342                 .build_code     = "A1",
 343                 .flash_size_kb  = 256,
 344         },
 345         {
 346                 .hwid           = 0x007E,
 347                 .variant        = "CDAB",
 348                 .build_code     = "A0",
 349                 .flash_size_kb  = 128,
 350         },
 351         {
 352                 .hwid           = 0x007A,
 353                 .variant        = "CEAA",
 354                 .build_code     = "C0",
 355                 .flash_size_kb  = 256,
 356         },
 357         {
 358                 .hwid           = 0x0088,
 359                 .variant        = "CFAC",
 360                 .build_code     = "A0",
 361                 .flash_size_kb  = 256,
 362         },
 363
 364         /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
 365            with built-in jlink seem to use engineering samples not listed
 366            in the nRF51 Series Compatibility Matrix V1.0. */
 367         {
 368                 .hwid           = 0x0071,
 369                 .variant        = "QFAC",
 370                 .build_code     = "AB",
 371                 .flash_size_kb  = 256,
 372         },
 373 };
 374
 375 static int nrf51_bank_is_probed(struct flash_bank *bank)
 376 {
 377         struct nrf51_info *chip = bank->driver_priv;
 378
 379         assert(chip != NULL);
 380
 381         return chip->bank[bank->bank_number].probed;
 382 }
 383 static int nrf51_probe(struct flash_bank *bank);
 384
 385 static int nrf51_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf51_info **chip)
 386 {
 387         if (bank->target->state != TARGET_HALTED) {
 388                 LOG_ERROR("Target not halted");
 389                 return ERROR_TARGET_NOT_HALTED;
 390         }
 391
 392         *chip = bank->driver_priv;
 393
 394         int probed = nrf51_bank_is_probed(bank);
 395         if (probed < 0)
 396                 return probed;
 397         else if (!probed)
 398                 return nrf51_probe(bank);
 399         else
 400                 return ERROR_OK;
 401 }
 402
 403 static int nrf51_wait_for_nvmc(struct nrf51_info *chip)
 404 {
 405         uint32_t ready;
 406         int res;
 407         int timeout = 100;
 408
 409         do {
 410                 res = target_read_u32(chip->target, NRF51_NVMC_READY, &ready);
 411                 if (res != ERROR_OK) {
 412                         LOG_ERROR("Couldn't read NVMC_READY register");
 413                         return res;
 414                 }
 415
 416                 if (ready == 0x00000001)
 417                         return ERROR_OK;
 418
 419                 alive_sleep(1);
 420         } while (timeout--);
 421
 422         LOG_DEBUG("Timed out waiting for NVMC_READY");
 423         return ERROR_FLASH_BUSY;
 424 }
 425
 426 static int nrf51_nvmc_erase_enable(struct nrf51_info *chip)
 427 {
 428         int res;
 429         res = target_write_u32(chip->target,
 430                                NRF51_NVMC_CONFIG,
 431                                NRF51_NVMC_CONFIG_EEN);
 432
 433         if (res != ERROR_OK) {
 434                 LOG_ERROR("Failed to enable erase operation");
 435                 return res;
 436         }
 437
 438         /*
 439           According to NVMC examples in Nordic SDK busy status must be
 440           checked after writing to NVMC_CONFIG
 441          */
 442         res = nrf51_wait_for_nvmc(chip);
 443         if (res != ERROR_OK)
 444                 LOG_ERROR("Erase enable did not complete");
 445
 446         return res;
 447 }
 448
 449 static int nrf51_nvmc_write_enable(struct nrf51_info *chip)
 450 {
 451         int res;
 452         res = target_write_u32(chip->target,
 453                                NRF51_NVMC_CONFIG,
 454                                NRF51_NVMC_CONFIG_WEN);
 455
 456         if (res != ERROR_OK) {
 457                 LOG_ERROR("Failed to enable write operation");
 458                 return res;
 459         }
 460
 461         /*
 462           According to NVMC examples in Nordic SDK busy status must be
 463           checked after writing to NVMC_CONFIG
 464          */
 465         res = nrf51_wait_for_nvmc(chip);
 466         if (res != ERROR_OK)
 467                 LOG_ERROR("Write enable did not complete");
 468
 469         return res;
 470 }
 471
 472 static int nrf51_nvmc_read_only(struct nrf51_info *chip)
 473 {
 474         int res;
 475         res = target_write_u32(chip->target,
 476                                NRF51_NVMC_CONFIG,
 477                                NRF51_NVMC_CONFIG_REN);
 478
 479         if (res != ERROR_OK) {
 480                 LOG_ERROR("Failed to enable read-only operation");
 481                 return res;
 482         }
 483         /*
 484           According to NVMC examples in Nordic SDK busy status must be
 485           checked after writing to NVMC_CONFIG
 486          */
 487         res = nrf51_wait_for_nvmc(chip);
 488         if (res != ERROR_OK)
 489                 LOG_ERROR("Read only enable did not complete");
 490
 491         return res;
 492 }
 493
 494 static int nrf51_nvmc_generic_erase(struct nrf51_info *chip,
 495                                uint32_t erase_register, uint32_t erase_value)
 496 {
 497         int res;
 498
 499         res = nrf51_nvmc_erase_enable(chip);
 500         if (res != ERROR_OK)
 501                 goto error;
 502
 503         res = target_write_u32(chip->target,
 504                                erase_register,
 505                                erase_value);
 506         if (res != ERROR_OK)
 507                 goto set_read_only;
 508
 509         res = nrf51_wait_for_nvmc(chip);
 510         if (res != ERROR_OK)
 511                 goto set_read_only;
 512
 513         return nrf51_nvmc_read_only(chip);
 514
 515 set_read_only:
 516         nrf51_nvmc_read_only(chip);
 517 error:
 518         LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
 519                   erase_register, erase_value);
 520         return ERROR_FAIL;
 521 }
 522
 523 static int nrf51_protect_check(struct flash_bank *bank)
 524 {
 525         int res;
 526         uint32_t clenr0;
 527
 528         /* UICR cannot be write protected so just return early */
 529         if (bank->base == NRF51_UICR_BASE)
 530                 return ERROR_OK;
 531
 532         struct nrf51_info *chip = bank->driver_priv;
 533
 534         assert(chip != NULL);
 535
 536         res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
 537                               &clenr0);
 538         if (res != ERROR_OK) {
 539                 LOG_ERROR("Couldn't read code region 0 size[FICR]");
 540                 return res;
 541         }
 542
 543         if (clenr0 == 0xFFFFFFFF) {
 544                 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 545                                       &clenr0);
 546                 if (res != ERROR_OK) {
 547                         LOG_ERROR("Couldn't read code region 0 size[UICR]");
 548                         return res;
 549                 }
 550         }
 551
 552         for (int i = 0; i < bank->num_sectors; i++)
 553                 bank->sectors[i].is_protected =
 554                         clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
 555
 556         return ERROR_OK;
 557 }
 558
 559 static int nrf51_protect(struct flash_bank *bank, int set, int first, int last)
 560 {
 561         int res;
 562         uint32_t clenr0, ppfc;
 563         struct nrf51_info *chip;
 564
 565         /* UICR cannot be write protected so just bail out early */
 566         if (bank->base == NRF51_UICR_BASE)
 567                 return ERROR_FAIL;
 568
 569         res = nrf51_get_probed_chip_if_halted(bank, &chip);
 570         if (res != ERROR_OK)
 571                 return res;
 572
 573         if (first != 0) {
 574                 LOG_ERROR("Code region 0 must start at the begining of the bank");
 575                 return ERROR_FAIL;
 576         }
 577
 578         res = target_read_u32(chip->target, NRF51_FICR_PPFC,
 579                               &ppfc);
 580         if (res != ERROR_OK) {
 581                 LOG_ERROR("Couldn't read PPFC register");
 582                 return res;
 583         }
 584
 585         if ((ppfc & 0xFF) == 0x00) {
 586                 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
 587                 return ERROR_FAIL;
 588         }
 589
 590         res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 591                               &clenr0);
 592         if (res != ERROR_OK) {
 593                 LOG_ERROR("Couldn't read code region 0 size[UICR]");
 594                 return res;
 595         }
 596
 597         if (clenr0 == 0xFFFFFFFF) {
 598                 res = target_write_u32(chip->target, NRF51_UICR_CLENR0,
 599                                        clenr0);
 600                 if (res != ERROR_OK) {
 601                         LOG_ERROR("Couldn't write code region 0 size[UICR]");
 602                         return res;
 603                 }
 604
 605         } else {
 606                 LOG_ERROR("You need to perform chip erase before changing the protection settings");
 607         }
 608
 609         nrf51_protect_check(bank);
 610
 611         return ERROR_OK;
 612 }
 613
 614 static int nrf51_probe(struct flash_bank *bank)
 615 {
 616         uint32_t hwid;
 617         int res;
 618         struct nrf51_info *chip = bank->driver_priv;
 619
 620         res = target_read_u32(chip->target, NRF51_FICR_CONFIGID, &hwid);
 621         if (res != ERROR_OK) {
 622                 LOG_ERROR("Couldn't read CONFIGID register");
 623                 return res;
 624         }
 625
 626         hwid &= 0xFFFF; /* HWID is stored in the lower two
 627                          * bytes of the CONFIGID register */
 628
 629         const struct nrf51_device_spec *spec = NULL;
 630         for (size_t i = 0; i < ARRAY_SIZE(nrf51_known_devices_table); i++)
 631                 if (hwid == nrf51_known_devices_table[i].hwid) {
 632                         spec = &nrf51_known_devices_table[i];
 633                         break;
 634                 }
 635
 636         if (!chip->bank[0].probed && !chip->bank[1].probed) {
 637                 if (spec)
 638                         LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
 639                                  spec->variant, spec->build_code, spec->flash_size_kb);
 640                 else
 641                         LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
 642         }
 643
 644
 645         if (bank->base == NRF51_FLASH_BASE) {
 646                 res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE,
 647                                       &chip->code_page_size);
 648                 if (res != ERROR_OK) {
 649                         LOG_ERROR("Couldn't read code page size");
 650                         return res;
 651                 }
 652
 653                 res = target_read_u32(chip->target, NRF51_FICR_CODESIZE,
 654                                       &chip->code_memory_size);
 655                 if (res != ERROR_OK) {
 656                         LOG_ERROR("Couldn't read code memory size");
 657                         return res;
 658                 }
 659
 660                 if (spec && chip->code_memory_size != spec->flash_size_kb) {
 661                         LOG_ERROR("Chip's reported Flash capacity does not match expected one");
 662                         return ERROR_FAIL;
 663                 }
 664
 665                 bank->size = chip->code_memory_size * 1024;
 666                 bank->num_sectors = bank->size / chip->code_page_size;
 667                 bank->sectors = calloc(bank->num_sectors,
 668                                        sizeof((bank->sectors)[0]));
 669                 if (!bank->sectors)
 670                         return ERROR_FLASH_BANK_NOT_PROBED;
 671
 672                 /* Fill out the sector information: all NRF51 sectors are the same size and
 673                  * there is always a fixed number of them. */
 674                 for (int i = 0; i < bank->num_sectors; i++) {
 675                         bank->sectors[i].size = chip->code_page_size;
 676                         bank->sectors[i].offset = i * chip->code_page_size;
 677
 678                         /* mark as unknown */
 679                         bank->sectors[i].is_erased = -1;
 680                         bank->sectors[i].is_protected = -1;
 681                 }
 682
 683                 nrf51_protect_check(bank);
 684
 685                 chip->bank[0].probed = true;
 686         } else {
 687                 bank->size = NRF51_UICR_SIZE;
 688                 bank->num_sectors = 1;
 689                 bank->sectors = calloc(bank->num_sectors,
 690                                        sizeof((bank->sectors)[0]));
 691                 if (!bank->sectors)
 692                         return ERROR_FLASH_BANK_NOT_PROBED;
 693
 694                 bank->sectors[0].size = bank->size;
 695                 bank->sectors[0].offset = 0;
 696
 697                 /* mark as unknown */
 698                 bank->sectors[0].is_erased = 0;
 699                 bank->sectors[0].is_protected = 0;
 700
 701                 chip->bank[1].probed = true;
 702         }
 703
 704         return ERROR_OK;
 705 }
 706
 707 static int nrf51_auto_probe(struct flash_bank *bank)
 708 {
 709         int probed = nrf51_bank_is_probed(bank);
 710
 711         if (probed < 0)
 712                 return probed;
 713         else if (probed)
 714                 return ERROR_OK;
 715         else
 716                 return nrf51_probe(bank);
 717 }
 718
 719 static struct flash_sector *nrf51_find_sector_by_address(struct flash_bank *bank, uint32_t address)
 720 {
 721         struct nrf51_info *chip = bank->driver_priv;
 722
 723         for (int i = 0; i < bank->num_sectors; i++)
 724                 if (bank->sectors[i].offset <= address &&
 725                     address < (bank->sectors[i].offset + chip->code_page_size))
 726                         return &bank->sectors[i];
 727         return NULL;
 728 }
 729
 730 static int nrf51_erase_all(struct nrf51_info *chip)
 731 {
 732         LOG_DEBUG("Erasing all non-volatile memory");
 733         return nrf51_nvmc_generic_erase(chip,
 734                                         NRF51_NVMC_ERASEALL,
 735                                         0x00000001);
 736 }
 737
 738 static int nrf51_erase_page(struct flash_bank *bank,
 739                                                         struct nrf51_info *chip,
 740                                                         struct flash_sector *sector)
 741 {
 742         int res;
 743
 744         LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
 745         if (sector->is_protected) {
 746                 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
 747                 return ERROR_FAIL;
 748         }
 749
 750         if (bank->base == NRF51_UICR_BASE) {
 751                 uint32_t ppfc;
 752                 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
 753                                       &ppfc);
 754                 if (res != ERROR_OK) {
 755                         LOG_ERROR("Couldn't read PPFC register");
 756                         return res;
 757                 }
 758
 759                 if ((ppfc & 0xFF) == 0xFF) {
 760                         /* We can't erase the UICR.  Double-check to
 761                            see if it's already erased before complaining. */
 762                         default_flash_blank_check(bank);
 763                         if (sector->is_erased == 1)
 764                                 return ERROR_OK;
 765
 766                         LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
 767                         return ERROR_FAIL;
 768                 }
 769
 770                 res = nrf51_nvmc_generic_erase(chip,
 771                                                NRF51_NVMC_ERASEUICR,
 772                                                0x00000001);
 773
 774
 775         } else {
 776                 res = nrf51_nvmc_generic_erase(chip,
 777                                                NRF51_NVMC_ERASEPAGE,
 778                                                sector->offset);
 779         }
 780
 781         if (res == ERROR_OK)
 782                 sector->is_erased = 1;
 783
 784         return res;
 785 }
 786
 787 static const uint8_t nrf51_flash_write_code[] = {
 788         /* See contrib/loaders/flash/cortex-m0.S */
 789 /* <wait_fifo>: */
 790         0x0d, 0x68,             /* ldr  r5,     [r1,    #0] */
 791         0x00, 0x2d,             /* cmp  r5,     #0 */
 792         0x0b, 0xd0,             /* beq.n        1e <exit> */
 793         0x4c, 0x68,             /* ldr  r4,     [r1,    #4] */
 794         0xac, 0x42,             /* cmp  r4,     r5 */
 795         0xf9, 0xd0,             /* beq.n        0 <wait_fifo> */
 796         0x20, 0xcc,             /* ldmia        r4!,    {r5} */
 797         0x20, 0xc3,             /* stmia        r3!,    {r5} */
 798         0x94, 0x42,             /* cmp  r4,     r2 */
 799         0x01, 0xd3,             /* bcc.n        18 <no_wrap> */
 800         0x0c, 0x46,             /* mov  r4,     r1 */
 801         0x08, 0x34,             /* adds r4,     #8 */
 802 /* <no_wrap>: */
 803         0x4c, 0x60,             /* str  r4, [r1,        #4] */
 804         0x04, 0x38,             /* subs r0, #4 */
 805         0xf0, 0xd1,             /* bne.n        0 <wait_fifo> */
 806 /* <exit>: */
 807         0x00, 0xbe              /* bkpt 0x0000 */
 808 };
 809
 810
 811 /* Start a low level flash write for the specified region */
 812 static int nrf51_ll_flash_write(struct nrf51_info *chip, uint32_t offset, const uint8_t *buffer, uint32_t bytes)
 813 {
 814         struct target *target = chip->target;
 815         uint32_t buffer_size = 8192;
 816         struct working_area *write_algorithm;
 817         struct working_area *source;
 818         uint32_t address = NRF51_FLASH_BASE + offset;
 819         struct reg_param reg_params[4];
 820         struct armv7m_algorithm armv7m_info;
 821         int retval = ERROR_OK;
 822
 823
 824         LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32" bytes=0x%"PRIx32, offset, bytes);
 825         assert(bytes % 4 == 0);
 826
 827         /* allocate working area with flash programming code */
 828         if (target_alloc_working_area(target, sizeof(nrf51_flash_write_code),
 829                         &write_algorithm) != ERROR_OK) {
 830                 LOG_WARNING("no working area available, falling back to slow memory writes");
 831
 832                 for (; bytes > 0; bytes -= 4) {
 833                         retval = target_write_memory(chip->target, offset, 4, 1, buffer);
 834                         if (retval != ERROR_OK)
 835                                 return retval;
 836
 837                         retval = nrf51_wait_for_nvmc(chip);
 838                         if (retval != ERROR_OK)
 839                                 return retval;
 840
 841                         offset += 4;
 842                         buffer += 4;
 843                 }
 844
 845                 return ERROR_OK;
 846         }
 847
 848         LOG_WARNING("using fast async flash loader. This is currently supported");
 849         LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
 850         LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg to disable it");
 851
 852         retval = target_write_buffer(target, write_algorithm->address,
 853                                 sizeof(nrf51_flash_write_code),
 854                                 nrf51_flash_write_code);
 855         if (retval != ERROR_OK)
 856                 return retval;
 857
 858         /* memory buffer */
 859         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
 860                 buffer_size /= 2;
 861                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 862                 if (buffer_size <= 256) {
 863                         /* free working area, write algorithm already allocated */
 864                         target_free_working_area(target, write_algorithm);
 865
 866                         LOG_WARNING("No large enough working area available, can't do block memory writes");
 867                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 868                 }
 869         }
 870
 871         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 872         armv7m_info.core_mode = ARM_MODE_THREAD;
 873
 874         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
 875         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* buffer start */
 876         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer end */
 877         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
 878
 879         buf_set_u32(reg_params[0].value, 0, 32, bytes);
 880         buf_set_u32(reg_params[1].value, 0, 32, source->address);
 881         buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
 882         buf_set_u32(reg_params[3].value, 0, 32, address);
 883
 884         retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
 885                         0, NULL,
 886                         4, reg_params,
 887                         source->address, source->size,
 888                         write_algorithm->address, 0,
 889                         &armv7m_info);
 890
 891         target_free_working_area(target, source);
 892         target_free_working_area(target, write_algorithm);
 893
 894         destroy_reg_param(&reg_params[0]);
 895         destroy_reg_param(&reg_params[1]);
 896         destroy_reg_param(&reg_params[2]);
 897         destroy_reg_param(&reg_params[3]);
 898
 899         return retval;
 900 }
 901
 902 /* Check and erase flash sectors in specified range then start a low level page write.
 903    start/end must be sector aligned.
 904 */
 905 static int nrf51_write_pages(struct flash_bank *bank, uint32_t start, uint32_t end, const uint8_t *buffer)
 906 {
 907         int res = ERROR_FAIL;
 908         struct nrf51_info *chip = bank->driver_priv;
 909         struct flash_sector *sector;
 910         uint32_t offset;
 911
 912         assert(start % chip->code_page_size == 0);
 913         assert(end % chip->code_page_size == 0);
 914
 915         /* Erase all sectors */
 916         for (offset = start; offset < end; offset += chip->code_page_size) {
 917                 sector = nrf51_find_sector_by_address(bank, offset);
 918                 if (!sector) {
 919                         LOG_ERROR("Invalid sector @ 0x%08"PRIx32, offset);
 920                         return ERROR_FLASH_SECTOR_INVALID;
 921                 }
 922
 923                 if (sector->is_protected) {
 924                         LOG_ERROR("Can't erase protected sector @ 0x%08"PRIx32, offset);
 925                         goto error;
 926                 }
 927
 928                 if (sector->is_erased != 1) {   /* 1 = erased, 0= not erased, -1 = unknown */
 929                         res = nrf51_erase_page(bank, chip, sector);
 930                         if (res != ERROR_OK) {
 931                                 LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32, sector->offset);
 932                                 goto error;
 933                         }
 934                 }
 935                 sector->is_erased = 0;
 936         }
 937
 938         res = nrf51_nvmc_write_enable(chip);
 939         if (res != ERROR_OK)
 940                 goto error;
 941
 942         res = nrf51_ll_flash_write(chip, start, buffer, (end - start));
 943         if (res != ERROR_OK)
 944                 goto set_read_only;
 945
 946         return nrf51_nvmc_read_only(chip);
 947
 948 set_read_only:
 949         nrf51_nvmc_read_only(chip);
 950 error:
 951         LOG_ERROR("Failed to write to nrf51 flash");
 952         return res;
 953 }
 954
 955 static int nrf51_erase(struct flash_bank *bank, int first, int last)
 956 {
 957         int res;
 958         struct nrf51_info *chip;
 959
 960         res = nrf51_get_probed_chip_if_halted(bank, &chip);
 961         if (res != ERROR_OK)
 962                 return res;
 963
 964         /* For each sector to be erased */
 965         for (int s = first; s <= last && res == ERROR_OK; s++)
 966                 res = nrf51_erase_page(bank, chip, &bank->sectors[s]);
 967
 968         return res;
 969 }
 970
 971 static int nrf51_code_flash_write(struct flash_bank *bank,
 972                                   struct nrf51_info *chip,
 973                                   const uint8_t *buffer, uint32_t offset, uint32_t count)
 974 {
 975
 976         int res;
 977         /* Need to perform reads to fill any gaps we need to preserve in the first page,
 978            before the start of buffer, or in the last page, after the end of buffer */
 979         uint32_t first_page = offset/chip->code_page_size;
 980         uint32_t last_page = DIV_ROUND_UP(offset+count, chip->code_page_size);
 981
 982         uint32_t first_page_offset = first_page * chip->code_page_size;
 983         uint32_t last_page_offset = last_page * chip->code_page_size;
 984
 985         LOG_DEBUG("Padding write from 0x%08"PRIx32"-0x%08"PRIx32" as 0x%08"PRIx32"-0x%08"PRIx32,
 986                 offset, offset+count, first_page_offset, last_page_offset);
 987
 988         uint32_t page_cnt = last_page - first_page;
 989         uint8_t buffer_to_flash[page_cnt*chip->code_page_size];
 990
 991         /* Fill in any space between start of first page and start of buffer */
 992         uint32_t pre = offset - first_page_offset;
 993         if (pre > 0) {
 994                 res = target_read_memory(bank->target,
 995                                         first_page_offset,
 996                                         1,
 997                                         pre,
 998                                         buffer_to_flash);
 999                 if (res != ERROR_OK)
1000                         return res;
1001         }
1002
1003         /* Fill in main contents of buffer */
1004         memcpy(buffer_to_flash+pre, buffer, count);
1005
1006         /* Fill in any space between end of buffer and end of last page */
1007         uint32_t post = last_page_offset - (offset+count);
1008         if (post > 0) {
1009                 /* Retrieve the full row contents from Flash */
1010                 res = target_read_memory(bank->target,
1011                                         offset + count,
1012                                         1,
1013                                         post,
1014                                         buffer_to_flash+pre+count);
1015                 if (res != ERROR_OK)
1016                         return res;
1017         }
1018
1019         return nrf51_write_pages(bank, first_page_offset, last_page_offset, buffer_to_flash);
1020 }
1021
1022 static int nrf51_uicr_flash_write(struct flash_bank *bank,
1023                                   struct nrf51_info *chip,
1024                                   const uint8_t *buffer, uint32_t offset, uint32_t count)
1025 {
1026         int res;
1027         uint8_t uicr[NRF51_UICR_SIZE];
1028         struct flash_sector *sector = &bank->sectors[0];
1029
1030         if ((offset + count) > NRF51_UICR_SIZE)
1031                 return ERROR_FAIL;
1032
1033         res = target_read_memory(bank->target,
1034                                  NRF51_UICR_BASE,
1035                                  1,
1036                                  NRF51_UICR_SIZE,
1037                                  uicr);
1038
1039         if (res != ERROR_OK)
1040                 return res;
1041
1042         if (sector->is_erased != 1) {
1043                 res = nrf51_erase_page(bank, chip, sector);
1044                 if (res != ERROR_OK)
1045                         return res;
1046         }
1047
1048         res = nrf51_nvmc_write_enable(chip);
1049         if (res != ERROR_OK)
1050                 return res;
1051
1052         memcpy(&uicr[offset], buffer, count);
1053
1054         res = nrf51_ll_flash_write(chip, NRF51_UICR_BASE, uicr, NRF51_UICR_SIZE);
1055         if (res != ERROR_OK) {
1056                 nrf51_nvmc_read_only(chip);
1057                 return res;
1058         }
1059
1060         return nrf51_nvmc_read_only(chip);
1061 }
1062
1063
1064 static int nrf51_write(struct flash_bank *bank, const uint8_t *buffer,
1065                        uint32_t offset, uint32_t count)
1066 {
1067         int res;
1068         struct nrf51_info *chip;
1069
1070         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1071         if (res != ERROR_OK)
1072                 return res;
1073
1074         return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, count);
1075 }
1076
1077
1078 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command)
1079 {
1080         static struct nrf51_info *chip;
1081
1082         switch (bank->base) {
1083         case NRF51_FLASH_BASE:
1084                 bank->bank_number = 0;
1085                 break;
1086         case NRF51_UICR_BASE:
1087                 bank->bank_number = 1;
1088                 break;
1089         default:
1090                 LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
1091                 return ERROR_FAIL;
1092         }
1093
1094         if (!chip) {
1095                 /* Create a new chip */
1096                 chip = calloc(1, sizeof(*chip));
1097                 if (!chip)
1098                         return ERROR_FAIL;
1099
1100                 chip->target = bank->target;
1101         }
1102
1103         switch (bank->base) {
1104         case NRF51_FLASH_BASE:
1105                 chip->bank[bank->bank_number].write = nrf51_code_flash_write;
1106                 break;
1107         case NRF51_UICR_BASE:
1108                 chip->bank[bank->bank_number].write = nrf51_uicr_flash_write;
1109                 break;
1110         }
1111
1112         chip->bank[bank->bank_number].probed = false;
1113         bank->driver_priv = chip;
1114
1115         return ERROR_OK;
1116 }
1117
1118 COMMAND_HANDLER(nrf51_handle_mass_erase_command)
1119 {
1120         int res;
1121         struct flash_bank *bank = NULL;
1122         struct target *target = get_current_target(CMD_CTX);
1123
1124         res = get_flash_bank_by_addr(target, NRF51_FLASH_BASE, true, &bank);
1125         if (res != ERROR_OK)
1126                 return res;
1127
1128         assert(bank != NULL);
1129
1130         struct nrf51_info *chip;
1131
1132         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1133         if (res != ERROR_OK)
1134                 return res;
1135
1136         uint32_t ppfc;
1137
1138         res = target_read_u32(target, NRF51_FICR_PPFC,
1139                               &ppfc);
1140         if (res != ERROR_OK) {
1141                 LOG_ERROR("Couldn't read PPFC register");
1142                 return res;
1143         }
1144
1145         if ((ppfc & 0xFF) == 0x00) {
1146                 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1147                           "mass erase command won't work.");
1148                 return ERROR_FAIL;
1149         }
1150
1151         res = nrf51_erase_all(chip);
1152         if (res != ERROR_OK) {
1153                 LOG_ERROR("Failed to erase the chip");
1154                 nrf51_protect_check(bank);
1155                 return res;
1156         }
1157
1158         for (int i = 0; i < bank->num_sectors; i++)
1159                 bank->sectors[i].is_erased = 1;
1160
1161         res = nrf51_protect_check(bank);
1162         if (res != ERROR_OK) {
1163                 LOG_ERROR("Failed to check chip's write protection");
1164                 return res;
1165         }
1166
1167         res = get_flash_bank_by_addr(target, NRF51_UICR_BASE, true, &bank);
1168         if (res != ERROR_OK)
1169                 return res;
1170
1171         bank->sectors[0].is_erased = 1;
1172
1173         return ERROR_OK;
1174 }
1175
1176 static int nrf51_info(struct flash_bank *bank, char *buf, int buf_size)
1177 {
1178         int res;
1179
1180         struct nrf51_info *chip;
1181
1182         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1183         if (res != ERROR_OK)
1184                 return res;
1185
1186         static struct {
1187                 const uint32_t address;
1188                 uint32_t value;
1189         } ficr[] = {
1190                 { .address = NRF51_FICR_CODEPAGESIZE    },
1191                 { .address = NRF51_FICR_CODESIZE        },
1192                 { .address = NRF51_FICR_CLENR0          },
1193                 { .address = NRF51_FICR_PPFC            },
1194                 { .address = NRF51_FICR_NUMRAMBLOCK     },
1195                 { .address = NRF51_FICR_SIZERAMBLOCK0   },
1196                 { .address = NRF51_FICR_SIZERAMBLOCK1   },
1197                 { .address = NRF51_FICR_SIZERAMBLOCK2   },
1198                 { .address = NRF51_FICR_SIZERAMBLOCK3   },
1199                 { .address = NRF51_FICR_CONFIGID        },
1200                 { .address = NRF51_FICR_DEVICEID0       },
1201                 { .address = NRF51_FICR_DEVICEID1       },
1202                 { .address = NRF51_FICR_ER0             },
1203                 { .address = NRF51_FICR_ER1             },
1204                 { .address = NRF51_FICR_ER2             },
1205                 { .address = NRF51_FICR_ER3             },
1206                 { .address = NRF51_FICR_IR0             },
1207                 { .address = NRF51_FICR_IR1             },
1208                 { .address = NRF51_FICR_IR2             },
1209                 { .address = NRF51_FICR_IR3             },
1210                 { .address = NRF51_FICR_DEVICEADDRTYPE  },
1211                 { .address = NRF51_FICR_DEVICEADDR0     },
1212                 { .address = NRF51_FICR_DEVICEADDR1     },
1213                 { .address = NRF51_FICR_OVERRIDEN       },
1214                 { .address = NRF51_FICR_NRF_1MBIT0      },
1215                 { .address = NRF51_FICR_NRF_1MBIT1      },
1216                 { .address = NRF51_FICR_NRF_1MBIT2      },
1217                 { .address = NRF51_FICR_NRF_1MBIT3      },
1218                 { .address = NRF51_FICR_NRF_1MBIT4      },
1219                 { .address = NRF51_FICR_BLE_1MBIT0      },
1220                 { .address = NRF51_FICR_BLE_1MBIT1      },
1221                 { .address = NRF51_FICR_BLE_1MBIT2      },
1222                 { .address = NRF51_FICR_BLE_1MBIT3      },
1223                 { .address = NRF51_FICR_BLE_1MBIT4      },
1224         }, uicr[] = {
1225                 { .address = NRF51_UICR_CLENR0,         },
1226                 { .address = NRF51_UICR_RBPCONF         },
1227                 { .address = NRF51_UICR_XTALFREQ        },
1228                 { .address = NRF51_UICR_FWID            },
1229         };
1230
1231         for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1232                 res = target_read_u32(chip->target, ficr[i].address,
1233                                       &ficr[i].value);
1234                 if (res != ERROR_OK) {
1235                         LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1236                         return res;
1237                 }
1238         }
1239
1240         for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1241                 res = target_read_u32(chip->target, uicr[i].address,
1242                                       &uicr[i].value);
1243                 if (res != ERROR_OK) {
1244                         LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1245                         return res;
1246                 }
1247         }
1248
1249         snprintf(buf, buf_size,
1250                  "\n[factory information control block]\n\n"
1251                  "code page size: %"PRIu32"B\n"
1252                  "code memory size: %"PRIu32"kB\n"
1253                  "code region 0 size: %"PRIu32"kB\n"
1254                  "pre-programmed code: %s\n"
1255                  "number of ram blocks: %"PRIu32"\n"
1256                  "ram block 0 size: %"PRIu32"B\n"
1257                  "ram block 1 size: %"PRIu32"B\n"
1258                  "ram block 2 size: %"PRIu32"B\n"
1259                  "ram block 3 size: %"PRIu32 "B\n"
1260                  "config id: %" PRIx32 "\n"
1261                  "device id: 0x%"PRIx32"%08"PRIx32"\n"
1262                  "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1263                  "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1264                  "device address type: 0x%"PRIx32"\n"
1265                  "device address: 0x%"PRIx32"%08"PRIx32"\n"
1266                  "override enable: %"PRIx32"\n"
1267                  "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1268                  "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1269                  "\n[user information control block]\n\n"
1270                  "code region 0 size: %"PRIu32"kB\n"
1271                  "read back protection configuration: %"PRIx32"\n"
1272                  "reset value for XTALFREQ: %"PRIx32"\n"
1273                  "firmware id: 0x%04"PRIx32,
1274                  ficr[0].value,
1275                  ficr[1].value,
1276                  (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1277                  ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1278                  ficr[4].value,
1279                  ficr[5].value,
1280                  (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1281                  (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1282                  (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1283                  ficr[9].value,
1284                  ficr[10].value, ficr[11].value,
1285                  ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1286                  ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1287                  ficr[20].value,
1288                  ficr[21].value, ficr[22].value,
1289                  ficr[23].value,
1290                  ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1291                  ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1292                  (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1293                  uicr[1].value & 0xFFFF,
1294                  uicr[2].value & 0xFF,
1295                  uicr[3].value & 0xFFFF);
1296
1297         return ERROR_OK;
1298 }
1299
1300 static const struct command_registration nrf51_exec_command_handlers[] = {
1301         {
1302                 .name           = "mass_erase",
1303                 .handler        = nrf51_handle_mass_erase_command,
1304                 .mode           = COMMAND_EXEC,
1305                 .help           = "Erase all flash contents of the chip.",
1306         },
1307         COMMAND_REGISTRATION_DONE
1308 };
1309
1310 static const struct command_registration nrf51_command_handlers[] = {
1311         {
1312                 .name   = "nrf51",
1313                 .mode   = COMMAND_ANY,
1314                 .help   = "nrf51 flash command group",
1315                 .usage  = "",
1316                 .chain  = nrf51_exec_command_handlers,
1317         },
1318         COMMAND_REGISTRATION_DONE
1319 };
1320
1321 struct flash_driver nrf51_flash = {
1322         .name                   = "nrf51",
1323         .commands               = nrf51_command_handlers,
1324         .flash_bank_command     = nrf51_flash_bank_command,
1325         .info                   = nrf51_info,
1326         .erase                  = nrf51_erase,
1327         .protect                = nrf51_protect,
1328         .write                  = nrf51_write,
1329         .read                   = default_flash_read,
1330         .probe                  = nrf51_probe,
1331         .auto_probe             = nrf51_auto_probe,
1332         .erase_check            = default_flash_blank_check,
1333         .protect_check          = nrf51_protect_check,
1334 };