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   1 /***************************************************************************
   2  *   Copyright (C) 2013 Synapse Product Development                        *
   3  *   Andrey Smirnov <andrew.smironv@gmail.com>                             *
   4  *   Angus Gratton <gus@projectgus.com>                                    *
   5  *   Erdem U. Altunyurt <spamjunkeater@gmail.com>                          *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  21  ***************************************************************************/
  22
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "imp.h"
  28 #include <target/algorithm.h>
  29 #include <target/armv7m.h>
  30 #include <helper/types.h>
  31
  32 enum {
  33         NRF51_FLASH_BASE = 0x00000000,
  34 };
  35
  36 enum nrf51_ficr_registers {
  37         NRF51_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
  38
  39 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
  40
  41         NRF51_FICR_CODEPAGESIZE         = NRF51_FICR_REG(0x010),
  42         NRF51_FICR_CODESIZE             = NRF51_FICR_REG(0x014),
  43         NRF51_FICR_CLENR0               = NRF51_FICR_REG(0x028),
  44         NRF51_FICR_PPFC                 = NRF51_FICR_REG(0x02C),
  45         NRF51_FICR_NUMRAMBLOCK          = NRF51_FICR_REG(0x034),
  46         NRF51_FICR_SIZERAMBLOCK0        = NRF51_FICR_REG(0x038),
  47         NRF51_FICR_SIZERAMBLOCK1        = NRF51_FICR_REG(0x03C),
  48         NRF51_FICR_SIZERAMBLOCK2        = NRF51_FICR_REG(0x040),
  49         NRF51_FICR_SIZERAMBLOCK3        = NRF51_FICR_REG(0x044),
  50         NRF51_FICR_CONFIGID             = NRF51_FICR_REG(0x05C),
  51         NRF51_FICR_DEVICEID0            = NRF51_FICR_REG(0x060),
  52         NRF51_FICR_DEVICEID1            = NRF51_FICR_REG(0x064),
  53         NRF51_FICR_ER0                  = NRF51_FICR_REG(0x080),
  54         NRF51_FICR_ER1                  = NRF51_FICR_REG(0x084),
  55         NRF51_FICR_ER2                  = NRF51_FICR_REG(0x088),
  56         NRF51_FICR_ER3                  = NRF51_FICR_REG(0x08C),
  57         NRF51_FICR_IR0                  = NRF51_FICR_REG(0x090),
  58         NRF51_FICR_IR1                  = NRF51_FICR_REG(0x094),
  59         NRF51_FICR_IR2                  = NRF51_FICR_REG(0x098),
  60         NRF51_FICR_IR3                  = NRF51_FICR_REG(0x09C),
  61         NRF51_FICR_DEVICEADDRTYPE       = NRF51_FICR_REG(0x0A0),
  62         NRF51_FICR_DEVICEADDR0          = NRF51_FICR_REG(0x0A4),
  63         NRF51_FICR_DEVICEADDR1          = NRF51_FICR_REG(0x0A8),
  64         NRF51_FICR_OVERRIDEN            = NRF51_FICR_REG(0x0AC),
  65         NRF51_FICR_NRF_1MBIT0           = NRF51_FICR_REG(0x0B0),
  66         NRF51_FICR_NRF_1MBIT1           = NRF51_FICR_REG(0x0B4),
  67         NRF51_FICR_NRF_1MBIT2           = NRF51_FICR_REG(0x0B8),
  68         NRF51_FICR_NRF_1MBIT3           = NRF51_FICR_REG(0x0BC),
  69         NRF51_FICR_NRF_1MBIT4           = NRF51_FICR_REG(0x0C0),
  70         NRF51_FICR_BLE_1MBIT0           = NRF51_FICR_REG(0x0EC),
  71         NRF51_FICR_BLE_1MBIT1           = NRF51_FICR_REG(0x0F0),
  72         NRF51_FICR_BLE_1MBIT2           = NRF51_FICR_REG(0x0F4),
  73         NRF51_FICR_BLE_1MBIT3           = NRF51_FICR_REG(0x0F8),
  74         NRF51_FICR_BLE_1MBIT4           = NRF51_FICR_REG(0x0FC),
  75 };
  76
  77 enum nrf51_uicr_registers {
  78         NRF51_UICR_BASE = 0x10001000, /* User Information
  79                                        * Configuration Regsters */
  80
  81         NRF51_UICR_SIZE = 0x100,
  82
  83 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
  84
  85         NRF51_UICR_CLENR0       = NRF51_UICR_REG(0x000),
  86         NRF51_UICR_RBPCONF      = NRF51_UICR_REG(0x004),
  87         NRF51_UICR_XTALFREQ     = NRF51_UICR_REG(0x008),
  88         NRF51_UICR_FWID         = NRF51_UICR_REG(0x010),
  89 };
  90
  91 enum nrf51_nvmc_registers {
  92         NRF51_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
  93                                        * Controller Regsters */
  94
  95 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
  96
  97         NRF51_NVMC_READY        = NRF51_NVMC_REG(0x400),
  98         NRF51_NVMC_CONFIG       = NRF51_NVMC_REG(0x504),
  99         NRF51_NVMC_ERASEPAGE    = NRF51_NVMC_REG(0x508),
 100         NRF51_NVMC_ERASEALL     = NRF51_NVMC_REG(0x50C),
 101         NRF51_NVMC_ERASEUICR    = NRF51_NVMC_REG(0x514),
 102 };
 103
 104 enum nrf51_nvmc_config_bits {
 105         NRF51_NVMC_CONFIG_REN = 0x00,
 106         NRF51_NVMC_CONFIG_WEN = 0x01,
 107         NRF51_NVMC_CONFIG_EEN = 0x02,
 108
 109 };
 110
 111 struct nrf51_info {
 112         uint32_t code_page_size;
 113         uint32_t code_memory_size;
 114
 115         struct {
 116                 bool probed;
 117                 int (*write) (struct flash_bank *bank,
 118                               struct nrf51_info *chip,
 119                               const uint8_t *buffer, uint32_t offset, uint32_t count);
 120         } bank[2];
 121         struct target *target;
 122 };
 123
 124 struct nrf51_device_spec {
 125         uint16_t hwid;
 126         const char *variant;
 127         const char *build_code;
 128         unsigned int flash_size_kb;
 129 };
 130
 131 /* The known devices table below is derived from the "nRF51 Series
 132  * Compatibility Matrix" document, which can be found by searching for
 133  * ATTN-51 on the Nordic Semi website:
 134  *
 135  * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
 136  *
 137  * Up to date with Matrix v2.0, plus some additional HWIDs.
 138  *
 139  * The additional HWIDs apply where the build code in the matrix is
 140  * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
 141  * for x==0, x!=0 means different (unspecified) HWIDs.
 142  */
 143 static const struct nrf51_device_spec nrf51_known_devices_table[] = {
 144         /* nRF51822 Devices (IC rev 1). */
 145         {
 146                 .hwid           = 0x001D,
 147                 .variant        = "QFAA",
 148                 .build_code     = "CA/C0",
 149                 .flash_size_kb  = 256,
 150         },
 151         {
 152                 .hwid           = 0x0026,
 153                 .variant        = "QFAB",
 154                 .build_code     = "AA",
 155                 .flash_size_kb  = 128,
 156         },
 157         {
 158                 .hwid           = 0x0027,
 159                 .variant        = "QFAB",
 160                 .build_code     = "A0",
 161                 .flash_size_kb  = 128,
 162         },
 163         {
 164                 .hwid           = 0x0020,
 165                 .variant        = "CEAA",
 166                 .build_code     = "BA",
 167                 .flash_size_kb  = 256,
 168         },
 169         {
 170                 .hwid           = 0x002F,
 171                 .variant        = "CEAA",
 172                 .build_code     = "B0",
 173                 .flash_size_kb  = 256,
 174         },
 175
 176         /* nRF51822 Devices (IC rev 2). */
 177         {
 178                 .hwid           = 0x002A,
 179                 .variant        = "QFAA",
 180                 .build_code     = "FA0",
 181                 .flash_size_kb  = 256,
 182         },
 183         {
 184                 .hwid           = 0x0044,
 185                 .variant        = "QFAA",
 186                 .build_code     = "GC0",
 187                 .flash_size_kb  = 256,
 188         },
 189         {
 190                 .hwid           = 0x003C,
 191                 .variant        = "QFAA",
 192                 .build_code     = "G0",
 193                 .flash_size_kb  = 256,
 194         },
 195         {
 196                 .hwid           = 0x0057,
 197                 .variant        = "QFAA",
 198                 .build_code     = "G2",
 199                 .flash_size_kb  = 256,
 200         },
 201         {
 202                 .hwid           = 0x0058,
 203                 .variant        = "QFAA",
 204                 .build_code     = "G3",
 205                 .flash_size_kb  = 256,
 206         },
 207         {
 208                 .hwid           = 0x004C,
 209                 .variant        = "QFAB",
 210                 .build_code     = "B0",
 211                 .flash_size_kb  = 128,
 212         },
 213         {
 214                 .hwid           = 0x0040,
 215                 .variant        = "CEAA",
 216                 .build_code     = "CA0",
 217                 .flash_size_kb  = 256,
 218         },
 219         {
 220                 .hwid           = 0x0047,
 221                 .variant        = "CEAA",
 222                 .build_code     = "DA0",
 223                 .flash_size_kb  = 256,
 224         },
 225         {
 226                 .hwid           = 0x004D,
 227                 .variant        = "CEAA",
 228                 .build_code     = "D00",
 229                 .flash_size_kb  = 256,
 230         },
 231
 232         /* nRF51822 Devices (IC rev 3). */
 233         {
 234                 .hwid           = 0x0072,
 235                 .variant        = "QFAA",
 236                 .build_code     = "H0",
 237                 .flash_size_kb  = 256,
 238         },
 239         {
 240                 .hwid           = 0x007B,
 241                 .variant        = "QFAB",
 242                 .build_code     = "C0",
 243                 .flash_size_kb  = 128,
 244         },
 245         {
 246                 .hwid           = 0x0083,
 247                 .variant        = "QFAC",
 248                 .build_code     = "A0",
 249                 .flash_size_kb  = 256,
 250         },
 251         {
 252                 .hwid           = 0x0084,
 253                 .variant        = "QFAC",
 254                 .build_code     = "A1",
 255                 .flash_size_kb  = 256,
 256         },
 257         {
 258                 .hwid           = 0x007D,
 259                 .variant        = "CDAB",
 260                 .build_code     = "A0",
 261                 .flash_size_kb  = 128,
 262         },
 263         {
 264                 .hwid           = 0x0079,
 265                 .variant        = "CEAA",
 266                 .build_code     = "E0",
 267                 .flash_size_kb  = 256,
 268         },
 269         {
 270                 .hwid           = 0x0087,
 271                 .variant        = "CFAC",
 272                 .build_code     = "A0",
 273                 .flash_size_kb  = 256,
 274         },
 275
 276         /* nRF51422 Devices (IC rev 1). */
 277         {
 278                 .hwid           = 0x001E,
 279                 .variant        = "QFAA",
 280                 .build_code     = "CA",
 281                 .flash_size_kb  = 256,
 282         },
 283         {
 284                 .hwid           = 0x0024,
 285                 .variant        = "QFAA",
 286                 .build_code     = "C0",
 287                 .flash_size_kb  = 256,
 288         },
 289         {
 290                 .hwid           = 0x0031,
 291                 .variant        = "CEAA",
 292                 .build_code     = "A0A",
 293                 .flash_size_kb  = 256,
 294         },
 295
 296         /* nRF51422 Devices (IC rev 2). */
 297         {
 298                 .hwid           = 0x002D,
 299                 .variant        = "QFAA",
 300                 .build_code     = "DAA",
 301                 .flash_size_kb  = 256,
 302         },
 303         {
 304                 .hwid           = 0x002E,
 305                 .variant        = "QFAA",
 306                 .build_code     = "E0",
 307                 .flash_size_kb  = 256,
 308         },
 309         {
 310                 .hwid           = 0x0061,
 311                 .variant        = "QFAB",
 312                 .build_code     = "A00",
 313                 .flash_size_kb  = 128,
 314         },
 315         {
 316                 .hwid           = 0x0050,
 317                 .variant        = "CEAA",
 318                 .build_code     = "B0",
 319                 .flash_size_kb  = 256,
 320         },
 321
 322         /* nRF51422 Devices (IC rev 3). */
 323         {
 324                 .hwid           = 0x0073,
 325                 .variant        = "QFAA",
 326                 .build_code     = "F0",
 327                 .flash_size_kb  = 256,
 328         },
 329         {
 330                 .hwid           = 0x007C,
 331                 .variant        = "QFAB",
 332                 .build_code     = "B0",
 333                 .flash_size_kb  = 128,
 334         },
 335         {
 336                 .hwid           = 0x0085,
 337                 .variant        = "QFAC",
 338                 .build_code     = "A0",
 339                 .flash_size_kb  = 256,
 340         },
 341         {
 342                 .hwid           = 0x0086,
 343                 .variant        = "QFAC",
 344                 .build_code     = "A1",
 345                 .flash_size_kb  = 256,
 346         },
 347         {
 348                 .hwid           = 0x007E,
 349                 .variant        = "CDAB",
 350                 .build_code     = "A0",
 351                 .flash_size_kb  = 128,
 352         },
 353         {
 354                 .hwid           = 0x007A,
 355                 .variant        = "CEAA",
 356                 .build_code     = "C0",
 357                 .flash_size_kb  = 256,
 358         },
 359         {
 360                 .hwid           = 0x0088,
 361                 .variant        = "CFAC",
 362                 .build_code     = "A0",
 363                 .flash_size_kb  = 256,
 364         },
 365
 366         /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
 367            with built-in jlink seem to use engineering samples not listed
 368            in the nRF51 Series Compatibility Matrix V1.0. */
 369         {
 370                 .hwid           = 0x0071,
 371                 .variant        = "QFAC",
 372                 .build_code     = "AB",
 373                 .flash_size_kb  = 256,
 374         },
 375 };
 376
 377 static int nrf51_bank_is_probed(struct flash_bank *bank)
 378 {
 379         struct nrf51_info *chip = bank->driver_priv;
 380
 381         assert(chip != NULL);
 382
 383         return chip->bank[bank->bank_number].probed;
 384 }
 385 static int nrf51_probe(struct flash_bank *bank);
 386
 387 static int nrf51_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf51_info **chip)
 388 {
 389         if (bank->target->state != TARGET_HALTED) {
 390                 LOG_ERROR("Target not halted");
 391                 return ERROR_TARGET_NOT_HALTED;
 392         }
 393
 394         *chip = bank->driver_priv;
 395
 396         int probed = nrf51_bank_is_probed(bank);
 397         if (probed < 0)
 398                 return probed;
 399         else if (!probed)
 400                 return nrf51_probe(bank);
 401         else
 402                 return ERROR_OK;
 403 }
 404
 405 static int nrf51_wait_for_nvmc(struct nrf51_info *chip)
 406 {
 407         uint32_t ready;
 408         int res;
 409         int timeout = 100;
 410
 411         do {
 412                 res = target_read_u32(chip->target, NRF51_NVMC_READY, &ready);
 413                 if (res != ERROR_OK) {
 414                         LOG_ERROR("Couldn't read NVMC_READY register");
 415                         return res;
 416                 }
 417
 418                 if (ready == 0x00000001)
 419                         return ERROR_OK;
 420
 421                 alive_sleep(1);
 422         } while (timeout--);
 423
 424         LOG_DEBUG("Timed out waiting for NVMC_READY");
 425         return ERROR_FLASH_BUSY;
 426 }
 427
 428 static int nrf51_nvmc_erase_enable(struct nrf51_info *chip)
 429 {
 430         int res;
 431         res = target_write_u32(chip->target,
 432                                NRF51_NVMC_CONFIG,
 433                                NRF51_NVMC_CONFIG_EEN);
 434
 435         if (res != ERROR_OK) {
 436                 LOG_ERROR("Failed to enable erase operation");
 437                 return res;
 438         }
 439
 440         /*
 441           According to NVMC examples in Nordic SDK busy status must be
 442           checked after writing to NVMC_CONFIG
 443          */
 444         res = nrf51_wait_for_nvmc(chip);
 445         if (res != ERROR_OK)
 446                 LOG_ERROR("Erase enable did not complete");
 447
 448         return res;
 449 }
 450
 451 static int nrf51_nvmc_write_enable(struct nrf51_info *chip)
 452 {
 453         int res;
 454         res = target_write_u32(chip->target,
 455                                NRF51_NVMC_CONFIG,
 456                                NRF51_NVMC_CONFIG_WEN);
 457
 458         if (res != ERROR_OK) {
 459                 LOG_ERROR("Failed to enable write operation");
 460                 return res;
 461         }
 462
 463         /*
 464           According to NVMC examples in Nordic SDK busy status must be
 465           checked after writing to NVMC_CONFIG
 466          */
 467         res = nrf51_wait_for_nvmc(chip);
 468         if (res != ERROR_OK)
 469                 LOG_ERROR("Write enable did not complete");
 470
 471         return res;
 472 }
 473
 474 static int nrf51_nvmc_read_only(struct nrf51_info *chip)
 475 {
 476         int res;
 477         res = target_write_u32(chip->target,
 478                                NRF51_NVMC_CONFIG,
 479                                NRF51_NVMC_CONFIG_REN);
 480
 481         if (res != ERROR_OK) {
 482                 LOG_ERROR("Failed to enable read-only operation");
 483                 return res;
 484         }
 485         /*
 486           According to NVMC examples in Nordic SDK busy status must be
 487           checked after writing to NVMC_CONFIG
 488          */
 489         res = nrf51_wait_for_nvmc(chip);
 490         if (res != ERROR_OK)
 491                 LOG_ERROR("Read only enable did not complete");
 492
 493         return res;
 494 }
 495
 496 static int nrf51_nvmc_generic_erase(struct nrf51_info *chip,
 497                                uint32_t erase_register, uint32_t erase_value)
 498 {
 499         int res;
 500
 501         res = nrf51_nvmc_erase_enable(chip);
 502         if (res != ERROR_OK)
 503                 goto error;
 504
 505         res = target_write_u32(chip->target,
 506                                erase_register,
 507                                erase_value);
 508         if (res != ERROR_OK)
 509                 goto set_read_only;
 510
 511         res = nrf51_wait_for_nvmc(chip);
 512         if (res != ERROR_OK)
 513                 goto set_read_only;
 514
 515         return nrf51_nvmc_read_only(chip);
 516
 517 set_read_only:
 518         nrf51_nvmc_read_only(chip);
 519 error:
 520         LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
 521                   erase_register, erase_value);
 522         return ERROR_FAIL;
 523 }
 524
 525 static int nrf51_protect_check(struct flash_bank *bank)
 526 {
 527         int res;
 528         uint32_t clenr0;
 529
 530         /* UICR cannot be write protected so just return early */
 531         if (bank->base == NRF51_UICR_BASE)
 532                 return ERROR_OK;
 533
 534         struct nrf51_info *chip = bank->driver_priv;
 535
 536         assert(chip != NULL);
 537
 538         res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
 539                               &clenr0);
 540         if (res != ERROR_OK) {
 541                 LOG_ERROR("Couldn't read code region 0 size[FICR]");
 542                 return res;
 543         }
 544
 545         if (clenr0 == 0xFFFFFFFF) {
 546                 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 547                                       &clenr0);
 548                 if (res != ERROR_OK) {
 549                         LOG_ERROR("Couldn't read code region 0 size[UICR]");
 550                         return res;
 551                 }
 552         }
 553
 554         for (int i = 0; i < bank->num_sectors; i++)
 555                 bank->sectors[i].is_protected =
 556                         clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
 557
 558         return ERROR_OK;
 559 }
 560
 561 static int nrf51_protect(struct flash_bank *bank, int set, int first, int last)
 562 {
 563         int res;
 564         uint32_t clenr0, ppfc;
 565         struct nrf51_info *chip;
 566
 567         /* UICR cannot be write protected so just bail out early */
 568         if (bank->base == NRF51_UICR_BASE)
 569                 return ERROR_FAIL;
 570
 571         res = nrf51_get_probed_chip_if_halted(bank, &chip);
 572         if (res != ERROR_OK)
 573                 return res;
 574
 575         if (first != 0) {
 576                 LOG_ERROR("Code region 0 must start at the begining of the bank");
 577                 return ERROR_FAIL;
 578         }
 579
 580         res = target_read_u32(chip->target, NRF51_FICR_PPFC,
 581                               &ppfc);
 582         if (res != ERROR_OK) {
 583                 LOG_ERROR("Couldn't read PPFC register");
 584                 return res;
 585         }
 586
 587         if ((ppfc & 0xFF) == 0x00) {
 588                 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
 589                 return ERROR_FAIL;
 590         }
 591
 592         res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 593                               &clenr0);
 594         if (res != ERROR_OK) {
 595                 LOG_ERROR("Couldn't read code region 0 size[UICR]");
 596                 return res;
 597         }
 598
 599         if (clenr0 == 0xFFFFFFFF) {
 600                 res = target_write_u32(chip->target, NRF51_UICR_CLENR0,
 601                                        clenr0);
 602                 if (res != ERROR_OK) {
 603                         LOG_ERROR("Couldn't write code region 0 size[UICR]");
 604                         return res;
 605                 }
 606
 607         } else {
 608                 LOG_ERROR("You need to perform chip erase before changing the protection settings");
 609         }
 610
 611         nrf51_protect_check(bank);
 612
 613         return ERROR_OK;
 614 }
 615
 616 static int nrf51_probe(struct flash_bank *bank)
 617 {
 618         uint32_t hwid;
 619         int res;
 620         struct nrf51_info *chip = bank->driver_priv;
 621
 622         res = target_read_u32(chip->target, NRF51_FICR_CONFIGID, &hwid);
 623         if (res != ERROR_OK) {
 624                 LOG_ERROR("Couldn't read CONFIGID register");
 625                 return res;
 626         }
 627
 628         hwid &= 0xFFFF; /* HWID is stored in the lower two
 629                          * bytes of the CONFIGID register */
 630
 631         const struct nrf51_device_spec *spec = NULL;
 632         for (size_t i = 0; i < ARRAY_SIZE(nrf51_known_devices_table); i++)
 633                 if (hwid == nrf51_known_devices_table[i].hwid) {
 634                         spec = &nrf51_known_devices_table[i];
 635                         break;
 636                 }
 637
 638         if (!chip->bank[0].probed && !chip->bank[1].probed) {
 639                 if (spec)
 640                         LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
 641                                  spec->variant, spec->build_code, spec->flash_size_kb);
 642                 else
 643                         LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
 644         }
 645
 646
 647         if (bank->base == NRF51_FLASH_BASE) {
 648                 res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE,
 649                                       &chip->code_page_size);
 650                 if (res != ERROR_OK) {
 651                         LOG_ERROR("Couldn't read code page size");
 652                         return res;
 653                 }
 654
 655                 res = target_read_u32(chip->target, NRF51_FICR_CODESIZE,
 656                                       &chip->code_memory_size);
 657                 if (res != ERROR_OK) {
 658                         LOG_ERROR("Couldn't read code memory size");
 659                         return res;
 660                 }
 661
 662                 if (spec && chip->code_memory_size != spec->flash_size_kb) {
 663                         LOG_ERROR("Chip's reported Flash capacity does not match expected one");
 664                         return ERROR_FAIL;
 665                 }
 666
 667                 bank->size = chip->code_memory_size * 1024;
 668                 bank->num_sectors = bank->size / chip->code_page_size;
 669                 bank->sectors = calloc(bank->num_sectors,
 670                                        sizeof((bank->sectors)[0]));
 671                 if (!bank->sectors)
 672                         return ERROR_FLASH_BANK_NOT_PROBED;
 673
 674                 /* Fill out the sector information: all NRF51 sectors are the same size and
 675                  * there is always a fixed number of them. */
 676                 for (int i = 0; i < bank->num_sectors; i++) {
 677                         bank->sectors[i].size = chip->code_page_size;
 678                         bank->sectors[i].offset = i * chip->code_page_size;
 679
 680                         /* mark as unknown */
 681                         bank->sectors[i].is_erased = -1;
 682                         bank->sectors[i].is_protected = -1;
 683                 }
 684
 685                 nrf51_protect_check(bank);
 686
 687                 chip->bank[0].probed = true;
 688         } else {
 689                 bank->size = NRF51_UICR_SIZE;
 690                 bank->num_sectors = 1;
 691                 bank->sectors = calloc(bank->num_sectors,
 692                                        sizeof((bank->sectors)[0]));
 693                 if (!bank->sectors)
 694                         return ERROR_FLASH_BANK_NOT_PROBED;
 695
 696                 bank->sectors[0].size = bank->size;
 697                 bank->sectors[0].offset = 0;
 698
 699                 /* mark as unknown */
 700                 bank->sectors[0].is_erased = 0;
 701                 bank->sectors[0].is_protected = 0;
 702
 703                 chip->bank[1].probed = true;
 704         }
 705
 706         return ERROR_OK;
 707 }
 708
 709 static int nrf51_auto_probe(struct flash_bank *bank)
 710 {
 711         int probed = nrf51_bank_is_probed(bank);
 712
 713         if (probed < 0)
 714                 return probed;
 715         else if (probed)
 716                 return ERROR_OK;
 717         else
 718                 return nrf51_probe(bank);
 719 }
 720
 721 static struct flash_sector *nrf51_find_sector_by_address(struct flash_bank *bank, uint32_t address)
 722 {
 723         struct nrf51_info *chip = bank->driver_priv;
 724
 725         for (int i = 0; i < bank->num_sectors; i++)
 726                 if (bank->sectors[i].offset <= address &&
 727                     address < (bank->sectors[i].offset + chip->code_page_size))
 728                         return &bank->sectors[i];
 729         return NULL;
 730 }
 731
 732 static int nrf51_erase_all(struct nrf51_info *chip)
 733 {
 734         LOG_DEBUG("Erasing all non-volatile memory");
 735         return nrf51_nvmc_generic_erase(chip,
 736                                         NRF51_NVMC_ERASEALL,
 737                                         0x00000001);
 738 }
 739
 740 static int nrf51_erase_page(struct flash_bank *bank,
 741                                                         struct nrf51_info *chip,
 742                                                         struct flash_sector *sector)
 743 {
 744         int res;
 745
 746         LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
 747         if (sector->is_protected) {
 748                 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
 749                 return ERROR_FAIL;
 750         }
 751
 752         if (bank->base == NRF51_UICR_BASE) {
 753                 uint32_t ppfc;
 754                 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
 755                                       &ppfc);
 756                 if (res != ERROR_OK) {
 757                         LOG_ERROR("Couldn't read PPFC register");
 758                         return res;
 759                 }
 760
 761                 if ((ppfc & 0xFF) == 0xFF) {
 762                         /* We can't erase the UICR.  Double-check to
 763                            see if it's already erased before complaining. */
 764                         default_flash_blank_check(bank);
 765                         if (sector->is_erased == 1)
 766                                 return ERROR_OK;
 767
 768                         LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
 769                         return ERROR_FAIL;
 770                 }
 771
 772                 res = nrf51_nvmc_generic_erase(chip,
 773                                                NRF51_NVMC_ERASEUICR,
 774                                                0x00000001);
 775
 776
 777         } else {
 778                 res = nrf51_nvmc_generic_erase(chip,
 779                                                NRF51_NVMC_ERASEPAGE,
 780                                                sector->offset);
 781         }
 782
 783         if (res == ERROR_OK)
 784                 sector->is_erased = 1;
 785
 786         return res;
 787 }
 788
 789 static const uint8_t nrf51_flash_write_code[] = {
 790         /* See contrib/loaders/flash/cortex-m0.S */
 791 /* <wait_fifo>: */
 792         0x0d, 0x68,             /* ldr  r5,     [r1,    #0] */
 793         0x00, 0x2d,             /* cmp  r5,     #0 */
 794         0x0b, 0xd0,             /* beq.n        1e <exit> */
 795         0x4c, 0x68,             /* ldr  r4,     [r1,    #4] */
 796         0xac, 0x42,             /* cmp  r4,     r5 */
 797         0xf9, 0xd0,             /* beq.n        0 <wait_fifo> */
 798         0x20, 0xcc,             /* ldmia        r4!,    {r5} */
 799         0x20, 0xc3,             /* stmia        r3!,    {r5} */
 800         0x94, 0x42,             /* cmp  r4,     r2 */
 801         0x01, 0xd3,             /* bcc.n        18 <no_wrap> */
 802         0x0c, 0x46,             /* mov  r4,     r1 */
 803         0x08, 0x34,             /* adds r4,     #8 */
 804 /* <no_wrap>: */
 805         0x4c, 0x60,             /* str  r4, [r1,        #4] */
 806         0x04, 0x38,             /* subs r0, #4 */
 807         0xf0, 0xd1,             /* bne.n        0 <wait_fifo> */
 808 /* <exit>: */
 809         0x00, 0xbe              /* bkpt 0x0000 */
 810 };
 811
 812
 813 /* Start a low level flash write for the specified region */
 814 static int nrf51_ll_flash_write(struct nrf51_info *chip, uint32_t offset, const uint8_t *buffer, uint32_t bytes)
 815 {
 816         struct target *target = chip->target;
 817         uint32_t buffer_size = 8192;
 818         struct working_area *write_algorithm;
 819         struct working_area *source;
 820         uint32_t address = NRF51_FLASH_BASE + offset;
 821         struct reg_param reg_params[4];
 822         struct armv7m_algorithm armv7m_info;
 823         int retval = ERROR_OK;
 824
 825
 826         LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32" bytes=0x%"PRIx32, offset, bytes);
 827         assert(bytes % 4 == 0);
 828
 829         /* allocate working area with flash programming code */
 830         if (target_alloc_working_area(target, sizeof(nrf51_flash_write_code),
 831                         &write_algorithm) != ERROR_OK) {
 832                 LOG_WARNING("no working area available, falling back to slow memory writes");
 833
 834                 for (; bytes > 0; bytes -= 4) {
 835                         retval = target_write_memory(chip->target, offset, 4, 1, buffer);
 836                         if (retval != ERROR_OK)
 837                                 return retval;
 838
 839                         retval = nrf51_wait_for_nvmc(chip);
 840                         if (retval != ERROR_OK)
 841                                 return retval;
 842
 843                         offset += 4;
 844                         buffer += 4;
 845                 }
 846
 847                 return ERROR_OK;
 848         }
 849
 850         LOG_WARNING("using fast async flash loader. This is currently supported");
 851         LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
 852         LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg to disable it");
 853
 854         retval = target_write_buffer(target, write_algorithm->address,
 855                                 sizeof(nrf51_flash_write_code),
 856                                 nrf51_flash_write_code);
 857         if (retval != ERROR_OK)
 858                 return retval;
 859
 860         /* memory buffer */
 861         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
 862                 buffer_size /= 2;
 863                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 864                 if (buffer_size <= 256) {
 865                         /* free working area, write algorithm already allocated */
 866                         target_free_working_area(target, write_algorithm);
 867
 868                         LOG_WARNING("No large enough working area available, can't do block memory writes");
 869                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 870                 }
 871         }
 872
 873         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 874         armv7m_info.core_mode = ARM_MODE_THREAD;
 875
 876         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
 877         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* buffer start */
 878         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer end */
 879         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
 880
 881         buf_set_u32(reg_params[0].value, 0, 32, bytes);
 882         buf_set_u32(reg_params[1].value, 0, 32, source->address);
 883         buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
 884         buf_set_u32(reg_params[3].value, 0, 32, address);
 885
 886         retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
 887                         0, NULL,
 888                         4, reg_params,
 889                         source->address, source->size,
 890                         write_algorithm->address, 0,
 891                         &armv7m_info);
 892
 893         target_free_working_area(target, source);
 894         target_free_working_area(target, write_algorithm);
 895
 896         destroy_reg_param(&reg_params[0]);
 897         destroy_reg_param(&reg_params[1]);
 898         destroy_reg_param(&reg_params[2]);
 899         destroy_reg_param(&reg_params[3]);
 900
 901         return retval;
 902 }
 903
 904 /* Check and erase flash sectors in specified range then start a low level page write.
 905    start/end must be sector aligned.
 906 */
 907 static int nrf51_write_pages(struct flash_bank *bank, uint32_t start, uint32_t end, const uint8_t *buffer)
 908 {
 909         int res = ERROR_FAIL;
 910         struct nrf51_info *chip = bank->driver_priv;
 911         struct flash_sector *sector;
 912         uint32_t offset;
 913
 914         assert(start % chip->code_page_size == 0);
 915         assert(end % chip->code_page_size == 0);
 916
 917         /* Erase all sectors */
 918         for (offset = start; offset < end; offset += chip->code_page_size) {
 919                 sector = nrf51_find_sector_by_address(bank, offset);
 920                 if (!sector) {
 921                         LOG_ERROR("Invalid sector @ 0x%08"PRIx32, offset);
 922                         return ERROR_FLASH_SECTOR_INVALID;
 923                 }
 924
 925                 if (sector->is_protected) {
 926                         LOG_ERROR("Can't erase protected sector @ 0x%08"PRIx32, offset);
 927                         goto error;
 928                 }
 929
 930                 if (sector->is_erased != 1) {   /* 1 = erased, 0= not erased, -1 = unknown */
 931                         res = nrf51_erase_page(bank, chip, sector);
 932                         if (res != ERROR_OK) {
 933                                 LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32, sector->offset);
 934                                 goto error;
 935                         }
 936                 }
 937                 sector->is_erased = 0;
 938         }
 939
 940         res = nrf51_nvmc_write_enable(chip);
 941         if (res != ERROR_OK)
 942                 goto error;
 943
 944         res = nrf51_ll_flash_write(chip, start, buffer, (end - start));
 945         if (res != ERROR_OK)
 946                 goto set_read_only;
 947
 948         return nrf51_nvmc_read_only(chip);
 949
 950 set_read_only:
 951         nrf51_nvmc_read_only(chip);
 952 error:
 953         LOG_ERROR("Failed to write to nrf51 flash");
 954         return res;
 955 }
 956
 957 static int nrf51_erase(struct flash_bank *bank, int first, int last)
 958 {
 959         int res;
 960         struct nrf51_info *chip;
 961
 962         res = nrf51_get_probed_chip_if_halted(bank, &chip);
 963         if (res != ERROR_OK)
 964                 return res;
 965
 966         /* For each sector to be erased */
 967         for (int s = first; s <= last && res == ERROR_OK; s++)
 968                 res = nrf51_erase_page(bank, chip, &bank->sectors[s]);
 969
 970         return res;
 971 }
 972
 973 static int nrf51_code_flash_write(struct flash_bank *bank,
 974                                   struct nrf51_info *chip,
 975                                   const uint8_t *buffer, uint32_t offset, uint32_t count)
 976 {
 977
 978         int res;
 979         /* Need to perform reads to fill any gaps we need to preserve in the first page,
 980            before the start of buffer, or in the last page, after the end of buffer */
 981         uint32_t first_page = offset/chip->code_page_size;
 982         uint32_t last_page = DIV_ROUND_UP(offset+count, chip->code_page_size);
 983
 984         uint32_t first_page_offset = first_page * chip->code_page_size;
 985         uint32_t last_page_offset = last_page * chip->code_page_size;
 986
 987         LOG_DEBUG("Padding write from 0x%08"PRIx32"-0x%08"PRIx32" as 0x%08"PRIx32"-0x%08"PRIx32,
 988                 offset, offset+count, first_page_offset, last_page_offset);
 989
 990         uint32_t page_cnt = last_page - first_page;
 991         uint8_t buffer_to_flash[page_cnt*chip->code_page_size];
 992
 993         /* Fill in any space between start of first page and start of buffer */
 994         uint32_t pre = offset - first_page_offset;
 995         if (pre > 0) {
 996                 res = target_read_memory(bank->target,
 997                                         first_page_offset,
 998                                         1,
 999                                         pre,
1000                                         buffer_to_flash);
1001                 if (res != ERROR_OK)
1002                         return res;
1003         }
1004
1005         /* Fill in main contents of buffer */
1006         memcpy(buffer_to_flash+pre, buffer, count);
1007
1008         /* Fill in any space between end of buffer and end of last page */
1009         uint32_t post = last_page_offset - (offset+count);
1010         if (post > 0) {
1011                 /* Retrieve the full row contents from Flash */
1012                 res = target_read_memory(bank->target,
1013                                         offset + count,
1014                                         1,
1015                                         post,
1016                                         buffer_to_flash+pre+count);
1017                 if (res != ERROR_OK)
1018                         return res;
1019         }
1020
1021         return nrf51_write_pages(bank, first_page_offset, last_page_offset, buffer_to_flash);
1022 }
1023
1024 static int nrf51_uicr_flash_write(struct flash_bank *bank,
1025                                   struct nrf51_info *chip,
1026                                   const uint8_t *buffer, uint32_t offset, uint32_t count)
1027 {
1028         int res;
1029         uint8_t uicr[NRF51_UICR_SIZE];
1030         struct flash_sector *sector = &bank->sectors[0];
1031
1032         if ((offset + count) > NRF51_UICR_SIZE)
1033                 return ERROR_FAIL;
1034
1035         res = target_read_memory(bank->target,
1036                                  NRF51_UICR_BASE,
1037                                  1,
1038                                  NRF51_UICR_SIZE,
1039                                  uicr);
1040
1041         if (res != ERROR_OK)
1042                 return res;
1043
1044         if (sector->is_erased != 1) {
1045                 res = nrf51_erase_page(bank, chip, sector);
1046                 if (res != ERROR_OK)
1047                         return res;
1048         }
1049
1050         res = nrf51_nvmc_write_enable(chip);
1051         if (res != ERROR_OK)
1052                 return res;
1053
1054         memcpy(&uicr[offset], buffer, count);
1055
1056         res = nrf51_ll_flash_write(chip, NRF51_UICR_BASE, uicr, NRF51_UICR_SIZE);
1057         if (res != ERROR_OK) {
1058                 nrf51_nvmc_read_only(chip);
1059                 return res;
1060         }
1061
1062         return nrf51_nvmc_read_only(chip);
1063 }
1064
1065
1066 static int nrf51_write(struct flash_bank *bank, const uint8_t *buffer,
1067                        uint32_t offset, uint32_t count)
1068 {
1069         int res;
1070         struct nrf51_info *chip;
1071
1072         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1073         if (res != ERROR_OK)
1074                 return res;
1075
1076         return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, count);
1077 }
1078
1079
1080 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command)
1081 {
1082         static struct nrf51_info *chip;
1083
1084         switch (bank->base) {
1085         case NRF51_FLASH_BASE:
1086                 bank->bank_number = 0;
1087                 break;
1088         case NRF51_UICR_BASE:
1089                 bank->bank_number = 1;
1090                 break;
1091         default:
1092                 LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
1093                 return ERROR_FAIL;
1094         }
1095
1096         if (!chip) {
1097                 /* Create a new chip */
1098                 chip = calloc(1, sizeof(*chip));
1099                 if (!chip)
1100                         return ERROR_FAIL;
1101
1102                 chip->target = bank->target;
1103         }
1104
1105         switch (bank->base) {
1106         case NRF51_FLASH_BASE:
1107                 chip->bank[bank->bank_number].write = nrf51_code_flash_write;
1108                 break;
1109         case NRF51_UICR_BASE:
1110                 chip->bank[bank->bank_number].write = nrf51_uicr_flash_write;
1111                 break;
1112         }
1113
1114         chip->bank[bank->bank_number].probed = false;
1115         bank->driver_priv = chip;
1116
1117         return ERROR_OK;
1118 }
1119
1120 COMMAND_HANDLER(nrf51_handle_mass_erase_command)
1121 {
1122         int res;
1123         struct flash_bank *bank = NULL;
1124         struct target *target = get_current_target(CMD_CTX);
1125
1126         res = get_flash_bank_by_addr(target, NRF51_FLASH_BASE, true, &bank);
1127         if (res != ERROR_OK)
1128                 return res;
1129
1130         assert(bank != NULL);
1131
1132         struct nrf51_info *chip;
1133
1134         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1135         if (res != ERROR_OK)
1136                 return res;
1137
1138         uint32_t ppfc;
1139
1140         res = target_read_u32(target, NRF51_FICR_PPFC,
1141                               &ppfc);
1142         if (res != ERROR_OK) {
1143                 LOG_ERROR("Couldn't read PPFC register");
1144                 return res;
1145         }
1146
1147         if ((ppfc & 0xFF) == 0x00) {
1148                 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1149                           "mass erase command won't work.");
1150                 return ERROR_FAIL;
1151         }
1152
1153         res = nrf51_erase_all(chip);
1154         if (res != ERROR_OK) {
1155                 LOG_ERROR("Failed to erase the chip");
1156                 nrf51_protect_check(bank);
1157                 return res;
1158         }
1159
1160         for (int i = 0; i < bank->num_sectors; i++)
1161                 bank->sectors[i].is_erased = 1;
1162
1163         res = nrf51_protect_check(bank);
1164         if (res != ERROR_OK) {
1165                 LOG_ERROR("Failed to check chip's write protection");
1166                 return res;
1167         }
1168
1169         res = get_flash_bank_by_addr(target, NRF51_UICR_BASE, true, &bank);
1170         if (res != ERROR_OK)
1171                 return res;
1172
1173         bank->sectors[0].is_erased = 1;
1174
1175         return ERROR_OK;
1176 }
1177
1178 static int nrf51_info(struct flash_bank *bank, char *buf, int buf_size)
1179 {
1180         int res;
1181
1182         struct nrf51_info *chip;
1183
1184         res = nrf51_get_probed_chip_if_halted(bank, &chip);
1185         if (res != ERROR_OK)
1186                 return res;
1187
1188         static struct {
1189                 const uint32_t address;
1190                 uint32_t value;
1191         } ficr[] = {
1192                 { .address = NRF51_FICR_CODEPAGESIZE    },
1193                 { .address = NRF51_FICR_CODESIZE        },
1194                 { .address = NRF51_FICR_CLENR0          },
1195                 { .address = NRF51_FICR_PPFC            },
1196                 { .address = NRF51_FICR_NUMRAMBLOCK     },
1197                 { .address = NRF51_FICR_SIZERAMBLOCK0   },
1198                 { .address = NRF51_FICR_SIZERAMBLOCK1   },
1199                 { .address = NRF51_FICR_SIZERAMBLOCK2   },
1200                 { .address = NRF51_FICR_SIZERAMBLOCK3   },
1201                 { .address = NRF51_FICR_CONFIGID        },
1202                 { .address = NRF51_FICR_DEVICEID0       },
1203                 { .address = NRF51_FICR_DEVICEID1       },
1204                 { .address = NRF51_FICR_ER0             },
1205                 { .address = NRF51_FICR_ER1             },
1206                 { .address = NRF51_FICR_ER2             },
1207                 { .address = NRF51_FICR_ER3             },
1208                 { .address = NRF51_FICR_IR0             },
1209                 { .address = NRF51_FICR_IR1             },
1210                 { .address = NRF51_FICR_IR2             },
1211                 { .address = NRF51_FICR_IR3             },
1212                 { .address = NRF51_FICR_DEVICEADDRTYPE  },
1213                 { .address = NRF51_FICR_DEVICEADDR0     },
1214                 { .address = NRF51_FICR_DEVICEADDR1     },
1215                 { .address = NRF51_FICR_OVERRIDEN       },
1216                 { .address = NRF51_FICR_NRF_1MBIT0      },
1217                 { .address = NRF51_FICR_NRF_1MBIT1      },
1218                 { .address = NRF51_FICR_NRF_1MBIT2      },
1219                 { .address = NRF51_FICR_NRF_1MBIT3      },
1220                 { .address = NRF51_FICR_NRF_1MBIT4      },
1221                 { .address = NRF51_FICR_BLE_1MBIT0      },
1222                 { .address = NRF51_FICR_BLE_1MBIT1      },
1223                 { .address = NRF51_FICR_BLE_1MBIT2      },
1224                 { .address = NRF51_FICR_BLE_1MBIT3      },
1225                 { .address = NRF51_FICR_BLE_1MBIT4      },
1226         }, uicr[] = {
1227                 { .address = NRF51_UICR_CLENR0,         },
1228                 { .address = NRF51_UICR_RBPCONF         },
1229                 { .address = NRF51_UICR_XTALFREQ        },
1230                 { .address = NRF51_UICR_FWID            },
1231         };
1232
1233         for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1234                 res = target_read_u32(chip->target, ficr[i].address,
1235                                       &ficr[i].value);
1236                 if (res != ERROR_OK) {
1237                         LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1238                         return res;
1239                 }
1240         }
1241
1242         for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1243                 res = target_read_u32(chip->target, uicr[i].address,
1244                                       &uicr[i].value);
1245                 if (res != ERROR_OK) {
1246                         LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1247                         return res;
1248                 }
1249         }
1250
1251         snprintf(buf, buf_size,
1252                  "\n[factory information control block]\n\n"
1253                  "code page size: %"PRIu32"B\n"
1254                  "code memory size: %"PRIu32"kB\n"
1255                  "code region 0 size: %"PRIu32"kB\n"
1256                  "pre-programmed code: %s\n"
1257                  "number of ram blocks: %"PRIu32"\n"
1258                  "ram block 0 size: %"PRIu32"B\n"
1259                  "ram block 1 size: %"PRIu32"B\n"
1260                  "ram block 2 size: %"PRIu32"B\n"
1261                  "ram block 3 size: %"PRIu32 "B\n"
1262                  "config id: %" PRIx32 "\n"
1263                  "device id: 0x%"PRIx32"%08"PRIx32"\n"
1264                  "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1265                  "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1266                  "device address type: 0x%"PRIx32"\n"
1267                  "device address: 0x%"PRIx32"%08"PRIx32"\n"
1268                  "override enable: %"PRIx32"\n"
1269                  "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1270                  "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1271                  "\n[user information control block]\n\n"
1272                  "code region 0 size: %"PRIu32"kB\n"
1273                  "read back protection configuration: %"PRIx32"\n"
1274                  "reset value for XTALFREQ: %"PRIx32"\n"
1275                  "firmware id: 0x%04"PRIx32,
1276                  ficr[0].value,
1277                  ficr[1].value,
1278                  (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1279                  ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1280                  ficr[4].value,
1281                  ficr[5].value,
1282                  (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1283                  (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1284                  (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1285                  ficr[9].value,
1286                  ficr[10].value, ficr[11].value,
1287                  ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1288                  ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1289                  ficr[20].value,
1290                  ficr[21].value, ficr[22].value,
1291                  ficr[23].value,
1292                  ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1293                  ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1294                  (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1295                  uicr[1].value & 0xFFFF,
1296                  uicr[2].value & 0xFF,
1297                  uicr[3].value & 0xFFFF);
1298
1299         return ERROR_OK;
1300 }
1301
1302 static const struct command_registration nrf51_exec_command_handlers[] = {
1303         {
1304                 .name           = "mass_erase",
1305                 .handler        = nrf51_handle_mass_erase_command,
1306                 .mode           = COMMAND_EXEC,
1307                 .help           = "Erase all flash contents of the chip.",
1308         },
1309         COMMAND_REGISTRATION_DONE
1310 };
1311
1312 static const struct command_registration nrf51_command_handlers[] = {
1313         {
1314                 .name   = "nrf51",
1315                 .mode   = COMMAND_ANY,
1316                 .help   = "nrf51 flash command group",
1317                 .usage  = "",
1318                 .chain  = nrf51_exec_command_handlers,
1319         },
1320         COMMAND_REGISTRATION_DONE
1321 };
1322
1323 struct flash_driver nrf51_flash = {
1324         .name                   = "nrf51",
1325         .commands               = nrf51_command_handlers,
1326         .flash_bank_command     = nrf51_flash_bank_command,
1327         .info                   = nrf51_info,
1328         .erase                  = nrf51_erase,
1329         .protect                = nrf51_protect,
1330         .write                  = nrf51_write,
1331         .read                   = default_flash_read,
1332         .probe                  = nrf51_probe,
1333         .auto_probe             = nrf51_auto_probe,
1334         .erase_check            = default_flash_blank_check,
1335         .protect_check          = nrf51_protect_check,
1336 };