git.gag.com Git - fw/openocd/blob - src/flash/nor/nrf5.c

   1 /***************************************************************************
   2  *   Copyright (C) 2013 Synapse Product Development                        *
   3  *   Andrey Smirnov <andrew.smironv@gmail.com>                             *
   4  *   Angus Gratton <gus@projectgus.com>                                    *
   5  *   Erdem U. Altunyurt <spamjunkeater@gmail.com>                          *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include "imp.h"
  26 #include <target/algorithm.h>
  27 #include <target/armv7m.h>
  28 #include <helper/types.h>
  29 #include <helper/time_support.h>
  30
  31 /* Both those values are constant across the current spectrum ofr nRF5 devices */
  32 #define WATCHDOG_REFRESH_REGISTER       0x40010600
  33 #define WATCHDOG_REFRESH_VALUE          0x6e524635
  34
  35 enum {
  36         NRF5_FLASH_BASE = 0x00000000,
  37 };
  38
  39 enum nrf5_ficr_registers {
  40         NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
  41
  42 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
  43
  44         NRF5_FICR_CODEPAGESIZE          = NRF5_FICR_REG(0x010),
  45         NRF5_FICR_CODESIZE              = NRF5_FICR_REG(0x014),
  46
  47         NRF51_FICR_CLENR0               = NRF5_FICR_REG(0x028),
  48         NRF51_FICR_PPFC                 = NRF5_FICR_REG(0x02C),
  49         NRF51_FICR_NUMRAMBLOCK          = NRF5_FICR_REG(0x034),
  50         NRF51_FICR_SIZERAMBLOCK0        = NRF5_FICR_REG(0x038),
  51         NRF51_FICR_SIZERAMBLOCK1        = NRF5_FICR_REG(0x03C),
  52         NRF51_FICR_SIZERAMBLOCK2        = NRF5_FICR_REG(0x040),
  53         NRF51_FICR_SIZERAMBLOCK3        = NRF5_FICR_REG(0x044),
  54
  55         NRF5_FICR_CONFIGID              = NRF5_FICR_REG(0x05C),
  56         NRF5_FICR_DEVICEID0             = NRF5_FICR_REG(0x060),
  57         NRF5_FICR_DEVICEID1             = NRF5_FICR_REG(0x064),
  58         NRF5_FICR_ER0                   = NRF5_FICR_REG(0x080),
  59         NRF5_FICR_ER1                   = NRF5_FICR_REG(0x084),
  60         NRF5_FICR_ER2                   = NRF5_FICR_REG(0x088),
  61         NRF5_FICR_ER3                   = NRF5_FICR_REG(0x08C),
  62         NRF5_FICR_IR0                   = NRF5_FICR_REG(0x090),
  63         NRF5_FICR_IR1                   = NRF5_FICR_REG(0x094),
  64         NRF5_FICR_IR2                   = NRF5_FICR_REG(0x098),
  65         NRF5_FICR_IR3                   = NRF5_FICR_REG(0x09C),
  66         NRF5_FICR_DEVICEADDRTYPE        = NRF5_FICR_REG(0x0A0),
  67         NRF5_FICR_DEVICEADDR0           = NRF5_FICR_REG(0x0A4),
  68         NRF5_FICR_DEVICEADDR1           = NRF5_FICR_REG(0x0A8),
  69
  70         NRF51_FICR_OVERRIDEN            = NRF5_FICR_REG(0x0AC),
  71         NRF51_FICR_NRF_1MBIT0           = NRF5_FICR_REG(0x0B0),
  72         NRF51_FICR_NRF_1MBIT1           = NRF5_FICR_REG(0x0B4),
  73         NRF51_FICR_NRF_1MBIT2           = NRF5_FICR_REG(0x0B8),
  74         NRF51_FICR_NRF_1MBIT3           = NRF5_FICR_REG(0x0BC),
  75         NRF51_FICR_NRF_1MBIT4           = NRF5_FICR_REG(0x0C0),
  76         NRF51_FICR_BLE_1MBIT0           = NRF5_FICR_REG(0x0EC),
  77         NRF51_FICR_BLE_1MBIT1           = NRF5_FICR_REG(0x0F0),
  78         NRF51_FICR_BLE_1MBIT2           = NRF5_FICR_REG(0x0F4),
  79         NRF51_FICR_BLE_1MBIT3           = NRF5_FICR_REG(0x0F8),
  80         NRF51_FICR_BLE_1MBIT4           = NRF5_FICR_REG(0x0FC),
  81
  82         /* Following registers are available on nRF52 and on nRF51 since rev 3 */
  83         NRF5_FICR_INFO_PART                     = NRF5_FICR_REG(0x100),
  84         NRF5_FICR_INFO_VARIANT          = NRF5_FICR_REG(0x104),
  85         NRF5_FICR_INFO_PACKAGE          = NRF5_FICR_REG(0x108),
  86         NRF5_FICR_INFO_RAM                      = NRF5_FICR_REG(0x10C),
  87         NRF5_FICR_INFO_FLASH            = NRF5_FICR_REG(0x110),
  88 };
  89
  90 enum nrf5_uicr_registers {
  91         NRF5_UICR_BASE = 0x10001000, /* User Information
  92                                        * Configuration Registers */
  93
  94 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
  95
  96         NRF51_UICR_CLENR0       = NRF5_UICR_REG(0x000),
  97         NRF51_UICR_RBPCONF      = NRF5_UICR_REG(0x004),
  98         NRF51_UICR_XTALFREQ     = NRF5_UICR_REG(0x008),
  99         NRF51_UICR_FWID         = NRF5_UICR_REG(0x010),
 100 };
 101
 102 enum nrf5_nvmc_registers {
 103         NRF5_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
 104                                        * Controller Registers */
 105
 106 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
 107
 108         NRF5_NVMC_READY = NRF5_NVMC_REG(0x400),
 109         NRF5_NVMC_CONFIG        = NRF5_NVMC_REG(0x504),
 110         NRF5_NVMC_ERASEPAGE     = NRF5_NVMC_REG(0x508),
 111         NRF5_NVMC_ERASEALL      = NRF5_NVMC_REG(0x50C),
 112         NRF5_NVMC_ERASEUICR     = NRF5_NVMC_REG(0x514),
 113
 114         NRF5_BPROT_BASE = 0x40000000,
 115 };
 116
 117 enum nrf5_nvmc_config_bits {
 118         NRF5_NVMC_CONFIG_REN = 0x00,
 119         NRF5_NVMC_CONFIG_WEN = 0x01,
 120         NRF5_NVMC_CONFIG_EEN = 0x02,
 121
 122 };
 123
 124 struct nrf52_ficr_info {
 125         uint32_t part;
 126         uint32_t variant;
 127         uint32_t package;
 128         uint32_t ram;
 129         uint32_t flash;
 130 };
 131
 132 enum nrf5_features {
 133         NRF5_FEATURE_SERIES_51  = 1 << 0,
 134         NRF5_FEATURE_SERIES_52  = 1 << 1,
 135         NRF5_FEATURE_BPROT              = 1 << 2,
 136         NRF5_FEATURE_ACL_PROT   = 1 << 3,
 137 };
 138
 139 struct nrf5_device_spec {
 140         uint16_t hwid;
 141         const char *part;
 142         const char *variant;
 143         const char *build_code;
 144         unsigned int flash_size_kb;
 145         enum nrf5_features features;
 146 };
 147
 148 struct nrf5_info {
 149         uint32_t refcount;
 150
 151         struct nrf5_bank {
 152                 struct nrf5_info *chip;
 153                 bool probed;
 154         } bank[2];
 155         struct target *target;
 156
 157         /* chip identification stored in nrf5_probe() for use in nrf5_info() */
 158         bool ficr_info_valid;
 159         struct nrf52_ficr_info ficr_info;
 160         const struct nrf5_device_spec *spec;
 161         uint16_t hwid;
 162         enum nrf5_features features;
 163         unsigned int flash_size_kb;
 164         unsigned int ram_size_kb;
 165 };
 166
 167 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
 168 {                                                   \
 169 .hwid          = (id),                              \
 170 .part          = pt,                                \
 171 .variant       = var,                               \
 172 .build_code    = bcode,                             \
 173 .flash_size_kb = (fsize),                           \
 174 .features      = NRF5_FEATURE_SERIES_51,            \
 175 }
 176
 177 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize, features) \
 178 {                                                   \
 179 .hwid          = (id),                              \
 180 .part          = pt,                                \
 181 .variant       = var,                               \
 182 .build_code    = bcode,                             \
 183 .flash_size_kb = (fsize),                           \
 184 .features      = features,                          \
 185 }
 186
 187 /* The known devices table below is derived from the "nRF5x series
 188  * compatibility matrix" documents, which can be found in the "DocLib" of
 189  * nordic:
 190  *
 191  * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51422_ic_revision_overview
 192  * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51822_ic_revision_overview
 193  * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51824_ic_revision_overview
 194  * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52810/latest/COMP/nrf52810/nRF52810_ic_revision_overview
 195  * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52832/latest/COMP/nrf52832/ic_revision_overview
 196  * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52840/latest/COMP/nrf52840/nRF52840_ic_revision_overview
 197  *
 198  * Up to date with Matrix v2.0, plus some additional HWIDs.
 199  *
 200  * The additional HWIDs apply where the build code in the matrix is
 201  * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
 202  * for x==0, x!=0 means different (unspecified) HWIDs.
 203  */
 204 static const struct nrf5_device_spec nrf5_known_devices_table[] = {
 205         /* nRF51822 Devices (IC rev 1). */
 206         NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
 207         NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA",    128),
 208         NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0",    128),
 209         NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA",    256),
 210         NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0",    256),
 211
 212         /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
 213            with built-in jlink seem to use engineering samples not listed
 214            in the nRF51 Series Compatibility Matrix V1.0. */
 215         NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB",    256),
 216
 217         /* nRF51822 Devices (IC rev 2). */
 218         NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0",   256),
 219         NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0",   256),
 220         NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0",    256),
 221         NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2",    256),
 222         NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3",    256),
 223         NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0",    128),
 224         NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0",   256),
 225         NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0",   256),
 226         NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00",   256),
 227
 228         /* nRF51822 Devices (IC rev 3). */
 229         NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0",    256),
 230         NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2",    256),
 231         NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0",    128),
 232         NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0",    256),
 233         NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1",    256),
 234         NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0",    128),
 235         NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0",    256),
 236         NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0",    256),
 237         NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1",    256),
 238
 239         /* nRF51422 Devices (IC rev 1). */
 240         NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA",    256),
 241         NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0",    256),
 242         NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A",   256),
 243
 244         /* nRF51422 Devices (IC rev 2). */
 245         NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA",   256),
 246         NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0",    256),
 247         NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00",   128),
 248         NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0",    256),
 249
 250         /* nRF51422 Devices (IC rev 3). */
 251         NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0",    256),
 252         NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0",    128),
 253         NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0",    256),
 254         NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1",    256),
 255         NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0",    128),
 256         NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0",    256),
 257         NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0",    256),
 258
 259         /* The driver fully autodetects nRF52 series devices by FICR INFO,
 260          * no need for nRF52xxx HWIDs in this table */
 261 #if 0
 262         /* nRF52810 Devices */
 263         NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0",    192,  NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
 264         NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0",    192,  NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
 265
 266         /* nRF52832 Devices */
 267         NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0",    512,  NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
 268         NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0",    512,  NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
 269         NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0",    512,  NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
 270
 271         /* nRF52840 Devices */
 272         NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0",    1024, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_ACL_PROT),
 273 #endif
 274 };
 275
 276 struct nrf5_device_package {
 277         uint32_t package;
 278         const char *code;
 279 };
 280
 281 /* Newer devices have FICR INFO.PACKAGE.
 282  * This table converts its value to two character code */
 283 static const struct nrf5_device_package nrf5_packages_table[] = {
 284         { 0x2000, "QF" },
 285         { 0x2001, "CH" },
 286         { 0x2002, "CI" },
 287         { 0x2005, "CK" },
 288 };
 289
 290 const struct flash_driver nrf5_flash, nrf51_flash;
 291
 292 static bool nrf5_bank_is_probed(const struct flash_bank *bank)
 293 {
 294         struct nrf5_bank *nbank = bank->driver_priv;
 295
 296         assert(nbank);
 297
 298         return nbank->probed;
 299 }
 300 static int nrf5_probe(struct flash_bank *bank);
 301
 302 static int nrf5_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf5_info **chip)
 303 {
 304         if (bank->target->state != TARGET_HALTED) {
 305                 LOG_ERROR("Target not halted");
 306                 return ERROR_TARGET_NOT_HALTED;
 307         }
 308
 309         struct nrf5_bank *nbank = bank->driver_priv;
 310         *chip = nbank->chip;
 311
 312         if (nrf5_bank_is_probed(bank))
 313                 return ERROR_OK;
 314
 315         return nrf5_probe(bank);
 316 }
 317
 318 static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
 319 {
 320         uint32_t ready;
 321         int res;
 322         int timeout_ms = 340;
 323         int64_t ts_start = timeval_ms();
 324
 325         do {
 326                 res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready);
 327                 if (res != ERROR_OK) {
 328                         LOG_ERROR("Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)");
 329                         return res;
 330                 }
 331
 332                 if (ready == 0x00000001)
 333                         return ERROR_OK;
 334
 335                 keep_alive();
 336
 337         } while ((timeval_ms()-ts_start) < timeout_ms);
 338
 339         LOG_DEBUG("Timed out waiting for NVMC_READY");
 340         return ERROR_FLASH_BUSY;
 341 }
 342
 343 static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
 344 {
 345         int res;
 346         res = target_write_u32(chip->target,
 347                                NRF5_NVMC_CONFIG,
 348                                NRF5_NVMC_CONFIG_EEN);
 349
 350         if (res != ERROR_OK) {
 351                 LOG_ERROR("Failed to enable erase operation");
 352                 return res;
 353         }
 354
 355         /*
 356           According to NVMC examples in Nordic SDK busy status must be
 357           checked after writing to NVMC_CONFIG
 358          */
 359         res = nrf5_wait_for_nvmc(chip);
 360         if (res != ERROR_OK)
 361                 LOG_ERROR("Erase enable did not complete");
 362
 363         return res;
 364 }
 365
 366 static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
 367 {
 368         int res;
 369         res = target_write_u32(chip->target,
 370                                NRF5_NVMC_CONFIG,
 371                                NRF5_NVMC_CONFIG_WEN);
 372
 373         if (res != ERROR_OK) {
 374                 LOG_ERROR("Failed to enable write operation");
 375                 return res;
 376         }
 377
 378         /*
 379           According to NVMC examples in Nordic SDK busy status must be
 380           checked after writing to NVMC_CONFIG
 381          */
 382         res = nrf5_wait_for_nvmc(chip);
 383         if (res != ERROR_OK)
 384                 LOG_ERROR("Write enable did not complete");
 385
 386         return res;
 387 }
 388
 389 static int nrf5_nvmc_read_only(struct nrf5_info *chip)
 390 {
 391         int res;
 392         res = target_write_u32(chip->target,
 393                                NRF5_NVMC_CONFIG,
 394                                NRF5_NVMC_CONFIG_REN);
 395
 396         if (res != ERROR_OK) {
 397                 LOG_ERROR("Failed to enable read-only operation");
 398                 return res;
 399         }
 400         /*
 401           According to NVMC examples in Nordic SDK busy status must be
 402           checked after writing to NVMC_CONFIG
 403          */
 404         res = nrf5_wait_for_nvmc(chip);
 405         if (res != ERROR_OK)
 406                 LOG_ERROR("Read only enable did not complete");
 407
 408         return res;
 409 }
 410
 411 static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
 412                                uint32_t erase_register, uint32_t erase_value)
 413 {
 414         int res;
 415
 416         res = nrf5_nvmc_erase_enable(chip);
 417         if (res != ERROR_OK)
 418                 goto error;
 419
 420         res = target_write_u32(chip->target,
 421                                erase_register,
 422                                erase_value);
 423         if (res != ERROR_OK)
 424                 goto set_read_only;
 425
 426         res = nrf5_wait_for_nvmc(chip);
 427         if (res != ERROR_OK)
 428                 goto set_read_only;
 429
 430         return nrf5_nvmc_read_only(chip);
 431
 432 set_read_only:
 433         nrf5_nvmc_read_only(chip);
 434 error:
 435         LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
 436                   erase_register, erase_value);
 437         return ERROR_FAIL;
 438 }
 439
 440 static int nrf5_protect_check_clenr0(struct flash_bank *bank)
 441 {
 442         int res;
 443         uint32_t clenr0;
 444         struct nrf5_bank *nbank = bank->driver_priv;
 445         struct nrf5_info *chip = nbank->chip;
 446
 447         assert(chip);
 448
 449         res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
 450                               &clenr0);
 451         if (res != ERROR_OK) {
 452                 LOG_ERROR("Couldn't read code region 0 size[FICR]");
 453                 return res;
 454         }
 455
 456         if (clenr0 == 0xFFFFFFFF) {
 457                 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 458                                       &clenr0);
 459                 if (res != ERROR_OK) {
 460                         LOG_ERROR("Couldn't read code region 0 size[UICR]");
 461                         return res;
 462                 }
 463         }
 464
 465         for (unsigned int i = 0; i < bank->num_sectors; i++)
 466                 bank->sectors[i].is_protected =
 467                         clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
 468
 469         return ERROR_OK;
 470 }
 471
 472 static int nrf5_protect_check_bprot(struct flash_bank *bank)
 473 {
 474         struct nrf5_bank *nbank = bank->driver_priv;
 475         struct nrf5_info *chip = nbank->chip;
 476
 477         assert(chip);
 478
 479         static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 };
 480         uint32_t bprot_reg = 0;
 481         int res;
 482
 483         for (unsigned int i = 0; i < bank->num_sectors; i++) {
 484                 unsigned int bit = i % 32;
 485                 if (bit == 0) {
 486                         unsigned int n_reg = i / 32;
 487                         if (n_reg >= ARRAY_SIZE(nrf5_bprot_offsets))
 488                                 break;
 489
 490                         res = target_read_u32(chip->target, NRF5_BPROT_BASE + nrf5_bprot_offsets[n_reg], &bprot_reg);
 491                         if (res != ERROR_OK)
 492                                 return res;
 493                 }
 494                 bank->sectors[i].is_protected = (bprot_reg & (1 << bit)) ? 1 : 0;
 495         }
 496         return ERROR_OK;
 497 }
 498
 499 static int nrf5_protect_check(struct flash_bank *bank)
 500 {
 501         /* UICR cannot be write protected so just return early */
 502         if (bank->base == NRF5_UICR_BASE)
 503                 return ERROR_OK;
 504
 505         struct nrf5_bank *nbank = bank->driver_priv;
 506         struct nrf5_info *chip = nbank->chip;
 507
 508         assert(chip);
 509
 510         if (chip->features & NRF5_FEATURE_BPROT)
 511                 return nrf5_protect_check_bprot(bank);
 512
 513         if (chip->features & NRF5_FEATURE_SERIES_51)
 514                 return nrf5_protect_check_clenr0(bank);
 515
 516         LOG_WARNING("Flash protection of this nRF device is not supported");
 517         return ERROR_FLASH_OPER_UNSUPPORTED;
 518 }
 519
 520 static int nrf5_protect_clenr0(struct flash_bank *bank, int set, unsigned int first,
 521                 unsigned int last)
 522 {
 523         int res;
 524         uint32_t clenr0, ppfc;
 525         struct nrf5_bank *nbank = bank->driver_priv;
 526         struct nrf5_info *chip = nbank->chip;
 527
 528         if (first != 0) {
 529                 LOG_ERROR("Code region 0 must start at the beginning of the bank");
 530                 return ERROR_FAIL;
 531         }
 532
 533         res = target_read_u32(chip->target, NRF51_FICR_PPFC,
 534                               &ppfc);
 535         if (res != ERROR_OK) {
 536                 LOG_ERROR("Couldn't read PPFC register");
 537                 return res;
 538         }
 539
 540         if ((ppfc & 0xFF) == 0x00) {
 541                 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
 542                 return ERROR_FAIL;
 543         }
 544
 545         res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 546                               &clenr0);
 547         if (res != ERROR_OK) {
 548                 LOG_ERROR("Couldn't read code region 0 size from UICR");
 549                 return res;
 550         }
 551
 552         if (!set || clenr0 != 0xFFFFFFFF) {
 553                 LOG_ERROR("You need to perform chip erase before changing the protection settings");
 554                 return ERROR_FAIL;
 555         }
 556
 557         res = nrf5_nvmc_write_enable(chip);
 558         if (res != ERROR_OK)
 559                 goto error;
 560
 561         clenr0 = bank->sectors[last].offset + bank->sectors[last].size;
 562         res = target_write_u32(chip->target, NRF51_UICR_CLENR0, clenr0);
 563
 564         int res2 = nrf5_wait_for_nvmc(chip);
 565
 566         if (res == ERROR_OK)
 567                 res = res2;
 568
 569         if (res == ERROR_OK)
 570                 LOG_INFO("A reset or power cycle is required for the new protection settings to take effect.");
 571         else
 572                 LOG_ERROR("Couldn't write code region 0 size to UICR");
 573
 574 error:
 575         nrf5_nvmc_read_only(chip);
 576
 577         return res;
 578 }
 579
 580 static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
 581                 unsigned int last)
 582 {
 583         int res;
 584         struct nrf5_info *chip;
 585
 586         /* UICR cannot be write protected so just bail out early */
 587         if (bank->base == NRF5_UICR_BASE) {
 588                 LOG_ERROR("UICR page does not support protection");
 589                 return ERROR_FLASH_OPER_UNSUPPORTED;
 590         }
 591
 592         res = nrf5_get_probed_chip_if_halted(bank, &chip);
 593         if (res != ERROR_OK)
 594                 return res;
 595
 596         if (chip->features & NRF5_FEATURE_SERIES_51)
 597                 return nrf5_protect_clenr0(bank, set, first, last);
 598
 599         LOG_ERROR("Flash protection setting is not supported on this nRF5 device");
 600         return ERROR_FLASH_OPER_UNSUPPORTED;
 601 }
 602
 603 static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
 604 {
 605         uint8_t b[4];
 606
 607         h_u32_to_be(b, variant);
 608         if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && isalnum(b[3])) {
 609                 memcpy(bf, b, 4);
 610                 bf[4] = 0;
 611                 return true;
 612         }
 613
 614         strcpy(bf, "xxxx");
 615         return false;
 616 }
 617
 618 static const char *nrf5_decode_info_package(uint32_t package)
 619 {
 620         for (size_t i = 0; i < ARRAY_SIZE(nrf5_packages_table); i++) {
 621                 if (nrf5_packages_table[i].package == package)
 622                         return nrf5_packages_table[i].code;
 623         }
 624         return "xx";
 625 }
 626
 627 static int get_nrf5_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size)
 628 {
 629         int res;
 630         if (chip->spec) {
 631                 res = snprintf(buf, buf_size, "nRF%s-%s(build code: %s)",
 632                                 chip->spec->part, chip->spec->variant, chip->spec->build_code);
 633         } else if (chip->ficr_info_valid) {
 634                 char variant[5];
 635                 nrf5_info_variant_to_str(chip->ficr_info.variant, variant);
 636                 res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s%.2s(build code: %s)",
 637                                 chip->ficr_info.part,
 638                                 nrf5_decode_info_package(chip->ficr_info.package),
 639                                 variant, &variant[2]);
 640         } else {
 641                 res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ")", chip->hwid);
 642         }
 643
 644         /* safety: */
 645         if (res <= 0 || (unsigned int)res >= buf_size) {
 646                 LOG_ERROR("BUG: buffer problem in %s", __func__);
 647                 return ERROR_FAIL;
 648         }
 649         return ERROR_OK;
 650 }
 651
 652 static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
 653 {
 654         struct nrf5_bank *nbank = bank->driver_priv;
 655         struct nrf5_info *chip = nbank->chip;
 656
 657         char chip_type_str[256];
 658         if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
 659                 return ERROR_FAIL;
 660
 661         command_print_sameline(cmd, "%s %ukB Flash, %ukB RAM",
 662                         chip_type_str, chip->flash_size_kb, chip->ram_size_kb);
 663         return ERROR_OK;
 664 }
 665
 666 static int nrf5_read_ficr_info(struct nrf5_info *chip)
 667 {
 668         int res;
 669         struct target *target = chip->target;
 670
 671         chip->ficr_info_valid = false;
 672
 673         res = target_read_u32(target, NRF5_FICR_INFO_PART, &chip->ficr_info.part);
 674         if (res != ERROR_OK) {
 675                 LOG_DEBUG("Couldn't read FICR INFO.PART register");
 676                 return res;
 677         }
 678
 679         uint32_t series = chip->ficr_info.part & 0xfffff000;
 680         switch (series) {
 681         case 0x51000:
 682                 chip->features = NRF5_FEATURE_SERIES_51;
 683                 break;
 684
 685         case 0x52000:
 686                 chip->features = NRF5_FEATURE_SERIES_52;
 687
 688                 switch (chip->ficr_info.part) {
 689                 case 0x52810:
 690                 case 0x52832:
 691                         chip->features |= NRF5_FEATURE_BPROT;
 692                         break;
 693
 694                 case 0x52840:
 695                         chip->features |= NRF5_FEATURE_ACL_PROT;
 696                         break;
 697                 }
 698                 break;
 699
 700         default:
 701                 LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
 702                                 PRIx32, chip->ficr_info.part);
 703                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 704         }
 705
 706         /* Now we know the device has FICR INFO filled by something relevant:
 707          * Although it is not documented, the tested nRF51 rev 3 devices
 708          * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
 709          * VARIANT and PACKAGE coding is unknown for a nRF51 device.
 710          * nRF52 devices have FICR INFO documented and always filled. */
 711
 712         res = target_read_u32(target, NRF5_FICR_INFO_VARIANT, &chip->ficr_info.variant);
 713         if (res != ERROR_OK)
 714                 return res;
 715
 716         res = target_read_u32(target, NRF5_FICR_INFO_PACKAGE, &chip->ficr_info.package);
 717         if (res != ERROR_OK)
 718                 return res;
 719
 720         res = target_read_u32(target, NRF5_FICR_INFO_RAM, &chip->ficr_info.ram);
 721         if (res != ERROR_OK)
 722                 return res;
 723
 724         res = target_read_u32(target, NRF5_FICR_INFO_FLASH, &chip->ficr_info.flash);
 725         if (res != ERROR_OK)
 726                 return res;
 727
 728         chip->ficr_info_valid = true;
 729         return ERROR_OK;
 730 }
 731
 732 static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size)
 733 {
 734         int res;
 735
 736         *ram_size = 0;
 737
 738         uint32_t numramblock;
 739         res = target_read_u32(target, NRF51_FICR_NUMRAMBLOCK, &numramblock);
 740         if (res != ERROR_OK) {
 741                 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
 742                 return res;
 743         }
 744
 745         if (numramblock < 1 || numramblock > 4) {
 746                 LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32, numramblock);
 747                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 748         }
 749
 750         for (unsigned int i = 0; i < numramblock; i++) {
 751                 uint32_t sizeramblock;
 752                 res = target_read_u32(target, NRF51_FICR_SIZERAMBLOCK0 + sizeof(uint32_t)*i, &sizeramblock);
 753                 if (res != ERROR_OK) {
 754                         LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
 755                         return res;
 756                 }
 757                 if (sizeramblock < 1024 || sizeramblock > 65536)
 758                         LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32, sizeramblock);
 759                 else
 760                         *ram_size += sizeramblock;
 761         }
 762         return res;
 763 }
 764
 765 static int nrf5_probe(struct flash_bank *bank)
 766 {
 767         int res;
 768         struct nrf5_bank *nbank = bank->driver_priv;
 769         struct nrf5_info *chip = nbank->chip;
 770         struct target *target = chip->target;
 771
 772         uint32_t configid;
 773         res = target_read_u32(target, NRF5_FICR_CONFIGID, &configid);
 774         if (res != ERROR_OK) {
 775                 LOG_ERROR("Couldn't read CONFIGID register");
 776                 return res;
 777         }
 778
 779         /* HWID is stored in the lower two bytes of the CONFIGID register */
 780         chip->hwid = configid & 0xFFFF;
 781
 782         /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
 783         chip->features = NRF5_FEATURE_SERIES_51;
 784
 785         /* Don't bail out on error for the case that some old engineering
 786          * sample has FICR INFO registers unreadable. We can proceed anyway. */
 787         (void)nrf5_read_ficr_info(chip);
 788
 789         chip->spec = NULL;
 790         for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
 791                 if (chip->hwid == nrf5_known_devices_table[i].hwid) {
 792                         chip->spec = &nrf5_known_devices_table[i];
 793                         chip->features = chip->spec->features;
 794                         break;
 795                 }
 796         }
 797
 798         if (chip->spec && chip->ficr_info_valid) {
 799                 /* check if HWID table gives the same part as FICR INFO */
 800                 if (chip->ficr_info.part != strtoul(chip->spec->part, NULL, 16))
 801                         LOG_WARNING("HWID 0x%04" PRIx32 " mismatch: FICR INFO.PART %"
 802                                                 PRIx32, chip->hwid, chip->ficr_info.part);
 803         }
 804
 805         if (chip->ficr_info_valid) {
 806                 chip->ram_size_kb = chip->ficr_info.ram;
 807         } else {
 808                 uint32_t ram_size;
 809                 nrf5_get_ram_size(target, &ram_size);
 810                 chip->ram_size_kb = ram_size / 1024;
 811         }
 812
 813         /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
 814         uint32_t flash_page_size;
 815         res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
 816                                 &flash_page_size);
 817         if (res != ERROR_OK) {
 818                 LOG_ERROR("Couldn't read code page size");
 819                 return res;
 820         }
 821
 822         /* Note the register name is misleading,
 823          * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
 824         uint32_t num_sectors;
 825         res = target_read_u32(chip->target, NRF5_FICR_CODESIZE, &num_sectors);
 826         if (res != ERROR_OK) {
 827                 LOG_ERROR("Couldn't read code memory size");
 828                 return res;
 829         }
 830
 831         chip->flash_size_kb = num_sectors * flash_page_size / 1024;
 832
 833         if (!chip->bank[0].probed && !chip->bank[1].probed) {
 834                 char chip_type_str[256];
 835                 if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
 836                         return ERROR_FAIL;
 837                 const bool device_is_unknown = (!chip->spec && !chip->ficr_info_valid);
 838                 LOG_INFO("%s%s %ukB Flash, %ukB RAM",
 839                                 device_is_unknown ? "Unknown device: " : "",
 840                                 chip_type_str,
 841                                 chip->flash_size_kb,
 842                                 chip->ram_size_kb);
 843         }
 844
 845         free(bank->sectors);
 846
 847         if (bank->base == NRF5_FLASH_BASE) {
 848                 /* Sanity check */
 849                 if (chip->spec && chip->flash_size_kb != chip->spec->flash_size_kb)
 850                         LOG_WARNING("Chip's reported Flash capacity does not match expected one");
 851                 if (chip->ficr_info_valid && chip->flash_size_kb != chip->ficr_info.flash)
 852                         LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH");
 853
 854                 bank->num_sectors = num_sectors;
 855                 bank->size = num_sectors * flash_page_size;
 856
 857                 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
 858                 if (!bank->sectors)
 859                         return ERROR_FAIL;
 860
 861                 chip->bank[0].probed = true;
 862
 863         } else {
 864                 bank->num_sectors = 1;
 865                 bank->size = flash_page_size;
 866
 867                 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
 868                 if (!bank->sectors)
 869                         return ERROR_FAIL;
 870
 871                 bank->sectors[0].is_protected = 0;
 872
 873                 chip->bank[1].probed = true;
 874         }
 875
 876         return ERROR_OK;
 877 }
 878
 879 static int nrf5_auto_probe(struct flash_bank *bank)
 880 {
 881         if (nrf5_bank_is_probed(bank))
 882                 return ERROR_OK;
 883
 884         return nrf5_probe(bank);
 885 }
 886
 887 static int nrf5_erase_all(struct nrf5_info *chip)
 888 {
 889         LOG_DEBUG("Erasing all non-volatile memory");
 890         return nrf5_nvmc_generic_erase(chip,
 891                                         NRF5_NVMC_ERASEALL,
 892                                         0x00000001);
 893 }
 894
 895 static int nrf5_erase_page(struct flash_bank *bank,
 896                                                         struct nrf5_info *chip,
 897                                                         struct flash_sector *sector)
 898 {
 899         int res;
 900
 901         LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
 902
 903         if (bank->base == NRF5_UICR_BASE) {
 904                 if (chip->features & NRF5_FEATURE_SERIES_51) {
 905                         uint32_t ppfc;
 906                         res = target_read_u32(chip->target, NRF51_FICR_PPFC,
 907                                       &ppfc);
 908                         if (res != ERROR_OK) {
 909                                 LOG_ERROR("Couldn't read PPFC register");
 910                                 return res;
 911                         }
 912
 913                         if ((ppfc & 0xFF) == 0xFF) {
 914                                 /* We can't erase the UICR.  Double-check to
 915                                    see if it's already erased before complaining. */
 916                                 default_flash_blank_check(bank);
 917                                 if (sector->is_erased == 1)
 918                                         return ERROR_OK;
 919
 920                                 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
 921                                 return ERROR_FAIL;
 922                         }
 923                 }
 924
 925                 res = nrf5_nvmc_generic_erase(chip,
 926                                                NRF5_NVMC_ERASEUICR,
 927                                                0x00000001);
 928
 929
 930         } else {
 931                 res = nrf5_nvmc_generic_erase(chip,
 932                                                NRF5_NVMC_ERASEPAGE,
 933                                                sector->offset);
 934         }
 935
 936         return res;
 937 }
 938
 939 /* Start a low level flash write for the specified region */
 940 static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const uint8_t *buffer, uint32_t bytes)
 941 {
 942         struct target *target = chip->target;
 943         uint32_t buffer_size = 8192;
 944         struct working_area *write_algorithm;
 945         struct working_area *source;
 946         struct reg_param reg_params[6];
 947         struct armv7m_algorithm armv7m_info;
 948         int retval = ERROR_OK;
 949
 950         static const uint8_t nrf5_flash_write_code[] = {
 951 #include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
 952         };
 953
 954         LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32" bytes=0x%"PRIx32, address, bytes);
 955         assert(bytes % 4 == 0);
 956
 957         /* allocate working area with flash programming code */
 958         if (target_alloc_working_area(target, sizeof(nrf5_flash_write_code),
 959                         &write_algorithm) != ERROR_OK) {
 960                 LOG_WARNING("no working area available, falling back to slow memory writes");
 961
 962                 for (; bytes > 0; bytes -= 4) {
 963                         retval = target_write_memory(target, address, 4, 1, buffer);
 964                         if (retval != ERROR_OK)
 965                                 return retval;
 966
 967                         retval = nrf5_wait_for_nvmc(chip);
 968                         if (retval != ERROR_OK)
 969                                 return retval;
 970
 971                         address += 4;
 972                         buffer += 4;
 973                 }
 974
 975                 return ERROR_OK;
 976         }
 977
 978         retval = target_write_buffer(target, write_algorithm->address,
 979                                 sizeof(nrf5_flash_write_code),
 980                                 nrf5_flash_write_code);
 981         if (retval != ERROR_OK)
 982                 return retval;
 983
 984         /* memory buffer */
 985         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
 986                 buffer_size /= 2;
 987                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 988                 if (buffer_size <= 256) {
 989                         /* free working area, write algorithm already allocated */
 990                         target_free_working_area(target, write_algorithm);
 991
 992                         LOG_WARNING("No large enough working area available, can't do block memory writes");
 993                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 994                 }
 995         }
 996
 997         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 998         armv7m_info.core_mode = ARM_MODE_THREAD;
 999
1000         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
1001         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* buffer start */
1002         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer end */
1003         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
1004         init_reg_param(&reg_params[4], "r6", 32, PARAM_OUT);    /* watchdog refresh value */
1005         init_reg_param(&reg_params[5], "r7", 32, PARAM_OUT);    /* watchdog refresh register address */
1006
1007         buf_set_u32(reg_params[0].value, 0, 32, bytes);
1008         buf_set_u32(reg_params[1].value, 0, 32, source->address);
1009         buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
1010         buf_set_u32(reg_params[3].value, 0, 32, address);
1011         buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE);
1012         buf_set_u32(reg_params[5].value, 0, 32, WATCHDOG_REFRESH_REGISTER);
1013
1014         retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
1015                         0, NULL,
1016                         ARRAY_SIZE(reg_params), reg_params,
1017                         source->address, source->size,
1018                         write_algorithm->address, write_algorithm->address + sizeof(nrf5_flash_write_code) - 2,
1019                         &armv7m_info);
1020
1021         target_free_working_area(target, source);
1022         target_free_working_area(target, write_algorithm);
1023
1024         destroy_reg_param(&reg_params[0]);
1025         destroy_reg_param(&reg_params[1]);
1026         destroy_reg_param(&reg_params[2]);
1027         destroy_reg_param(&reg_params[3]);
1028         destroy_reg_param(&reg_params[4]);
1029         destroy_reg_param(&reg_params[5]);
1030
1031         return retval;
1032 }
1033
1034 static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
1035                                         uint32_t offset, uint32_t count)
1036 {
1037         struct nrf5_info *chip;
1038
1039         int res = nrf5_get_probed_chip_if_halted(bank, &chip);
1040         if (res != ERROR_OK)
1041                 return res;
1042
1043         assert(offset % 4 == 0);
1044         assert(count % 4 == 0);
1045
1046         /* UICR CLENR0 based protection used on nRF51 is somewhat clumsy:
1047          * RM reads: Code running from code region 1 will not be able to write
1048          * to code region 0.
1049          * Unfortunately the flash loader running from RAM can write to both
1050          * code regions without any hint the protection is violated.
1051          *
1052          * Update protection state and check if any flash sector to be written
1053          * is protected. */
1054         if (chip->features & NRF5_FEATURE_SERIES_51) {
1055
1056                 res = nrf5_protect_check_clenr0(bank);
1057                 if (res != ERROR_OK)
1058                         return res;
1059
1060                 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
1061                         struct flash_sector *bs = &bank->sectors[sector];
1062
1063                         /* Start offset in or before this sector? */
1064                         /* End offset in or behind this sector? */
1065                         if ((offset < (bs->offset + bs->size))
1066                                         && ((offset + count - 1) >= bs->offset)
1067                                         && bs->is_protected == 1) {
1068                                 LOG_ERROR("Write refused, sector %d is protected", sector);
1069                                 return ERROR_FLASH_PROTECTED;
1070                         }
1071                 }
1072         }
1073
1074         res = nrf5_nvmc_write_enable(chip);
1075         if (res != ERROR_OK)
1076                 goto error;
1077
1078         res = nrf5_ll_flash_write(chip, bank->base + offset, buffer, count);
1079         if (res != ERROR_OK)
1080                 goto error;
1081
1082         return nrf5_nvmc_read_only(chip);
1083
1084 error:
1085         nrf5_nvmc_read_only(chip);
1086         LOG_ERROR("Failed to write to nrf5 flash");
1087         return res;
1088 }
1089
1090 static int nrf5_erase(struct flash_bank *bank, unsigned int first,
1091                 unsigned int last)
1092 {
1093         int res;
1094         struct nrf5_info *chip;
1095
1096         res = nrf5_get_probed_chip_if_halted(bank, &chip);
1097         if (res != ERROR_OK)
1098                 return res;
1099
1100         /* UICR CLENR0 based protection used on nRF51 prevents erase
1101          * absolutely silently. NVMC has no flag to indicate the protection
1102          * was violated.
1103          *
1104          * Update protection state and check if any flash sector to be erased
1105          * is protected. */
1106         if (chip->features & NRF5_FEATURE_SERIES_51) {
1107
1108                 res = nrf5_protect_check_clenr0(bank);
1109                 if (res != ERROR_OK)
1110                         return res;
1111         }
1112
1113         /* For each sector to be erased */
1114         for (unsigned int s = first; s <= last && res == ERROR_OK; s++) {
1115
1116                 if (chip->features & NRF5_FEATURE_SERIES_51
1117                                 && bank->sectors[s].is_protected == 1) {
1118                         LOG_ERROR("Flash sector %d is protected", s);
1119                         return ERROR_FLASH_PROTECTED;
1120                 }
1121
1122                 res = nrf5_erase_page(bank, chip, &bank->sectors[s]);
1123                 if (res != ERROR_OK) {
1124                         LOG_ERROR("Error erasing sector %d", s);
1125                         return res;
1126                 }
1127         }
1128
1129         return ERROR_OK;
1130 }
1131
1132 static void nrf5_free_driver_priv(struct flash_bank *bank)
1133 {
1134         struct nrf5_bank *nbank = bank->driver_priv;
1135         struct nrf5_info *chip = nbank->chip;
1136         if (!chip)
1137                 return;
1138
1139         chip->refcount--;
1140         if (chip->refcount == 0) {
1141                 free(chip);
1142                 bank->driver_priv = NULL;
1143         }
1144 }
1145
1146 static struct nrf5_info *nrf5_get_chip(struct target *target)
1147 {
1148         struct flash_bank *bank_iter;
1149
1150         /* iterate over nrf5 banks of same target */
1151         for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
1152                 if (bank_iter->driver != &nrf5_flash && bank_iter->driver != &nrf51_flash)
1153                         continue;
1154
1155                 if (bank_iter->target != target)
1156                         continue;
1157
1158                 struct nrf5_bank *nbank = bank_iter->driver_priv;
1159                 if (!nbank)
1160                         continue;
1161
1162                 if (nbank->chip)
1163                         return nbank->chip;
1164         }
1165         return NULL;
1166 }
1167
1168 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
1169 {
1170         struct nrf5_info *chip;
1171         struct nrf5_bank *nbank = NULL;
1172
1173         switch (bank->base) {
1174         case NRF5_FLASH_BASE:
1175         case NRF5_UICR_BASE:
1176                 break;
1177         default:
1178                 LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
1179                 return ERROR_FAIL;
1180         }
1181
1182         chip = nrf5_get_chip(bank->target);
1183         if (!chip) {
1184                 /* Create a new chip */
1185                 chip = calloc(1, sizeof(*chip));
1186                 if (!chip)
1187                         return ERROR_FAIL;
1188
1189                 chip->target = bank->target;
1190         }
1191
1192         switch (bank->base) {
1193         case NRF5_FLASH_BASE:
1194                 nbank = &chip->bank[0];
1195                 break;
1196         case NRF5_UICR_BASE:
1197                 nbank = &chip->bank[1];
1198                 break;
1199         }
1200         assert(nbank);
1201
1202         chip->refcount++;
1203         nbank->chip = chip;
1204         nbank->probed = false;
1205         bank->driver_priv = nbank;
1206         bank->write_start_alignment = bank->write_end_alignment = 4;
1207
1208         return ERROR_OK;
1209 }
1210
1211 COMMAND_HANDLER(nrf5_handle_mass_erase_command)
1212 {
1213         int res;
1214         struct flash_bank *bank = NULL;
1215         struct target *target = get_current_target(CMD_CTX);
1216
1217         res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1218         if (res != ERROR_OK)
1219                 return res;
1220
1221         assert(bank);
1222
1223         struct nrf5_info *chip;
1224
1225         res = nrf5_get_probed_chip_if_halted(bank, &chip);
1226         if (res != ERROR_OK)
1227                 return res;
1228
1229         if (chip->features & NRF5_FEATURE_SERIES_51) {
1230                 uint32_t ppfc;
1231                 res = target_read_u32(target, NRF51_FICR_PPFC,
1232                               &ppfc);
1233                 if (res != ERROR_OK) {
1234                         LOG_ERROR("Couldn't read PPFC register");
1235                         return res;
1236                 }
1237
1238                 if ((ppfc & 0xFF) == 0x00) {
1239                         LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1240                                   "mass erase command won't work.");
1241                         return ERROR_FAIL;
1242                 }
1243         }
1244
1245         res = nrf5_erase_all(chip);
1246         if (res == ERROR_OK) {
1247                 LOG_INFO("Mass erase completed.");
1248                 if (chip->features & NRF5_FEATURE_SERIES_51)
1249                         LOG_INFO("A reset or power cycle is required if the flash was protected before.");
1250
1251         } else {
1252                 LOG_ERROR("Failed to erase the chip");
1253         }
1254
1255         return res;
1256 }
1257
1258 COMMAND_HANDLER(nrf5_handle_info_command)
1259 {
1260         int res;
1261         struct flash_bank *bank = NULL;
1262         struct target *target = get_current_target(CMD_CTX);
1263
1264         res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1265         if (res != ERROR_OK)
1266                 return res;
1267
1268         assert(bank);
1269
1270         struct nrf5_info *chip;
1271
1272         res = nrf5_get_probed_chip_if_halted(bank, &chip);
1273         if (res != ERROR_OK)
1274                 return res;
1275
1276         static struct {
1277                 const uint32_t address;
1278                 uint32_t value;
1279         } ficr[] = {
1280                 { .address = NRF5_FICR_CODEPAGESIZE     },
1281                 { .address = NRF5_FICR_CODESIZE },
1282                 { .address = NRF51_FICR_CLENR0          },
1283                 { .address = NRF51_FICR_PPFC            },
1284                 { .address = NRF51_FICR_NUMRAMBLOCK     },
1285                 { .address = NRF51_FICR_SIZERAMBLOCK0   },
1286                 { .address = NRF51_FICR_SIZERAMBLOCK1   },
1287                 { .address = NRF51_FICR_SIZERAMBLOCK2   },
1288                 { .address = NRF51_FICR_SIZERAMBLOCK3   },
1289                 { .address = NRF5_FICR_CONFIGID },
1290                 { .address = NRF5_FICR_DEVICEID0        },
1291                 { .address = NRF5_FICR_DEVICEID1        },
1292                 { .address = NRF5_FICR_ER0              },
1293                 { .address = NRF5_FICR_ER1              },
1294                 { .address = NRF5_FICR_ER2              },
1295                 { .address = NRF5_FICR_ER3              },
1296                 { .address = NRF5_FICR_IR0              },
1297                 { .address = NRF5_FICR_IR1              },
1298                 { .address = NRF5_FICR_IR2              },
1299                 { .address = NRF5_FICR_IR3              },
1300                 { .address = NRF5_FICR_DEVICEADDRTYPE   },
1301                 { .address = NRF5_FICR_DEVICEADDR0      },
1302                 { .address = NRF5_FICR_DEVICEADDR1      },
1303                 { .address = NRF51_FICR_OVERRIDEN       },
1304                 { .address = NRF51_FICR_NRF_1MBIT0      },
1305                 { .address = NRF51_FICR_NRF_1MBIT1      },
1306                 { .address = NRF51_FICR_NRF_1MBIT2      },
1307                 { .address = NRF51_FICR_NRF_1MBIT3      },
1308                 { .address = NRF51_FICR_NRF_1MBIT4      },
1309                 { .address = NRF51_FICR_BLE_1MBIT0      },
1310                 { .address = NRF51_FICR_BLE_1MBIT1      },
1311                 { .address = NRF51_FICR_BLE_1MBIT2      },
1312                 { .address = NRF51_FICR_BLE_1MBIT3      },
1313                 { .address = NRF51_FICR_BLE_1MBIT4      },
1314         }, uicr[] = {
1315                 { .address = NRF51_UICR_CLENR0,         },
1316                 { .address = NRF51_UICR_RBPCONF         },
1317                 { .address = NRF51_UICR_XTALFREQ        },
1318                 { .address = NRF51_UICR_FWID            },
1319         };
1320
1321         for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1322                 res = target_read_u32(chip->target, ficr[i].address,
1323                                       &ficr[i].value);
1324                 if (res != ERROR_OK) {
1325                         LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1326                         return res;
1327                 }
1328         }
1329
1330         for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1331                 res = target_read_u32(chip->target, uicr[i].address,
1332                                       &uicr[i].value);
1333                 if (res != ERROR_OK) {
1334                         LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1335                         return res;
1336                 }
1337         }
1338
1339         command_print(CMD,
1340                  "\n[factory information control block]\n\n"
1341                  "code page size: %"PRIu32"B\n"
1342                  "code memory size: %"PRIu32"kB\n"
1343                  "code region 0 size: %"PRIu32"kB\n"
1344                  "pre-programmed code: %s\n"
1345                  "number of ram blocks: %"PRIu32"\n"
1346                  "ram block 0 size: %"PRIu32"B\n"
1347                  "ram block 1 size: %"PRIu32"B\n"
1348                  "ram block 2 size: %"PRIu32"B\n"
1349                  "ram block 3 size: %"PRIu32 "B\n"
1350                  "config id: %" PRIx32 "\n"
1351                  "device id: 0x%"PRIx32"%08"PRIx32"\n"
1352                  "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1353                  "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1354                  "device address type: 0x%"PRIx32"\n"
1355                  "device address: 0x%"PRIx32"%08"PRIx32"\n"
1356                  "override enable: %"PRIx32"\n"
1357                  "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1358                  "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1359                  "\n[user information control block]\n\n"
1360                  "code region 0 size: %"PRIu32"kB\n"
1361                  "read back protection configuration: %"PRIx32"\n"
1362                  "reset value for XTALFREQ: %"PRIx32"\n"
1363                  "firmware id: 0x%04"PRIx32,
1364                  ficr[0].value,
1365                  (ficr[1].value * ficr[0].value) / 1024,
1366                  (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1367                  ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1368                  ficr[4].value,
1369                  ficr[5].value,
1370                  (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1371                  (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1372                  (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1373                  ficr[9].value,
1374                  ficr[10].value, ficr[11].value,
1375                  ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1376                  ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1377                  ficr[20].value,
1378                  ficr[21].value, ficr[22].value,
1379                  ficr[23].value,
1380                  ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1381                  ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1382                  (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1383                  uicr[1].value & 0xFFFF,
1384                  uicr[2].value & 0xFF,
1385                  uicr[3].value & 0xFFFF);
1386
1387         return ERROR_OK;
1388 }
1389
1390 static const struct command_registration nrf5_exec_command_handlers[] = {
1391         {
1392                 .name           = "mass_erase",
1393                 .handler        = nrf5_handle_mass_erase_command,
1394                 .mode           = COMMAND_EXEC,
1395                 .help           = "Erase all flash contents of the chip.",
1396                 .usage          = "",
1397         },
1398         {
1399                 .name           = "info",
1400                 .handler        = nrf5_handle_info_command,
1401                 .mode           = COMMAND_EXEC,
1402                 .help           = "Show FICR and UICR info.",
1403                 .usage          = "",
1404         },
1405         COMMAND_REGISTRATION_DONE
1406 };
1407
1408 static const struct command_registration nrf5_command_handlers[] = {
1409         {
1410                 .name   = "nrf5",
1411                 .mode   = COMMAND_ANY,
1412                 .help   = "nrf5 flash command group",
1413                 .usage  = "",
1414                 .chain  = nrf5_exec_command_handlers,
1415         },
1416         {
1417                 .name   = "nrf51",
1418                 .mode   = COMMAND_ANY,
1419                 .help   = "nrf51 flash command group",
1420                 .usage  = "",
1421                 .chain  = nrf5_exec_command_handlers,
1422         },
1423         COMMAND_REGISTRATION_DONE
1424 };
1425
1426 const struct flash_driver nrf5_flash = {
1427         .name                   = "nrf5",
1428         .commands               = nrf5_command_handlers,
1429         .flash_bank_command     = nrf5_flash_bank_command,
1430         .info                   = nrf5_info,
1431         .erase                  = nrf5_erase,
1432         .protect                = nrf5_protect,
1433         .write                  = nrf5_write,
1434         .read                   = default_flash_read,
1435         .probe                  = nrf5_probe,
1436         .auto_probe             = nrf5_auto_probe,
1437         .erase_check            = default_flash_blank_check,
1438         .protect_check          = nrf5_protect_check,
1439         .free_driver_priv       = nrf5_free_driver_priv,
1440 };
1441
1442 /* We need to retain the flash-driver name as well as the commands
1443  * for backwards compatibility */
1444 const struct flash_driver nrf51_flash = {
1445         .name                   = "nrf51",
1446         .commands               = nrf5_command_handlers,
1447         .flash_bank_command     = nrf5_flash_bank_command,
1448         .info                   = nrf5_info,
1449         .erase                  = nrf5_erase,
1450         .protect                = nrf5_protect,
1451         .write                  = nrf5_write,
1452         .read                   = default_flash_read,
1453         .probe                  = nrf5_probe,
1454         .auto_probe             = nrf5_auto_probe,
1455         .erase_check            = default_flash_blank_check,
1456         .protect_check          = nrf5_protect_check,
1457         .free_driver_priv       = nrf5_free_driver_priv,
1458 };