1 /***************************************************************************
2 * Copyright (C) 2014 by Mahavir Jain <mjain@marvell.com> *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
19 * This is QSPI flash controller driver for Marvell's Wireless
20 * Microcontroller platform.
22 * For more information please refer,
23 * https://origin-www.marvell.com/microcontrollers/wi-fi-microcontroller-platform/
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
36 #define QSPI_R_EN (0x0)
37 #define QSPI_W_EN (0x1)
38 #define QSPI_SS_DISABLE (0x0)
39 #define QSPI_SS_ENABLE (0x1)
40 #define WRITE_DISABLE (0x0)
41 #define WRITE_ENABLE (0x1)
43 #define QSPI_TIMEOUT (1000)
44 #define FIFO_FLUSH_TIMEOUT (1000)
45 #define BLOCK_ERASE_TIMEOUT (1000)
46 #define CHIP_ERASE_TIMEOUT (10000)
48 #define SS_EN (1 << 0)
49 #define XFER_RDY (1 << 1)
50 #define RFIFO_EMPTY (1 << 4)
51 #define WFIFO_EMPTY (1 << 6)
52 #define WFIFO_FULL (1 << 7)
53 #define FIFO_FLUSH (1 << 9)
54 #define RW_EN (1 << 13)
55 #define XFER_STOP (1 << 14)
56 #define XFER_START (1 << 15)
57 #define CONF_MASK (0x7)
58 #define CONF_OFFSET (10)
60 #define INS_WRITE_ENABLE 0x06
61 #define INS_WRITE_DISABLE 0x04
62 #define INS_READ_STATUS 0x05
63 #define INS_PAGE_PROGRAM 0x02
65 #define CNTL 0x0 /* QSPI_BASE + 0x0 */
75 struct mrvlqspi_flash_bank {
79 const struct flash_device *dev;
82 static inline uint32_t mrvlqspi_get_reg(struct flash_bank *bank, uint32_t reg)
84 struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
85 return reg + mrvlqspi_info->reg_base;
88 static inline int mrvlqspi_set_din_cnt(struct flash_bank *bank, uint32_t count)
90 struct target *target = bank->target;
92 return target_write_u32(target, mrvlqspi_get_reg(bank, DINCNT), count);
95 static inline int mrvlqspi_set_addr(struct flash_bank *bank, uint32_t addr)
97 struct target *target = bank->target;
99 return target_write_u32(target, mrvlqspi_get_reg(bank, ADDR), addr);
102 static inline int mrvlqspi_set_instr(struct flash_bank *bank, uint32_t instr)
104 struct target *target = bank->target;
106 return target_write_u32(target, mrvlqspi_get_reg(bank, INSTR), instr);
109 static inline int mrvlqspi_set_hdr_cnt(struct flash_bank *bank, uint32_t hdr_cnt)
111 struct target *target = bank->target;
113 return target_write_u32(target, mrvlqspi_get_reg(bank, HDRCNT), hdr_cnt);
116 static int mrvlqspi_set_conf(struct flash_bank *bank, uint32_t conf_val)
120 struct target *target = bank->target;
122 retval = target_read_u32(target,
123 mrvlqspi_get_reg(bank, CONF), ®val);
124 if (retval != ERROR_OK)
127 regval &= ~(CONF_MASK << CONF_OFFSET);
128 regval |= (conf_val << CONF_OFFSET);
130 return target_write_u32(target,
131 mrvlqspi_get_reg(bank, CONF), regval);
134 static int mrvlqspi_set_ss_state(struct flash_bank *bank, bool state, int timeout)
138 struct target *target = bank->target;
140 retval = target_read_u32(target,
141 mrvlqspi_get_reg(bank, CNTL), ®val);
142 if (retval != ERROR_OK)
150 retval = target_write_u32(target,
151 mrvlqspi_get_reg(bank, CNTL), regval);
152 if (retval != ERROR_OK)
155 /* wait for xfer_ready to set */
157 retval = target_read_u32(target,
158 mrvlqspi_get_reg(bank, CNTL), ®val);
159 if (retval != ERROR_OK)
161 LOG_DEBUG("status: 0x%08" PRIx32, regval);
162 if ((regval & XFER_RDY) == XFER_RDY)
164 if (timeout-- <= 0) {
165 LOG_ERROR("timed out waiting for flash");
173 static int mrvlqspi_start_transfer(struct flash_bank *bank, bool rw_mode)
177 struct target *target = bank->target;
179 retval = mrvlqspi_set_ss_state(bank, QSPI_SS_ENABLE, QSPI_TIMEOUT);
180 if (retval != ERROR_OK)
183 retval = target_read_u32(target,
184 mrvlqspi_get_reg(bank, CONF), ®val);
185 if (retval != ERROR_OK)
193 regval |= XFER_START;
195 retval = target_write_u32(target,
196 mrvlqspi_get_reg(bank, CONF), regval);
197 if (retval != ERROR_OK)
203 static int mrvlqspi_stop_transfer(struct flash_bank *bank)
207 struct target *target = bank->target;
208 int timeout = QSPI_TIMEOUT;
210 /* wait for xfer_ready and wfifo_empty to set */
212 retval = target_read_u32(target,
213 mrvlqspi_get_reg(bank, CNTL), ®val);
214 if (retval != ERROR_OK)
216 LOG_DEBUG("status: 0x%08" PRIx32, regval);
217 if ((regval & (XFER_RDY | WFIFO_EMPTY)) ==
218 (XFER_RDY | WFIFO_EMPTY))
220 if (timeout-- <= 0) {
221 LOG_ERROR("timed out waiting for flash");
227 retval = target_read_u32(target,
228 mrvlqspi_get_reg(bank, CONF), ®val);
229 if (retval != ERROR_OK)
234 retval = target_write_u32(target,
235 mrvlqspi_get_reg(bank, CONF), regval);
236 if (retval != ERROR_OK)
239 /* wait for xfer_start to reset */
241 retval = target_read_u32(target,
242 mrvlqspi_get_reg(bank, CONF), ®val);
243 if (retval != ERROR_OK)
245 LOG_DEBUG("status: 0x%08" PRIx32, regval);
246 if ((regval & XFER_START) == 0)
248 if (timeout-- <= 0) {
249 LOG_ERROR("timed out waiting for flash");
255 retval = mrvlqspi_set_ss_state(bank, QSPI_SS_DISABLE, QSPI_TIMEOUT);
256 if (retval != ERROR_OK)
262 static int mrvlqspi_fifo_flush(struct flash_bank *bank, int timeout)
266 struct target *target = bank->target;
268 retval = target_read_u32(target,
269 mrvlqspi_get_reg(bank, CONF), &val);
270 if (retval != ERROR_OK)
275 retval = target_write_u32(target,
276 mrvlqspi_get_reg(bank, CONF), val);
277 if (retval != ERROR_OK)
280 /* wait for fifo_flush to clear */
282 retval = target_read_u32(target,
283 mrvlqspi_get_reg(bank, CONF), &val);
284 if (retval != ERROR_OK)
286 LOG_DEBUG("status: 0x%08" PRIX32, val);
287 if ((val & FIFO_FLUSH) == 0)
289 if (timeout-- <= 0) {
290 LOG_ERROR("timed out waiting for flash");
298 static int mrvlqspi_read_byte(struct flash_bank *bank, uint8_t *data)
302 struct target *target = bank->target;
304 /* wait for rfifo_empty to reset */
306 retval = target_read_u32(target,
307 mrvlqspi_get_reg(bank, CNTL), &val);
308 if (retval != ERROR_OK)
310 LOG_DEBUG("status: 0x%08" PRIx32, val);
311 if ((val & RFIFO_EMPTY) == 0)
316 retval = target_read_u32(target,
317 mrvlqspi_get_reg(bank, DIN), &val);
318 if (retval != ERROR_OK)
326 static int mrvlqspi_flash_busy_status(struct flash_bank *bank, int timeout)
331 /* Flush read/write fifos */
332 retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
333 if (retval != ERROR_OK)
336 /* Set instruction/addr count value */
337 retval = mrvlqspi_set_hdr_cnt(bank, 0x1);
338 if (retval != ERROR_OK)
341 /* Read flash status register in continuous manner */
342 retval = mrvlqspi_set_din_cnt(bank, 0x0);
343 if (retval != ERROR_OK)
346 /* Set instruction */
347 retval = mrvlqspi_set_instr(bank, INS_READ_STATUS);
348 if (retval != ERROR_OK)
351 /* Set data and addr pin length */
352 retval = mrvlqspi_set_conf(bank, 0x0);
353 if (retval != ERROR_OK)
356 /* Enable read mode transfer */
357 retval = mrvlqspi_start_transfer(bank, QSPI_R_EN);
358 if (retval != ERROR_OK)
362 retval = mrvlqspi_read_byte(bank, &val);
363 if (retval != ERROR_OK)
367 if (timeout-- <= 0) {
368 LOG_ERROR("timed out waiting for flash");
374 return mrvlqspi_stop_transfer(bank);
377 static int mrvlqspi_set_write_status(struct flash_bank *bank, bool mode)
382 /* Flush read/write fifos */
383 retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
384 if (retval != ERROR_OK)
387 /* Set instruction/addr count value */
388 retval = mrvlqspi_set_hdr_cnt(bank, 0x1);
389 if (retval != ERROR_OK)
393 instr = INS_WRITE_ENABLE;
395 instr = INS_WRITE_DISABLE;
397 /* Set instruction */
398 retval = mrvlqspi_set_instr(bank, instr);
399 if (retval != ERROR_OK)
402 retval = mrvlqspi_start_transfer(bank, QSPI_W_EN);
403 if (retval != ERROR_OK)
406 retval = mrvlqspi_stop_transfer(bank);
407 if (retval != ERROR_OK)
413 static int mrvlqspi_read_id(struct flash_bank *bank, uint32_t *id)
415 uint8_t id_buf[3] = {0, 0, 0};
418 LOG_DEBUG("Getting ID");
420 /* Flush read/write fifos */
421 retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
422 if (retval != ERROR_OK)
425 /* Set instruction/addr count value */
426 retval = mrvlqspi_set_hdr_cnt(bank, 0x1);
427 if (retval != ERROR_OK)
430 /* Set count for number of bytes to read */
431 retval = mrvlqspi_set_din_cnt(bank, 0x3);
432 if (retval != ERROR_OK)
435 /* Set instruction */
436 retval = mrvlqspi_set_instr(bank, SPIFLASH_READ_ID);
437 if (retval != ERROR_OK)
440 /* Set data and addr pin length */
441 retval = mrvlqspi_set_conf(bank, 0x0);
442 if (retval != ERROR_OK)
445 retval = mrvlqspi_start_transfer(bank, QSPI_R_EN);
446 if (retval != ERROR_OK)
449 for (i = 0; i < 3; i++) {
450 retval = mrvlqspi_read_byte(bank, &id_buf[i]);
451 if (retval != ERROR_OK)
455 LOG_DEBUG("ID is 0x%02" PRIx8 " 0x%02" PRIx8 " 0x%02" PRIx8,
456 id_buf[0], id_buf[1], id_buf[2]);
457 retval = mrvlqspi_set_ss_state(bank, QSPI_SS_DISABLE, QSPI_TIMEOUT);
458 if (retval != ERROR_OK)
461 *id = id_buf[2] << 16 | id_buf[1] << 8 | id_buf[0];
465 static int mrvlqspi_block_erase(struct flash_bank *bank, uint32_t offset)
468 struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
470 /* Set flash write enable */
471 retval = mrvlqspi_set_write_status(bank, WRITE_ENABLE);
472 if (retval != ERROR_OK)
475 /* Set instruction/addr count value */
476 retval = mrvlqspi_set_hdr_cnt(bank, (0x1 | (0x3 << 4)));
477 if (retval != ERROR_OK)
480 /* Set read offset address */
481 retval = mrvlqspi_set_addr(bank, offset);
482 if (retval != ERROR_OK)
485 /* Set instruction */
486 retval = mrvlqspi_set_instr(bank, mrvlqspi_info->dev->erase_cmd);
487 if (retval != ERROR_OK)
490 retval = mrvlqspi_start_transfer(bank, QSPI_W_EN);
491 if (retval != ERROR_OK)
494 retval = mrvlqspi_stop_transfer(bank);
495 if (retval != ERROR_OK)
498 return mrvlqspi_flash_busy_status(bank, BLOCK_ERASE_TIMEOUT);
501 static int mrvlqspi_bulk_erase(struct flash_bank *bank)
504 struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
506 if (mrvlqspi_info->dev->chip_erase_cmd == 0x00)
507 return ERROR_FLASH_OPER_UNSUPPORTED;
509 /* Set flash write enable */
510 retval = mrvlqspi_set_write_status(bank, WRITE_ENABLE);
511 if (retval != ERROR_OK)
514 /* Set instruction */
515 retval = mrvlqspi_set_instr(bank, mrvlqspi_info->dev->chip_erase_cmd);
516 if (retval != ERROR_OK)
519 retval = mrvlqspi_start_transfer(bank, QSPI_W_EN);
520 if (retval != ERROR_OK)
523 retval = mrvlqspi_stop_transfer(bank);
524 if (retval != ERROR_OK)
527 return mrvlqspi_flash_busy_status(bank, CHIP_ERASE_TIMEOUT);
530 static int mrvlqspi_flash_erase(struct flash_bank *bank, unsigned int first,
533 struct target *target = bank->target;
534 struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
535 int retval = ERROR_OK;
537 LOG_DEBUG("erase from sector %u to sector %u", first, last);
539 if (target->state != TARGET_HALTED) {
540 LOG_ERROR("Target not halted");
541 return ERROR_TARGET_NOT_HALTED;
544 if ((last < first) || (last >= bank->num_sectors)) {
545 LOG_ERROR("Flash sector invalid");
546 return ERROR_FLASH_SECTOR_INVALID;
549 if (!(mrvlqspi_info->probed)) {
550 LOG_ERROR("Flash bank not probed");
551 return ERROR_FLASH_BANK_NOT_PROBED;
554 for (unsigned int sector = first; sector <= last; sector++) {
555 if (bank->sectors[sector].is_protected) {
556 LOG_ERROR("Flash sector %u protected", sector);
561 /* If we're erasing the entire chip and the flash supports
562 * it, use a bulk erase instead of going sector-by-sector. */
563 if (first == 0 && last == (bank->num_sectors - 1)
564 && mrvlqspi_info->dev->chip_erase_cmd !=
565 mrvlqspi_info->dev->erase_cmd) {
566 LOG_DEBUG("Chip supports the bulk erase command."
567 " Will use bulk erase instead of sector-by-sector erase.");
568 retval = mrvlqspi_bulk_erase(bank);
569 if (retval == ERROR_OK) {
572 LOG_WARNING("Bulk flash erase failed."
573 " Falling back to sector-by-sector erase.");
576 if (mrvlqspi_info->dev->erase_cmd == 0x00)
577 return ERROR_FLASH_OPER_UNSUPPORTED;
579 for (unsigned int sector = first; sector <= last; sector++) {
580 retval = mrvlqspi_block_erase(bank,
581 sector * mrvlqspi_info->dev->sectorsize);
582 if (retval != ERROR_OK)
589 static int mrvlqspi_flash_write(struct flash_bank *bank, const uint8_t *buffer,
590 uint32_t offset, uint32_t count)
592 struct target *target = bank->target;
593 struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
594 int retval = ERROR_OK;
595 uint32_t page_size, fifo_size;
596 struct working_area *fifo;
597 struct reg_param reg_params[6];
598 struct armv7m_algorithm armv7m_info;
599 struct working_area *write_algorithm;
601 LOG_DEBUG("offset=0x%08" PRIx32 " count=0x%08" PRIx32,
604 if (target->state != TARGET_HALTED) {
605 LOG_ERROR("Target not halted");
606 return ERROR_TARGET_NOT_HALTED;
609 if (offset + count > mrvlqspi_info->dev->size_in_bytes) {
610 LOG_WARNING("Writes past end of flash. Extra data discarded.");
611 count = mrvlqspi_info->dev->size_in_bytes - offset;
614 /* Check sector protection */
615 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
616 /* Start offset in or before this sector? */
617 /* End offset in or behind this sector? */
619 (bank->sectors[sector].offset + bank->sectors[sector].size))
620 && ((offset + count - 1) >= bank->sectors[sector].offset)
621 && bank->sectors[sector].is_protected) {
622 LOG_ERROR("Flash sector %u protected", sector);
627 /* if no valid page_size, use reasonable default */
628 page_size = mrvlqspi_info->dev->pagesize ?
629 mrvlqspi_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
631 /* See contrib/loaders/flash/mrvlqspi.S for src */
632 static const uint8_t mrvlqspi_flash_write_code[] = {
633 0x4f, 0xf0, 0x00, 0x0a, 0xa2, 0x44, 0x92, 0x45,
634 0x7f, 0xf6, 0xfc, 0xaf, 0x00, 0xf0, 0x6b, 0xf8,
635 0x5f, 0xf0, 0x01, 0x08, 0xc5, 0xf8, 0x1c, 0x80,
636 0x5f, 0xf0, 0x06, 0x08, 0xc5, 0xf8, 0x10, 0x80,
637 0x5f, 0xf0, 0x01, 0x09, 0x00, 0xf0, 0x6b, 0xf8,
638 0x00, 0xf0, 0x7d, 0xf8, 0x5f, 0xf0, 0x31, 0x08,
639 0xc5, 0xf8, 0x1c, 0x80, 0x90, 0x46, 0xc5, 0xf8,
640 0x14, 0x80, 0x5f, 0xf0, 0x02, 0x08, 0xc5, 0xf8,
641 0x10, 0x80, 0x5f, 0xf0, 0x01, 0x09, 0x00, 0xf0,
642 0x5a, 0xf8, 0xd0, 0xf8, 0x00, 0x80, 0xb8, 0xf1,
643 0x00, 0x0f, 0x00, 0xf0, 0x8b, 0x80, 0x47, 0x68,
644 0x47, 0x45, 0x3f, 0xf4, 0xf6, 0xaf, 0x17, 0xf8,
645 0x01, 0x9b, 0x00, 0xf0, 0x30, 0xf8, 0x8f, 0x42,
646 0x28, 0xbf, 0x00, 0xf1, 0x08, 0x07, 0x47, 0x60,
647 0x01, 0x3b, 0x00, 0x2b, 0x00, 0xf0, 0x05, 0x80,
648 0x02, 0xf1, 0x01, 0x02, 0x92, 0x45, 0x7f, 0xf4,
649 0xe4, 0xaf, 0x00, 0xf0, 0x50, 0xf8, 0xa2, 0x44,
650 0x00, 0xf0, 0x2d, 0xf8, 0x5f, 0xf0, 0x01, 0x08,
651 0xc5, 0xf8, 0x1c, 0x80, 0x5f, 0xf0, 0x00, 0x08,
652 0xc5, 0xf8, 0x20, 0x80, 0x5f, 0xf0, 0x05, 0x08,
653 0xc5, 0xf8, 0x10, 0x80, 0x5f, 0xf0, 0x00, 0x09,
654 0x00, 0xf0, 0x29, 0xf8, 0x00, 0xf0, 0x13, 0xf8,
655 0x09, 0xf0, 0x01, 0x09, 0xb9, 0xf1, 0x00, 0x0f,
656 0xf8, 0xd1, 0x00, 0xf0, 0x34, 0xf8, 0x00, 0x2b,
657 0xa4, 0xd1, 0x00, 0xf0, 0x53, 0xb8, 0xd5, 0xf8,
658 0x00, 0x80, 0x5f, 0xea, 0x08, 0x68, 0xfa, 0xd4,
659 0xc5, 0xf8, 0x08, 0x90, 0x70, 0x47, 0xd5, 0xf8,
660 0x00, 0x80, 0x5f, 0xea, 0xc8, 0x68, 0xfa, 0xd4,
661 0xd5, 0xf8, 0x0c, 0x90, 0x70, 0x47, 0xd5, 0xf8,
662 0x04, 0x80, 0x48, 0xf4, 0x00, 0x78, 0xc5, 0xf8,
663 0x04, 0x80, 0xd5, 0xf8, 0x04, 0x80, 0x5f, 0xea,
664 0x88, 0x58, 0xfa, 0xd4, 0x70, 0x47, 0xd5, 0xf8,
665 0x00, 0x80, 0x48, 0xf0, 0x01, 0x08, 0xc5, 0xf8,
666 0x00, 0x80, 0xd5, 0xf8, 0x00, 0x80, 0x5f, 0xea,
667 0x88, 0x78, 0xfa, 0xd5, 0xd5, 0xf8, 0x04, 0x80,
668 0x69, 0xf3, 0x4d, 0x38, 0x48, 0xf4, 0x00, 0x48,
669 0xc5, 0xf8, 0x04, 0x80, 0x70, 0x47, 0xd5, 0xf8,
670 0x00, 0x80, 0x5f, 0xea, 0x88, 0x78, 0xfa, 0xd5,
671 0xd5, 0xf8, 0x00, 0x80, 0x5f, 0xea, 0x48, 0x68,
672 0xfa, 0xd5, 0xd5, 0xf8, 0x04, 0x80, 0x48, 0xf4,
673 0x80, 0x48, 0xc5, 0xf8, 0x04, 0x80, 0xd5, 0xf8,
674 0x04, 0x80, 0x5f, 0xea, 0x08, 0x48, 0xfa, 0xd4,
675 0xd5, 0xf8, 0x00, 0x80, 0x28, 0xf0, 0x01, 0x08,
676 0xc5, 0xf8, 0x00, 0x80, 0xd5, 0xf8, 0x00, 0x80,
677 0x5f, 0xea, 0x88, 0x78, 0xfa, 0xd5, 0x70, 0x47,
678 0x00, 0x20, 0x50, 0x60, 0x30, 0x46, 0x00, 0xbe
681 if (target_alloc_working_area(target, sizeof(mrvlqspi_flash_write_code),
682 &write_algorithm) != ERROR_OK) {
683 LOG_ERROR("Insufficient working area. You must configure"
684 " a working area > %zdB in order to write to SPIFI flash.",
685 sizeof(mrvlqspi_flash_write_code));
686 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
689 retval = target_write_buffer(target, write_algorithm->address,
690 sizeof(mrvlqspi_flash_write_code),
691 mrvlqspi_flash_write_code);
692 if (retval != ERROR_OK) {
693 target_free_working_area(target, write_algorithm);
697 /* FIFO allocation */
698 fifo_size = target_get_working_area_avail(target);
700 if (fifo_size == 0) {
701 /* if we already allocated the writing code but failed to get fifo
702 * space, free the algorithm */
703 target_free_working_area(target, write_algorithm);
705 LOG_ERROR("Insufficient working area. Please allocate at least"
706 " %zdB of working area to enable flash writes.",
707 sizeof(mrvlqspi_flash_write_code) + 1
710 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
711 } else if (fifo_size < page_size)
712 LOG_WARNING("Working area size is limited; flash writes may be"
713 " slow. Increase working area size to at least %zdB"
714 " to reduce write times.",
715 (size_t)(sizeof(mrvlqspi_flash_write_code) + page_size)
718 if (target_alloc_working_area(target, fifo_size, &fifo) != ERROR_OK) {
719 target_free_working_area(target, write_algorithm);
720 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
723 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
724 armv7m_info.core_mode = ARM_MODE_THREAD;
726 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
727 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
728 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
729 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (halfword-16bit) */
730 init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* page size */
731 init_reg_param(®_params[5], "r5", 32, PARAM_OUT); /* qspi base address */
733 buf_set_u32(reg_params[0].value, 0, 32, fifo->address);
734 buf_set_u32(reg_params[1].value, 0, 32, fifo->address + fifo->size);
735 buf_set_u32(reg_params[2].value, 0, 32, offset);
736 buf_set_u32(reg_params[3].value, 0, 32, count);
737 buf_set_u32(reg_params[4].value, 0, 32, page_size);
738 buf_set_u32(reg_params[5].value, 0, 32, (uint32_t) mrvlqspi_info->reg_base);
740 retval = target_run_flash_async_algorithm(target, buffer, count, 1,
743 fifo->address, fifo->size,
744 write_algorithm->address, 0,
748 if (retval != ERROR_OK)
749 LOG_ERROR("Error executing flash write algorithm");
751 target_free_working_area(target, fifo);
752 target_free_working_area(target, write_algorithm);
754 destroy_reg_param(®_params[0]);
755 destroy_reg_param(®_params[1]);
756 destroy_reg_param(®_params[2]);
757 destroy_reg_param(®_params[3]);
758 destroy_reg_param(®_params[4]);
759 destroy_reg_param(®_params[5]);
764 static int mrvlqspi_flash_read(struct flash_bank *bank, uint8_t *buffer,
765 uint32_t offset, uint32_t count)
767 struct target *target = bank->target;
768 struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
772 if (target->state != TARGET_HALTED) {
773 LOG_ERROR("Target not halted");
774 return ERROR_TARGET_NOT_HALTED;
777 if (!(mrvlqspi_info->probed)) {
778 LOG_ERROR("Flash bank not probed");
779 return ERROR_FLASH_BANK_NOT_PROBED;
782 /* Flush read/write fifos */
783 retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
784 if (retval != ERROR_OK)
787 /* Set instruction/addr count value */
788 retval = mrvlqspi_set_hdr_cnt(bank, (0x1 | (0x3 << 4)));
789 if (retval != ERROR_OK)
792 /* Set count for number of bytes to read */
793 retval = mrvlqspi_set_din_cnt(bank, count);
794 if (retval != ERROR_OK)
797 /* Set read address */
798 retval = mrvlqspi_set_addr(bank, offset);
799 if (retval != ERROR_OK)
802 /* Set instruction */
803 retval = mrvlqspi_set_instr(bank, SPIFLASH_READ);
804 if (retval != ERROR_OK)
807 /* Set data and addr pin length */
808 retval = mrvlqspi_set_conf(bank, 0x0);
809 if (retval != ERROR_OK)
812 retval = mrvlqspi_start_transfer(bank, QSPI_R_EN);
813 if (retval != ERROR_OK)
816 for (i = 0; i < count; i++) {
817 retval = mrvlqspi_read_byte(bank, &buffer[i]);
818 if (retval != ERROR_OK)
822 retval = mrvlqspi_set_ss_state(bank, QSPI_SS_DISABLE, QSPI_TIMEOUT);
823 if (retval != ERROR_OK)
829 static int mrvlqspi_probe(struct flash_bank *bank)
831 struct target *target = bank->target;
832 struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
835 struct flash_sector *sectors;
838 /* If we've already probed, we should be fine to skip this time. */
839 if (mrvlqspi_info->probed)
842 if (target->state != TARGET_HALTED) {
843 LOG_ERROR("Target not halted");
844 return ERROR_TARGET_NOT_HALTED;
847 mrvlqspi_info->probed = false;
848 mrvlqspi_info->bank_num = bank->bank_number;
850 /* Read flash JEDEC ID */
851 retval = mrvlqspi_read_id(bank, &id);
852 if (retval != ERROR_OK)
855 mrvlqspi_info->dev = NULL;
856 for (const struct flash_device *p = flash_devices; p->name ; p++)
857 if (p->device_id == id) {
858 mrvlqspi_info->dev = p;
862 if (!mrvlqspi_info->dev) {
863 LOG_ERROR("Unknown flash device ID 0x%08" PRIx32, id);
867 LOG_INFO("Found flash device \'%s\' ID 0x%08" PRIx32,
868 mrvlqspi_info->dev->name, mrvlqspi_info->dev->device_id);
871 /* Set correct size value */
872 bank->size = mrvlqspi_info->dev->size_in_bytes;
873 if (bank->size <= (1UL << 16))
874 LOG_WARNING("device needs 2-byte addresses - not implemented");
875 if (bank->size > (1UL << 24))
876 LOG_WARNING("device needs paging or 4-byte addresses - not implemented");
878 /* if no sectors, treat whole bank as single sector */
879 sectorsize = mrvlqspi_info->dev->sectorsize ?
880 mrvlqspi_info->dev->sectorsize : mrvlqspi_info->dev->size_in_bytes;
882 /* create and fill sectors array */
883 bank->num_sectors = mrvlqspi_info->dev->size_in_bytes / sectorsize;
884 sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
885 if (sectors == NULL) {
886 LOG_ERROR("not enough memory");
890 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
891 sectors[sector].offset = sector * sectorsize;
892 sectors[sector].size = sectorsize;
893 sectors[sector].is_erased = -1;
894 sectors[sector].is_protected = 0;
897 bank->sectors = sectors;
898 mrvlqspi_info->probed = true;
903 static int mrvlqspi_auto_probe(struct flash_bank *bank)
905 struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
906 if (mrvlqspi_info->probed)
908 return mrvlqspi_probe(bank);
911 static int mrvlqspi_flash_erase_check(struct flash_bank *bank)
913 /* Not implemented yet */
917 static int mrvlqspi_get_info(struct flash_bank *bank, char *buf, int buf_size)
919 struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
921 if (!(mrvlqspi_info->probed)) {
922 snprintf(buf, buf_size,
923 "\nQSPI flash bank not probed yet\n");
927 snprintf(buf, buf_size, "\nQSPI flash information:\n"
928 " Device \'%s\' ID 0x%08" PRIx32 "\n",
929 mrvlqspi_info->dev->name, mrvlqspi_info->dev->device_id);
934 FLASH_BANK_COMMAND_HANDLER(mrvlqspi_flash_bank_command)
936 struct mrvlqspi_flash_bank *mrvlqspi_info;
939 return ERROR_COMMAND_SYNTAX_ERROR;
941 mrvlqspi_info = malloc(sizeof(struct mrvlqspi_flash_bank));
942 if (mrvlqspi_info == NULL) {
943 LOG_ERROR("not enough memory");
947 /* Get QSPI controller register map base address */
948 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], mrvlqspi_info->reg_base);
949 bank->driver_priv = mrvlqspi_info;
950 mrvlqspi_info->probed = false;
955 const struct flash_driver mrvlqspi_flash = {
957 .flash_bank_command = mrvlqspi_flash_bank_command,
958 .erase = mrvlqspi_flash_erase,
959 .write = mrvlqspi_flash_write,
960 .read = mrvlqspi_flash_read,
961 .probe = mrvlqspi_probe,
962 .auto_probe = mrvlqspi_auto_probe,
963 .erase_check = mrvlqspi_flash_erase_check,
964 .info = mrvlqspi_get_info,
965 .free_driver_priv = default_flash_free_driver_priv,