1 /***************************************************************************
2 * Copyright (C) 2011 by Mathias Kuester *
5 * Copyright (C) 2011 sleep(5) ltd *
6 * tomas@sleepfive.com *
8 * Copyright (C) 2012 by Christopher D. Kilgour *
9 * techie at whiterocker.com *
11 * Copyright (C) 2013 Nemui Trinomius *
12 * nemuisan_kawausogasuki@live.jp *
14 * Copyright (C) 2015 Tomas Vanek *
17 * This program is free software; you can redistribute it and/or modify *
18 * it under the terms of the GNU General Public License as published by *
19 * the Free Software Foundation; either version 2 of the License, or *
20 * (at your option) any later version. *
22 * This program is distributed in the hope that it will be useful, *
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
25 * GNU General Public License for more details. *
27 * You should have received a copy of the GNU General Public License *
28 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
29 ***************************************************************************/
35 #include "jtag/interface.h"
37 #include <helper/binarybuffer.h>
38 #include <helper/time_support.h>
39 #include <target/target_type.h>
40 #include <target/algorithm.h>
41 #include <target/armv7m.h>
42 #include <target/cortex_m.h>
45 * Implementation Notes
47 * The persistent memories in the Kinetis chip families K10 through
48 * K70 are all manipulated with the Flash Memory Module. Some
49 * variants call this module the FTFE, others call it the FTFL. To
50 * indicate that both are considered here, we use FTFX.
52 * Within the module, according to the chip variant, the persistent
53 * memory is divided into what Freescale terms Program Flash, FlexNVM,
54 * and FlexRAM. All chip variants have Program Flash. Some chip
55 * variants also have FlexNVM and FlexRAM, which always appear
58 * A given Kinetis chip may have 1, 2 or 4 blocks of flash. Here we map
59 * each block to a separate bank. Each block size varies by chip and
60 * may be determined by the read-only SIM_FCFG1 register. The sector
61 * size within each bank/block varies by chip, and may be 1, 2 or 4k.
62 * The sector size may be different for flash and FlexNVM.
64 * The first half of the flash (1 or 2 blocks) is always Program Flash
65 * and always starts at address 0x00000000. The "PFLSH" flag, bit 23
66 * of the read-only SIM_FCFG2 register, determines whether the second
67 * half of the flash is also Program Flash or FlexNVM+FlexRAM. When
68 * PFLSH is set, the second from the first half. When PFLSH is clear,
69 * the second half of flash is FlexNVM and always starts at address
70 * 0x10000000. FlexRAM, which is also present when PFLSH is clear,
71 * always starts at address 0x14000000.
73 * The Flash Memory Module provides a register set where flash
74 * commands are loaded to perform flash operations like erase and
75 * program. Different commands are available depending on whether
76 * Program Flash or FlexNVM/FlexRAM is being manipulated. Although
77 * the commands used are quite consistent between flash blocks, the
78 * parameters they accept differ according to the flash sector size.
83 #define FCF_ADDRESS 0x00000400
87 #define FCF_FDPROT 0xf
90 #define FLEXRAM 0x14000000
92 #define MSCM_OCMDR0 0x40001400
93 #define FMC_PFB01CR 0x4001f004
94 #define FTFx_FSTAT 0x40020000
95 #define FTFx_FCNFG 0x40020001
96 #define FTFx_FCCOB3 0x40020004
97 #define FTFx_FPROT3 0x40020010
98 #define FTFx_FDPROT 0x40020017
99 #define SIM_BASE 0x40047000
100 #define SIM_BASE_KL28 0x40074000
101 #define SIM_COPC 0x40048100
102 /* SIM_COPC does not exist on devices with changed SIM_BASE */
103 #define WDOG_BASE 0x40052000
104 #define WDOG32_KE1X 0x40052000
105 #define WDOG32_KL28 0x40076000
106 #define SMC_PMCTRL 0x4007E001
107 #define SMC_PMSTAT 0x4007E003
108 #define SMC32_PMCTRL 0x4007E00C
109 #define SMC32_PMSTAT 0x4007E014
110 #define MCM_PLACR 0xF000300C
113 #define SIM_SOPT1_OFFSET 0x0000
114 #define SIM_SDID_OFFSET 0x1024
115 #define SIM_FCFG1_OFFSET 0x104c
116 #define SIM_FCFG2_OFFSET 0x1050
118 #define WDOG_STCTRLH_OFFSET 0
119 #define WDOG32_CS_OFFSET 0
122 #define PM_STAT_RUN 0x01
123 #define PM_STAT_VLPR 0x04
124 #define PM_CTRL_RUNM_RUN 0x00
127 #define FTFx_CMD_BLOCKSTAT 0x00
128 #define FTFx_CMD_SECTSTAT 0x01
129 #define FTFx_CMD_LWORDPROG 0x06
130 #define FTFx_CMD_SECTERASE 0x09
131 #define FTFx_CMD_SECTWRITE 0x0b
132 #define FTFx_CMD_MASSERASE 0x44
133 #define FTFx_CMD_PGMPART 0x80
134 #define FTFx_CMD_SETFLEXRAM 0x81
136 /* The older Kinetis K series uses the following SDID layout :
143 * The newer Kinetis series uses the following SDID layout :
145 * Bit 27-24 : SUBFAMID
146 * Bit 23-20 : SERIESID
147 * Bit 19-16 : SRAMSIZE
149 * Bit 6-4 : Reserved (0)
152 * We assume that if bits 31-16 are 0 then it's an older
156 #define KINETIS_SOPT1_RAMSIZE_MASK 0x0000F000
157 #define KINETIS_SOPT1_RAMSIZE_K24FN1M 0x0000B000
159 #define KINETIS_SDID_K_SERIES_MASK 0x0000FFFF
161 #define KINETIS_SDID_DIEID_MASK 0x00000F80
163 #define KINETIS_SDID_DIEID_K22FN128 0x00000680 /* smaller pflash with FTFA */
164 #define KINETIS_SDID_DIEID_K22FN256 0x00000A80
165 #define KINETIS_SDID_DIEID_K22FN512 0x00000E80
166 #define KINETIS_SDID_DIEID_K24FN256 0x00000700
168 #define KINETIS_SDID_DIEID_K24FN1M 0x00000300 /* Detect Errata 7534 */
170 /* We can't rely solely on the FAMID field to determine the MCU
171 * type since some FAMID values identify multiple MCUs with
172 * different flash sector sizes (K20 and K22 for instance).
173 * Therefore we combine it with the DIEID bits which may possibly
174 * break if Freescale bumps the DIEID for a particular MCU. */
175 #define KINETIS_K_SDID_TYPE_MASK 0x00000FF0
176 #define KINETIS_K_SDID_K10_M50 0x00000000
177 #define KINETIS_K_SDID_K10_M72 0x00000080
178 #define KINETIS_K_SDID_K10_M100 0x00000100
179 #define KINETIS_K_SDID_K10_M120 0x00000180
180 #define KINETIS_K_SDID_K11 0x00000220
181 #define KINETIS_K_SDID_K12 0x00000200
182 #define KINETIS_K_SDID_K20_M50 0x00000010
183 #define KINETIS_K_SDID_K20_M72 0x00000090
184 #define KINETIS_K_SDID_K20_M100 0x00000110
185 #define KINETIS_K_SDID_K20_M120 0x00000190
186 #define KINETIS_K_SDID_K21_M50 0x00000230
187 #define KINETIS_K_SDID_K21_M120 0x00000330
188 #define KINETIS_K_SDID_K22_M50 0x00000210
189 #define KINETIS_K_SDID_K22_M120 0x00000310
190 #define KINETIS_K_SDID_K30_M72 0x000000A0
191 #define KINETIS_K_SDID_K30_M100 0x00000120
192 #define KINETIS_K_SDID_K40_M72 0x000000B0
193 #define KINETIS_K_SDID_K40_M100 0x00000130
194 #define KINETIS_K_SDID_K50_M72 0x000000E0
195 #define KINETIS_K_SDID_K51_M72 0x000000F0
196 #define KINETIS_K_SDID_K53 0x00000170
197 #define KINETIS_K_SDID_K60_M100 0x00000140
198 #define KINETIS_K_SDID_K60_M150 0x000001C0
199 #define KINETIS_K_SDID_K70_M150 0x000001D0
201 #define KINETIS_SDID_SERIESID_MASK 0x00F00000
202 #define KINETIS_SDID_SERIESID_K 0x00000000
203 #define KINETIS_SDID_SERIESID_KL 0x00100000
204 #define KINETIS_SDID_SERIESID_KE 0x00200000
205 #define KINETIS_SDID_SERIESID_KW 0x00500000
206 #define KINETIS_SDID_SERIESID_KV 0x00600000
208 #define KINETIS_SDID_SUBFAMID_SHIFT 24
209 #define KINETIS_SDID_SUBFAMID_MASK 0x0F000000
210 #define KINETIS_SDID_SUBFAMID_KX0 0x00000000
211 #define KINETIS_SDID_SUBFAMID_KX1 0x01000000
212 #define KINETIS_SDID_SUBFAMID_KX2 0x02000000
213 #define KINETIS_SDID_SUBFAMID_KX3 0x03000000
214 #define KINETIS_SDID_SUBFAMID_KX4 0x04000000
215 #define KINETIS_SDID_SUBFAMID_KX5 0x05000000
216 #define KINETIS_SDID_SUBFAMID_KX6 0x06000000
217 #define KINETIS_SDID_SUBFAMID_KX7 0x07000000
218 #define KINETIS_SDID_SUBFAMID_KX8 0x08000000
220 #define KINETIS_SDID_FAMILYID_SHIFT 28
221 #define KINETIS_SDID_FAMILYID_MASK 0xF0000000
222 #define KINETIS_SDID_FAMILYID_K0X 0x00000000
223 #define KINETIS_SDID_FAMILYID_K1X 0x10000000
224 #define KINETIS_SDID_FAMILYID_K2X 0x20000000
225 #define KINETIS_SDID_FAMILYID_K3X 0x30000000
226 #define KINETIS_SDID_FAMILYID_K4X 0x40000000
227 #define KINETIS_SDID_FAMILYID_K5X 0x50000000
228 #define KINETIS_SDID_FAMILYID_K6X 0x60000000
229 #define KINETIS_SDID_FAMILYID_K7X 0x70000000
230 #define KINETIS_SDID_FAMILYID_K8X 0x80000000
231 #define KINETIS_SDID_FAMILYID_KL8X 0x90000000
233 /* The field originally named DIEID has new name/meaning on KE1x */
234 #define KINETIS_SDID_PROJECTID_MASK KINETIS_SDID_DIEID_MASK
235 #define KINETIS_SDID_PROJECTID_KE1xF 0x00000080
236 #define KINETIS_SDID_PROJECTID_KE1xZ 0x00000100
238 struct kinetis_flash_bank {
239 struct kinetis_chip *k_chip;
241 unsigned bank_number; /* bank number in particular chip */
242 struct flash_bank *bank;
244 uint32_t sector_size;
245 uint32_t protection_size;
246 uint32_t prog_base; /* base address for FTFx operations */
247 /* usually same as bank->base for pflash, differs for FlexNVM */
248 uint32_t protection_block; /* number of first protection block in this bank */
258 #define KINETIS_MAX_BANKS 4u
260 struct kinetis_chip {
261 struct target *target;
267 uint32_t fcfg2_maxaddr0_shifted;
268 uint32_t fcfg2_maxaddr1_shifted;
270 unsigned num_pflash_blocks, num_nvm_blocks;
271 unsigned pflash_sector_size, nvm_sector_size;
272 unsigned max_flash_prog_size;
274 uint32_t pflash_base;
275 uint32_t pflash_size;
277 uint32_t nvm_size; /* whole FlexNVM */
278 uint32_t dflash_size; /* accessible rest of FlexNVM if EEPROM backup uses part of FlexNVM */
280 uint32_t progr_accel_ram;
284 FS_PROGRAM_SECTOR = 1,
285 FS_PROGRAM_LONGWORD = 2,
286 FS_PROGRAM_PHRASE = 4, /* Unsupported */
288 FS_NO_CMD_BLOCKSTAT = 0x40,
289 FS_WIDTH_256BIT = 0x80,
295 KINETIS_CACHE_K, /* invalidate using FMC->PFB0CR/PFB01CR */
296 KINETIS_CACHE_L, /* invalidate using MCM->PLACR */
297 KINETIS_CACHE_MSCM, /* devices like KE1xF, invalidate MSCM->OCMDR0 */
316 struct kinetis_flash_bank banks[KINETIS_MAX_BANKS];
319 struct kinetis_type {
324 static const struct kinetis_type kinetis_types_old[] = {
325 { KINETIS_K_SDID_K10_M50, "MK10D%s5" },
326 { KINETIS_K_SDID_K10_M72, "MK10D%s7" },
327 { KINETIS_K_SDID_K10_M100, "MK10D%s10" },
328 { KINETIS_K_SDID_K10_M120, "MK10F%s12" },
329 { KINETIS_K_SDID_K11, "MK11D%s5" },
330 { KINETIS_K_SDID_K12, "MK12D%s5" },
332 { KINETIS_K_SDID_K20_M50, "MK20D%s5" },
333 { KINETIS_K_SDID_K20_M72, "MK20D%s7" },
334 { KINETIS_K_SDID_K20_M100, "MK20D%s10" },
335 { KINETIS_K_SDID_K20_M120, "MK20F%s12" },
336 { KINETIS_K_SDID_K21_M50, "MK21D%s5" },
337 { KINETIS_K_SDID_K21_M120, "MK21F%s12" },
338 { KINETIS_K_SDID_K22_M50, "MK22D%s5" },
339 { KINETIS_K_SDID_K22_M120, "MK22F%s12" },
341 { KINETIS_K_SDID_K30_M72, "MK30D%s7" },
342 { KINETIS_K_SDID_K30_M100, "MK30D%s10" },
344 { KINETIS_K_SDID_K40_M72, "MK40D%s7" },
345 { KINETIS_K_SDID_K40_M100, "MK40D%s10" },
347 { KINETIS_K_SDID_K50_M72, "MK50D%s7" },
348 { KINETIS_K_SDID_K51_M72, "MK51D%s7" },
349 { KINETIS_K_SDID_K53, "MK53D%s10" },
351 { KINETIS_K_SDID_K60_M100, "MK60D%s10" },
352 { KINETIS_K_SDID_K60_M150, "MK60F%s15" },
354 { KINETIS_K_SDID_K70_M150, "MK70F%s15" },
360 #define MDM_REG_STAT 0x00
361 #define MDM_REG_CTRL 0x04
362 #define MDM_REG_ID 0xfc
364 #define MDM_STAT_FMEACK (1<<0)
365 #define MDM_STAT_FREADY (1<<1)
366 #define MDM_STAT_SYSSEC (1<<2)
367 #define MDM_STAT_SYSRES (1<<3)
368 #define MDM_STAT_FMEEN (1<<5)
369 #define MDM_STAT_BACKDOOREN (1<<6)
370 #define MDM_STAT_LPEN (1<<7)
371 #define MDM_STAT_VLPEN (1<<8)
372 #define MDM_STAT_LLSMODEXIT (1<<9)
373 #define MDM_STAT_VLLSXMODEXIT (1<<10)
374 #define MDM_STAT_CORE_HALTED (1<<16)
375 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
376 #define MDM_STAT_CORESLEEPING (1<<18)
378 #define MDM_CTRL_FMEIP (1<<0)
379 #define MDM_CTRL_DBG_DIS (1<<1)
380 #define MDM_CTRL_DBG_REQ (1<<2)
381 #define MDM_CTRL_SYS_RES_REQ (1<<3)
382 #define MDM_CTRL_CORE_HOLD_RES (1<<4)
383 #define MDM_CTRL_VLLSX_DBG_REQ (1<<5)
384 #define MDM_CTRL_VLLSX_DBG_ACK (1<<6)
385 #define MDM_CTRL_VLLSX_STAT_ACK (1<<7)
387 #define MDM_ACCESS_TIMEOUT 500 /* msec */
390 static bool allow_fcf_writes;
391 static uint8_t fcf_fopt = 0xff;
392 static bool fcf_fopt_configured;
393 static bool create_banks;
396 const struct flash_driver kinetis_flash;
397 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
398 uint32_t offset, uint32_t count);
399 static int kinetis_probe_chip(struct kinetis_chip *k_chip);
400 static int kinetis_auto_probe(struct flash_bank *bank);
403 static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value)
406 LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
408 retval = dap_queue_ap_write(dap_ap(dap, MDM_AP), reg, value);
409 if (retval != ERROR_OK) {
410 LOG_DEBUG("MDM: failed to queue a write request");
414 retval = dap_run(dap);
415 if (retval != ERROR_OK) {
416 LOG_DEBUG("MDM: dap_run failed");
424 static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *result)
428 retval = dap_queue_ap_read(dap_ap(dap, MDM_AP), reg, result);
429 if (retval != ERROR_OK) {
430 LOG_DEBUG("MDM: failed to queue a read request");
434 retval = dap_run(dap);
435 if (retval != ERROR_OK) {
436 LOG_DEBUG("MDM: dap_run failed");
440 LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
444 static int kinetis_mdm_poll_register(struct adiv5_dap *dap, unsigned reg,
445 uint32_t mask, uint32_t value, uint32_t timeout_ms)
449 int64_t ms_timeout = timeval_ms() + timeout_ms;
452 retval = kinetis_mdm_read_register(dap, reg, &val);
453 if (retval != ERROR_OK || (val & mask) == value)
457 } while (timeval_ms() < ms_timeout);
459 LOG_DEBUG("MDM: polling timed out");
464 * This command can be used to break a watchdog reset loop when
465 * connecting to an unsecured target. Unlike other commands, halt will
466 * automatically retry as it does not know how far into the boot process
467 * it is when the command is called.
469 COMMAND_HANDLER(kinetis_mdm_halt)
471 struct target *target = get_current_target(CMD_CTX);
472 struct cortex_m_common *cortex_m = target_to_cm(target);
473 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
477 int64_t ms_timeout = timeval_ms() + MDM_ACCESS_TIMEOUT;
480 LOG_ERROR("Cannot perform halt with a high-level adapter");
487 kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_CORE_HOLD_RES);
491 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
492 if (retval != ERROR_OK) {
493 LOG_DEBUG("MDM: failed to read MDM_REG_STAT");
497 /* Repeat setting MDM_CTRL_CORE_HOLD_RES until system is out of
498 * reset with flash ready and without security
500 if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSSEC | MDM_STAT_SYSRES))
501 == (MDM_STAT_FREADY | MDM_STAT_SYSRES))
504 if (timeval_ms() >= ms_timeout) {
505 LOG_ERROR("MDM: halt timed out");
510 LOG_DEBUG("MDM: halt succeded after %d attempts.", tries);
513 /* enable polling in case kinetis_check_flash_security_status disabled it */
514 jtag_poll_set_enabled(true);
518 target->reset_halt = true;
519 target->type->assert_reset(target);
521 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
522 if (retval != ERROR_OK) {
523 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
527 target->type->deassert_reset(target);
532 COMMAND_HANDLER(kinetis_mdm_reset)
534 struct target *target = get_current_target(CMD_CTX);
535 struct cortex_m_common *cortex_m = target_to_cm(target);
536 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
540 LOG_ERROR("Cannot perform reset with a high-level adapter");
544 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ);
545 if (retval != ERROR_OK) {
546 LOG_ERROR("MDM: failed to write MDM_REG_CTRL");
550 retval = kinetis_mdm_poll_register(dap, MDM_REG_STAT, MDM_STAT_SYSRES, 0, 500);
551 if (retval != ERROR_OK) {
552 LOG_ERROR("MDM: failed to assert reset");
556 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
557 if (retval != ERROR_OK) {
558 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
566 * This function implements the procedure to mass erase the flash via
567 * SWD/JTAG on Kinetis K and L series of devices as it is described in
568 * AN4835 "Production Flash Programming Best Practices for Kinetis K-
569 * and L-series MCUs" Section 4.2.1. To prevent a watchdog reset loop,
570 * the core remains halted after this function completes as suggested
571 * by the application note.
573 COMMAND_HANDLER(kinetis_mdm_mass_erase)
575 struct target *target = get_current_target(CMD_CTX);
576 struct cortex_m_common *cortex_m = target_to_cm(target);
577 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
580 LOG_ERROR("Cannot perform mass erase with a high-level adapter");
587 * ... Power on the processor, or if power has already been
588 * applied, assert the RESET pin to reset the processor. For
589 * devices that do not have a RESET pin, write the System
590 * Reset Request bit in the MDM-AP control register after
591 * establishing communication...
594 /* assert SRST if configured */
595 bool has_srst = jtag_get_reset_config() & RESET_HAS_SRST;
597 adapter_assert_reset();
599 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ);
600 if (retval != ERROR_OK && !has_srst) {
601 LOG_ERROR("MDM: failed to assert reset");
602 goto deassert_reset_and_exit;
606 * ... Read the MDM-AP status register repeatedly and wait for
607 * stable conditions suitable for mass erase:
608 * - mass erase is enabled
610 * - reset is finished
612 * Mass erase is started as soon as all conditions are met in 32
613 * subsequent status reads.
615 * In case of not stable conditions (RESET/WDOG loop in secured device)
616 * the user is asked for manual pressing of RESET button
619 int cnt_mass_erase_disabled = 0;
621 int64_t ms_start = timeval_ms();
622 bool man_reset_requested = false;
626 int64_t ms_elapsed = timeval_ms() - ms_start;
628 if (!man_reset_requested && ms_elapsed > 100) {
629 LOG_INFO("MDM: Press RESET button now if possible.");
630 man_reset_requested = true;
633 if (ms_elapsed > 3000) {
634 LOG_ERROR("MDM: waiting for mass erase conditions timed out.");
635 LOG_INFO("Mass erase of a secured MCU is not possible without hardware reset.");
636 LOG_INFO("Connect SRST, use 'reset_config srst_only' and retry.");
637 goto deassert_reset_and_exit;
639 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
640 if (retval != ERROR_OK) {
645 if (!(stat & MDM_STAT_FMEEN)) {
647 cnt_mass_erase_disabled++;
648 if (cnt_mass_erase_disabled > 10) {
649 LOG_ERROR("MDM: mass erase is disabled");
650 goto deassert_reset_and_exit;
655 if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSRES)) == MDM_STAT_FREADY)
660 } while (cnt_ready < 32);
663 * ... Write the MDM-AP control register to set the Flash Mass
664 * Erase in Progress bit. This will start the mass erase
667 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ | MDM_CTRL_FMEIP);
668 if (retval != ERROR_OK) {
669 LOG_ERROR("MDM: failed to start mass erase");
670 goto deassert_reset_and_exit;
674 * ... Read the MDM-AP control register until the Flash Mass
675 * Erase in Progress bit clears...
676 * Data sheed defines erase time <3.6 sec/512kB flash block.
677 * The biggest device has 4 pflash blocks => timeout 16 sec.
679 retval = kinetis_mdm_poll_register(dap, MDM_REG_CTRL, MDM_CTRL_FMEIP, 0, 16000);
680 if (retval != ERROR_OK) {
681 LOG_ERROR("MDM: mass erase timeout");
682 goto deassert_reset_and_exit;
686 /* enable polling in case kinetis_check_flash_security_status disabled it */
687 jtag_poll_set_enabled(true);
691 target->reset_halt = true;
692 target->type->assert_reset(target);
695 * ... Negate the RESET signal or clear the System Reset Request
696 * bit in the MDM-AP control register.
698 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
699 if (retval != ERROR_OK)
700 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
702 target->type->deassert_reset(target);
706 deassert_reset_and_exit:
707 kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
709 adapter_deassert_reset();
713 static const uint32_t kinetis_known_mdm_ids[] = {
714 0x001C0000, /* Kinetis-K Series */
715 0x001C0020, /* Kinetis-L/M/V/E Series */
716 0x001C0030, /* Kinetis with a Cortex-M7, in time of writing KV58 */
720 * This function implements the procedure to connect to
721 * SWD/JTAG on Kinetis K and L series of devices as it is described in
722 * AN4835 "Production Flash Programming Best Practices for Kinetis K-
723 * and L-series MCUs" Section 4.1.1
725 COMMAND_HANDLER(kinetis_check_flash_security_status)
727 struct target *target = get_current_target(CMD_CTX);
728 struct cortex_m_common *cortex_m = target_to_cm(target);
729 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
732 LOG_WARNING("Cannot check flash security status with a high-level adapter");
737 return ERROR_OK; /* too early to check, in JTAG mode ops may not be initialised */
743 * ... The MDM-AP ID register can be read to verify that the
744 * connection is working correctly...
746 retval = kinetis_mdm_read_register(dap, MDM_REG_ID, &val);
747 if (retval != ERROR_OK) {
748 LOG_ERROR("MDM: failed to read ID register");
753 return ERROR_OK; /* dap not yet initialised */
756 for (size_t i = 0; i < ARRAY_SIZE(kinetis_known_mdm_ids); i++) {
757 if (val == kinetis_known_mdm_ids[i]) {
764 LOG_WARNING("MDM: unknown ID %08" PRIX32, val);
767 * ... Read the System Security bit to determine if security is enabled.
768 * If System Security = 0, then proceed. If System Security = 1, then
769 * communication with the internals of the processor, including the
770 * flash, will not be possible without issuing a mass erase command or
771 * unsecuring the part through other means (backdoor key unlock)...
773 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &val);
774 if (retval != ERROR_OK) {
775 LOG_ERROR("MDM: failed to read MDM_REG_STAT");
780 * System Security bit is also active for short time during reset.
781 * If a MCU has blank flash and runs in RESET/WDOG loop,
782 * System Security bit is active most of time!
783 * We should observe Flash Ready bit and read status several times
784 * to avoid false detection of secured MCU
786 int secured_score = 0, flash_not_ready_score = 0;
788 if ((val & (MDM_STAT_SYSSEC | MDM_STAT_FREADY)) != MDM_STAT_FREADY) {
791 for (unsigned int i = 0; i < 32; i++) {
792 stats[i] = MDM_STAT_FREADY;
793 dap_queue_ap_read(dap_ap(dap, MDM_AP), MDM_REG_STAT, &stats[i]);
795 retval = dap_run(dap);
796 if (retval != ERROR_OK) {
797 LOG_DEBUG("MDM: dap_run failed when validating secured state");
800 for (unsigned int i = 0; i < 32; i++) {
801 if (stats[i] & MDM_STAT_SYSSEC)
803 if (!(stats[i] & MDM_STAT_FREADY))
804 flash_not_ready_score++;
808 if (flash_not_ready_score <= 8 && secured_score > 24) {
809 jtag_poll_set_enabled(false);
811 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
812 LOG_WARNING("**** ****");
813 LOG_WARNING("**** Your Kinetis MCU is in secured state, which means that, ****");
814 LOG_WARNING("**** with exception for very basic communication, JTAG/SWD ****");
815 LOG_WARNING("**** interface will NOT work. In order to restore its ****");
816 LOG_WARNING("**** functionality please issue 'kinetis mdm mass_erase' ****");
817 LOG_WARNING("**** command, power cycle the MCU and restart OpenOCD. ****");
818 LOG_WARNING("**** ****");
819 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
821 } else if (flash_not_ready_score > 24) {
822 jtag_poll_set_enabled(false);
823 LOG_WARNING("**** Your Kinetis MCU is probably locked-up in RESET/WDOG loop. ****");
824 LOG_WARNING("**** Common reason is a blank flash (at least a reset vector). ****");
825 LOG_WARNING("**** Issue 'kinetis mdm halt' command or if SRST is connected ****");
826 LOG_WARNING("**** and configured, use 'reset halt' ****");
827 LOG_WARNING("**** If MCU cannot be halted, it is likely secured and running ****");
828 LOG_WARNING("**** in RESET/WDOG loop. Issue 'kinetis mdm mass_erase' ****");
831 LOG_INFO("MDM: Chip is unsecured. Continuing.");
832 jtag_poll_set_enabled(true);
839 static struct kinetis_chip *kinetis_get_chip(struct target *target)
841 struct flash_bank *bank_iter;
842 struct kinetis_flash_bank *k_bank;
844 /* iterate over all kinetis banks */
845 for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
846 if (bank_iter->driver != &kinetis_flash
847 || bank_iter->target != target)
850 k_bank = bank_iter->driver_priv;
855 return k_bank->k_chip;
860 static int kinetis_chip_options(struct kinetis_chip *k_chip, int argc, const char *argv[])
862 for (int i = 0; i < argc; i++) {
863 if (strcmp(argv[i], "-sim-base") == 0) {
865 k_chip->sim_base = strtoul(argv[++i], NULL, 0);
867 LOG_ERROR("Unsupported flash bank option %s", argv[i]);
872 FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
874 struct target *target = bank->target;
875 struct kinetis_chip *k_chip;
876 struct kinetis_flash_bank *k_bank;
880 return ERROR_COMMAND_SYNTAX_ERROR;
882 LOG_INFO("add flash_bank kinetis %s", bank->name);
884 k_chip = kinetis_get_chip(target);
886 if (k_chip == NULL) {
887 k_chip = calloc(sizeof(struct kinetis_chip), 1);
888 if (k_chip == NULL) {
889 LOG_ERROR("No memory");
893 k_chip->target = target;
895 /* only the first defined bank can define chip options */
896 retval = kinetis_chip_options(k_chip, CMD_ARGC - 6, CMD_ARGV + 6);
897 if (retval != ERROR_OK)
901 if (k_chip->num_banks >= KINETIS_MAX_BANKS) {
902 LOG_ERROR("Only %u Kinetis flash banks are supported", KINETIS_MAX_BANKS);
906 bank->driver_priv = k_bank = &(k_chip->banks[k_chip->num_banks]);
907 k_bank->k_chip = k_chip;
908 k_bank->bank_number = k_chip->num_banks;
916 static void kinetis_free_driver_priv(struct flash_bank *bank)
918 struct kinetis_flash_bank *k_bank = bank->driver_priv;
922 struct kinetis_chip *k_chip = k_bank->k_chip;
927 if (k_chip->num_banks == 0)
932 static int kinetis_create_missing_banks(struct kinetis_chip *k_chip)
935 struct kinetis_flash_bank *k_bank;
936 struct flash_bank *bank;
937 char base_name[69], name[80], num[4];
940 num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
941 if (num_blocks > KINETIS_MAX_BANKS) {
942 LOG_ERROR("Only %u Kinetis flash banks are supported", KINETIS_MAX_BANKS);
946 bank = k_chip->banks[0].bank;
947 if (bank && bank->name) {
948 strncpy(base_name, bank->name, sizeof(base_name) - 1);
949 base_name[sizeof(base_name) - 1] = '\0';
950 p = strstr(base_name, ".pflash");
953 if (k_chip->num_pflash_blocks > 1) {
954 /* rename first bank if numbering is needed */
955 snprintf(name, sizeof(name), "%s.pflash0", base_name);
957 bank->name = strdup(name);
961 strncpy(base_name, target_name(k_chip->target), sizeof(base_name) - 1);
962 base_name[sizeof(base_name) - 1] = '\0';
963 p = strstr(base_name, ".cpu");
968 for (unsigned int bank_idx = 1; bank_idx < num_blocks; bank_idx++) {
969 k_bank = &(k_chip->banks[bank_idx]);
977 if (bank_idx < k_chip->num_pflash_blocks) {
979 if (k_chip->num_pflash_blocks > 1)
980 snprintf(num, sizeof(num), "%u", bank_idx);
983 if (k_chip->num_nvm_blocks > 1)
984 snprintf(num, sizeof(num), "%u",
985 bank_idx - k_chip->num_pflash_blocks);
988 bank = calloc(sizeof(struct flash_bank), 1);
992 bank->target = k_chip->target;
993 bank->driver = &kinetis_flash;
994 bank->default_padded_value = bank->erased_value = 0xff;
996 snprintf(name, sizeof(name), "%s.%s%s",
997 base_name, class, num);
998 bank->name = strdup(name);
1000 bank->driver_priv = k_bank = &(k_chip->banks[k_chip->num_banks]);
1001 k_bank->k_chip = k_chip;
1002 k_bank->bank_number = bank_idx;
1003 k_bank->bank = bank;
1004 if (k_chip->num_banks <= bank_idx)
1005 k_chip->num_banks = bank_idx + 1;
1007 flash_bank_add(bank);
1013 static int kinetis_disable_wdog_algo(struct target *target, size_t code_size, const uint8_t *code, uint32_t wdog_base)
1015 struct working_area *wdog_algorithm;
1016 struct armv7m_algorithm armv7m_info;
1017 struct reg_param reg_params[1];
1020 if (target->state != TARGET_HALTED) {
1021 LOG_ERROR("Target not halted");
1022 return ERROR_TARGET_NOT_HALTED;
1025 retval = target_alloc_working_area(target, code_size, &wdog_algorithm);
1026 if (retval != ERROR_OK)
1029 retval = target_write_buffer(target, wdog_algorithm->address,
1031 if (retval == ERROR_OK) {
1032 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1033 armv7m_info.core_mode = ARM_MODE_THREAD;
1035 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
1036 buf_set_u32(reg_params[0].value, 0, 32, wdog_base);
1038 retval = target_run_algorithm(target, 0, NULL, 1, reg_params,
1039 wdog_algorithm->address,
1040 wdog_algorithm->address + code_size - 2,
1043 destroy_reg_param(®_params[0]);
1045 if (retval != ERROR_OK)
1046 LOG_ERROR("Error executing Kinetis WDOG unlock algorithm");
1049 target_free_working_area(target, wdog_algorithm);
1054 /* Disable the watchdog on Kinetis devices
1055 * Standard Kx WDOG peripheral checks timing and therefore requires to run algo.
1057 static int kinetis_disable_wdog_kx(struct target *target)
1059 const uint32_t wdog_base = WDOG_BASE;
1063 static const uint8_t kinetis_unlock_wdog_code[] = {
1064 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog.inc"
1067 retval = target_read_u16(target, wdog_base + WDOG_STCTRLH_OFFSET, &wdog);
1068 if (retval != ERROR_OK)
1071 if ((wdog & 0x1) == 0) {
1072 /* watchdog already disabled */
1075 LOG_INFO("Disabling Kinetis watchdog (initial WDOG_STCTRLH = 0x%04" PRIx16 ")", wdog);
1077 retval = kinetis_disable_wdog_algo(target, sizeof(kinetis_unlock_wdog_code), kinetis_unlock_wdog_code, wdog_base);
1078 if (retval != ERROR_OK)
1081 retval = target_read_u16(target, wdog_base + WDOG_STCTRLH_OFFSET, &wdog);
1082 if (retval != ERROR_OK)
1085 LOG_INFO("WDOG_STCTRLH = 0x%04" PRIx16, wdog);
1086 return (wdog & 0x1) ? ERROR_FAIL : ERROR_OK;
1089 static int kinetis_disable_wdog32(struct target *target, uint32_t wdog_base)
1094 static const uint8_t kinetis_unlock_wdog_code[] = {
1095 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog32.inc"
1098 retval = target_read_u32(target, wdog_base + WDOG32_CS_OFFSET, &wdog_cs);
1099 if (retval != ERROR_OK)
1102 if ((wdog_cs & 0x80) == 0)
1103 return ERROR_OK; /* watchdog already disabled */
1105 LOG_INFO("Disabling Kinetis watchdog (initial WDOG_CS 0x%08" PRIx32 ")", wdog_cs);
1107 retval = kinetis_disable_wdog_algo(target, sizeof(kinetis_unlock_wdog_code), kinetis_unlock_wdog_code, wdog_base);
1108 if (retval != ERROR_OK)
1111 retval = target_read_u32(target, wdog_base + WDOG32_CS_OFFSET, &wdog_cs);
1112 if (retval != ERROR_OK)
1115 if ((wdog_cs & 0x80) == 0)
1116 return ERROR_OK; /* watchdog disabled successfully */
1118 LOG_ERROR("Cannot disable Kinetis watchdog (WDOG_CS 0x%08" PRIx32 "), issue 'reset init'", wdog_cs);
1122 static int kinetis_disable_wdog(struct kinetis_chip *k_chip)
1124 struct target *target = k_chip->target;
1128 if (!k_chip->probed) {
1129 retval = kinetis_probe_chip(k_chip);
1130 if (retval != ERROR_OK)
1134 switch (k_chip->watchdog_type) {
1135 case KINETIS_WDOG_K:
1136 return kinetis_disable_wdog_kx(target);
1138 case KINETIS_WDOG_COP:
1139 retval = target_read_u8(target, SIM_COPC, &sim_copc);
1140 if (retval != ERROR_OK)
1143 if ((sim_copc & 0xc) == 0)
1144 return ERROR_OK; /* watchdog already disabled */
1146 LOG_INFO("Disabling Kinetis watchdog (initial SIM_COPC 0x%02" PRIx8 ")", sim_copc);
1147 retval = target_write_u8(target, SIM_COPC, sim_copc & ~0xc);
1148 if (retval != ERROR_OK)
1151 retval = target_read_u8(target, SIM_COPC, &sim_copc);
1152 if (retval != ERROR_OK)
1155 if ((sim_copc & 0xc) == 0)
1156 return ERROR_OK; /* watchdog disabled successfully */
1158 LOG_ERROR("Cannot disable Kinetis watchdog (SIM_COPC 0x%02" PRIx8 "), issue 'reset init'", sim_copc);
1161 case KINETIS_WDOG32_KE1X:
1162 return kinetis_disable_wdog32(target, WDOG32_KE1X);
1164 case KINETIS_WDOG32_KL28:
1165 return kinetis_disable_wdog32(target, WDOG32_KL28);
1172 COMMAND_HANDLER(kinetis_disable_wdog_handler)
1175 struct target *target = get_current_target(CMD_CTX);
1176 struct kinetis_chip *k_chip = kinetis_get_chip(target);
1182 return ERROR_COMMAND_SYNTAX_ERROR;
1184 result = kinetis_disable_wdog(k_chip);
1189 static int kinetis_ftfx_decode_error(uint8_t fstat)
1192 LOG_ERROR("Flash operation failed, illegal command");
1193 return ERROR_FLASH_OPER_UNSUPPORTED;
1195 } else if (fstat & 0x10)
1196 LOG_ERROR("Flash operation failed, protection violated");
1198 else if (fstat & 0x40)
1199 LOG_ERROR("Flash operation failed, read collision");
1201 else if (fstat & 0x80)
1205 LOG_ERROR("Flash operation timed out");
1207 return ERROR_FLASH_OPERATION_FAILED;
1210 static int kinetis_ftfx_clear_error(struct target *target)
1212 /* reset error flags */
1213 return target_write_u8(target, FTFx_FSTAT, 0x70);
1217 static int kinetis_ftfx_prepare(struct target *target)
1222 /* wait until busy */
1223 for (unsigned int i = 0; i < 50; i++) {
1224 result = target_read_u8(target, FTFx_FSTAT, &fstat);
1225 if (result != ERROR_OK)
1232 if ((fstat & 0x80) == 0) {
1233 LOG_ERROR("Flash controller is busy");
1234 return ERROR_FLASH_OPERATION_FAILED;
1236 if (fstat != 0x80) {
1237 /* reset error flags */
1238 result = kinetis_ftfx_clear_error(target);
1243 /* Kinetis Program-LongWord Microcodes */
1244 static const uint8_t kinetis_flash_write_code[] = {
1245 #include "../../../contrib/loaders/flash/kinetis/kinetis_flash.inc"
1248 /* Program LongWord Block Write */
1249 static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
1250 uint32_t offset, uint32_t wcount)
1252 struct target *target = bank->target;
1253 uint32_t buffer_size;
1254 struct working_area *write_algorithm;
1255 struct working_area *source;
1256 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1257 uint32_t address = k_bank->prog_base + offset;
1258 uint32_t end_address;
1259 struct reg_param reg_params[5];
1260 struct armv7m_algorithm armv7m_info;
1264 /* allocate working area with flash programming code */
1265 if (target_alloc_working_area(target, sizeof(kinetis_flash_write_code),
1266 &write_algorithm) != ERROR_OK) {
1267 LOG_WARNING("no working area available, can't do block memory writes");
1268 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1271 retval = target_write_buffer(target, write_algorithm->address,
1272 sizeof(kinetis_flash_write_code), kinetis_flash_write_code);
1273 if (retval != ERROR_OK)
1276 /* memory buffer, size *must* be multiple of word */
1277 buffer_size = target_get_working_area_avail(target) & ~(sizeof(uint32_t) - 1);
1278 if (buffer_size < 256) {
1279 LOG_WARNING("large enough working area not available, can't do block memory writes");
1280 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1281 } else if (buffer_size > 16384) {
1282 /* probably won't benefit from more than 16k ... */
1283 buffer_size = 16384;
1286 if (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
1287 LOG_ERROR("allocating working area failed");
1288 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1291 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1292 armv7m_info.core_mode = ARM_MODE_THREAD;
1294 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* address */
1295 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* word count */
1296 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
1297 init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
1298 init_reg_param(®_params[4], "r4", 32, PARAM_OUT);
1300 buf_set_u32(reg_params[0].value, 0, 32, address);
1301 buf_set_u32(reg_params[1].value, 0, 32, wcount);
1302 buf_set_u32(reg_params[2].value, 0, 32, source->address);
1303 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
1304 buf_set_u32(reg_params[4].value, 0, 32, FTFx_FSTAT);
1306 retval = target_run_flash_async_algorithm(target, buffer, wcount, 4,
1309 source->address, source->size,
1310 write_algorithm->address, 0,
1313 if (retval == ERROR_FLASH_OPERATION_FAILED) {
1314 end_address = buf_get_u32(reg_params[0].value, 0, 32);
1316 LOG_ERROR("Error writing flash at %08" PRIx32, end_address);
1318 retval = target_read_u8(target, FTFx_FSTAT, &fstat);
1319 if (retval == ERROR_OK) {
1320 retval = kinetis_ftfx_decode_error(fstat);
1322 /* reset error flags */
1323 target_write_u8(target, FTFx_FSTAT, 0x70);
1325 } else if (retval != ERROR_OK)
1326 LOG_ERROR("Error executing kinetis Flash programming algorithm");
1328 target_free_working_area(target, source);
1329 target_free_working_area(target, write_algorithm);
1331 destroy_reg_param(®_params[0]);
1332 destroy_reg_param(®_params[1]);
1333 destroy_reg_param(®_params[2]);
1334 destroy_reg_param(®_params[3]);
1335 destroy_reg_param(®_params[4]);
1340 static int kinetis_protect(struct flash_bank *bank, int set, unsigned int first,
1343 if (allow_fcf_writes) {
1344 LOG_ERROR("Protection setting is possible with 'kinetis fcf_source protection' only!");
1348 if (!bank->prot_blocks || bank->num_prot_blocks == 0) {
1349 LOG_ERROR("No protection possible for current bank!");
1350 return ERROR_FLASH_BANK_INVALID;
1353 for (unsigned int i = first; i < bank->num_prot_blocks && i <= last; i++)
1354 bank->prot_blocks[i].is_protected = set;
1356 LOG_INFO("Protection bits will be written at the next FCF sector erase or write.");
1357 LOG_INFO("Do not issue 'flash info' command until protection is written,");
1358 LOG_INFO("doing so would re-read protection status from MCU.");
1363 static int kinetis_protect_check(struct flash_bank *bank)
1365 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1370 if (k_bank->flash_class == FC_PFLASH) {
1372 /* read protection register */
1373 result = target_read_u32(bank->target, FTFx_FPROT3, &fprot);
1374 if (result != ERROR_OK)
1377 /* Every bit protects 1/32 of the full flash (not necessarily just this bank) */
1379 } else if (k_bank->flash_class == FC_FLEX_NVM) {
1382 /* read protection register */
1383 result = target_read_u8(bank->target, FTFx_FDPROT, &fdprot);
1384 if (result != ERROR_OK)
1390 LOG_ERROR("Protection checks for FlexRAM not supported");
1391 return ERROR_FLASH_BANK_INVALID;
1394 b = k_bank->protection_block;
1395 for (unsigned int i = 0; i < bank->num_prot_blocks; i++) {
1396 if ((fprot >> b) & 1)
1397 bank->prot_blocks[i].is_protected = 0;
1399 bank->prot_blocks[i].is_protected = 1;
1408 static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
1410 uint32_t fprot = 0xffffffff;
1411 uint8_t fsec = 0xfe; /* set MCU unsecure */
1412 uint8_t fdprot = 0xff;
1413 unsigned num_blocks;
1414 uint32_t pflash_bit;
1416 struct flash_bank *bank_iter;
1417 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1418 struct kinetis_chip *k_chip = k_bank->k_chip;
1420 memset(fcf, 0xff, FCF_SIZE);
1425 /* iterate over all kinetis banks */
1426 /* current bank is bank 0, it contains FCF */
1427 num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
1428 for (unsigned int bank_idx = 0; bank_idx < num_blocks; bank_idx++) {
1429 k_bank = &(k_chip->banks[bank_idx]);
1430 bank_iter = k_bank->bank;
1432 if (bank_iter == NULL) {
1433 LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplette", bank_idx);
1437 kinetis_auto_probe(bank_iter);
1439 assert(bank_iter->prot_blocks);
1441 if (k_bank->flash_class == FC_PFLASH) {
1442 for (unsigned int i = 0; i < bank_iter->num_prot_blocks; i++) {
1443 if (bank_iter->prot_blocks[i].is_protected == 1)
1444 fprot &= ~pflash_bit;
1449 } else if (k_bank->flash_class == FC_FLEX_NVM) {
1450 for (unsigned int i = 0; i < bank_iter->num_prot_blocks; i++) {
1451 if (bank_iter->prot_blocks[i].is_protected == 1)
1452 fdprot &= ~dflash_bit;
1460 target_buffer_set_u32(bank->target, fcf + FCF_FPROT, fprot);
1461 fcf[FCF_FSEC] = fsec;
1462 fcf[FCF_FOPT] = fcf_fopt;
1463 fcf[FCF_FDPROT] = fdprot;
1467 static int kinetis_ftfx_command(struct target *target, uint8_t fcmd, uint32_t faddr,
1468 uint8_t fccob4, uint8_t fccob5, uint8_t fccob6, uint8_t fccob7,
1469 uint8_t fccob8, uint8_t fccob9, uint8_t fccoba, uint8_t fccobb,
1470 uint8_t *ftfx_fstat)
1472 uint8_t command[12] = {faddr & 0xff, (faddr >> 8) & 0xff, (faddr >> 16) & 0xff, fcmd,
1473 fccob7, fccob6, fccob5, fccob4,
1474 fccobb, fccoba, fccob9, fccob8};
1477 int64_t ms_timeout = timeval_ms() + 250;
1479 result = target_write_memory(target, FTFx_FCCOB3, 4, 3, command);
1480 if (result != ERROR_OK)
1484 result = target_write_u8(target, FTFx_FSTAT, 0x80);
1485 if (result != ERROR_OK)
1490 result = target_read_u8(target, FTFx_FSTAT, &fstat);
1492 if (result != ERROR_OK)
1498 } while (timeval_ms() < ms_timeout);
1501 *ftfx_fstat = fstat;
1503 if ((fstat & 0xf0) != 0x80) {
1504 LOG_DEBUG("ftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X",
1505 fstat, command[3], command[2], command[1], command[0],
1506 command[7], command[6], command[5], command[4],
1507 command[11], command[10], command[9], command[8]);
1509 return kinetis_ftfx_decode_error(fstat);
1516 static int kinetis_read_pmstat(struct kinetis_chip *k_chip, uint8_t *pmstat)
1520 struct target *target = k_chip->target;
1522 switch (k_chip->sysmodectrlr_type) {
1524 result = target_read_u8(target, SMC_PMSTAT, pmstat);
1528 result = target_read_u32(target, SMC32_PMSTAT, &stat32);
1529 if (result == ERROR_OK)
1530 *pmstat = stat32 & 0xff;
1536 static int kinetis_check_run_mode(struct kinetis_chip *k_chip)
1540 struct target *target;
1542 if (k_chip == NULL) {
1543 LOG_ERROR("Chip not probed.");
1546 target = k_chip->target;
1548 if (target->state != TARGET_HALTED) {
1549 LOG_ERROR("Target not halted");
1550 return ERROR_TARGET_NOT_HALTED;
1553 result = kinetis_read_pmstat(k_chip, &pmstat);
1554 if (result != ERROR_OK)
1557 if (pmstat == PM_STAT_RUN)
1560 if (pmstat == PM_STAT_VLPR) {
1561 /* It is safe to switch from VLPR to RUN mode without changing clock */
1562 LOG_INFO("Switching from VLPR to RUN mode.");
1564 switch (k_chip->sysmodectrlr_type) {
1566 result = target_write_u8(target, SMC_PMCTRL, PM_CTRL_RUNM_RUN);
1570 result = target_write_u32(target, SMC32_PMCTRL, PM_CTRL_RUNM_RUN);
1573 if (result != ERROR_OK)
1576 for (unsigned int i = 100; i > 0; i--) {
1577 result = kinetis_read_pmstat(k_chip, &pmstat);
1578 if (result != ERROR_OK)
1581 if (pmstat == PM_STAT_RUN)
1586 LOG_ERROR("Flash operation not possible in current run mode: SMC_PMSTAT: 0x%x", pmstat);
1587 LOG_ERROR("Issue a 'reset init' command.");
1588 return ERROR_TARGET_NOT_HALTED;
1592 static void kinetis_invalidate_flash_cache(struct kinetis_chip *k_chip)
1594 struct target *target = k_chip->target;
1596 switch (k_chip->cache_type) {
1597 case KINETIS_CACHE_K:
1598 target_write_u8(target, FMC_PFB01CR + 2, 0xf0);
1599 /* Set CINV_WAY bits - request invalidate of all cache ways */
1600 /* FMC_PFB0CR has same address and CINV_WAY bits as FMC_PFB01CR */
1603 case KINETIS_CACHE_L:
1604 target_write_u8(target, MCM_PLACR + 1, 0x04);
1605 /* set bit CFCC - Clear Flash Controller Cache */
1608 case KINETIS_CACHE_MSCM:
1609 target_write_u32(target, MSCM_OCMDR0, 0x30);
1610 /* disable data prefetch and flash speculate */
1619 static int kinetis_erase(struct flash_bank *bank, unsigned int first,
1623 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1624 struct kinetis_chip *k_chip = k_bank->k_chip;
1626 result = kinetis_check_run_mode(k_chip);
1627 if (result != ERROR_OK)
1630 /* reset error flags */
1631 result = kinetis_ftfx_prepare(bank->target);
1632 if (result != ERROR_OK)
1635 if ((first > bank->num_sectors) || (last > bank->num_sectors))
1636 return ERROR_FLASH_OPERATION_FAILED;
1639 * FIXME: TODO: use the 'Erase Flash Block' command if the
1640 * requested erase is PFlash or NVM and encompasses the entire
1641 * block. Should be quicker.
1643 for (unsigned int i = first; i <= last; i++) {
1644 /* set command and sector address */
1645 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTERASE, k_bank->prog_base + bank->sectors[i].offset,
1646 0, 0, 0, 0, 0, 0, 0, 0, NULL);
1648 if (result != ERROR_OK) {
1649 LOG_WARNING("erase sector %u failed", i);
1650 return ERROR_FLASH_OPERATION_FAILED;
1653 bank->sectors[i].is_erased = 1;
1655 if (k_bank->prog_base == 0
1656 && bank->sectors[i].offset <= FCF_ADDRESS
1657 && bank->sectors[i].offset + bank->sectors[i].size > FCF_ADDRESS + FCF_SIZE) {
1658 if (allow_fcf_writes) {
1659 LOG_WARNING("Flash Configuration Field erased, DO NOT reset or power off the device");
1660 LOG_WARNING("until correct FCF is programmed or MCU gets security lock.");
1662 uint8_t fcf_buffer[FCF_SIZE];
1664 kinetis_fill_fcf(bank, fcf_buffer);
1665 result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1666 if (result != ERROR_OK)
1667 LOG_WARNING("Flash Configuration Field write failed");
1668 bank->sectors[i].is_erased = 0;
1673 kinetis_invalidate_flash_cache(k_bank->k_chip);
1678 static int kinetis_make_ram_ready(struct target *target)
1683 /* check if ram ready */
1684 result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
1685 if (result != ERROR_OK)
1688 if (ftfx_fcnfg & (1 << 1))
1689 return ERROR_OK; /* ram ready */
1691 /* make flex ram available */
1692 result = kinetis_ftfx_command(target, FTFx_CMD_SETFLEXRAM, 0x00ff0000,
1693 0, 0, 0, 0, 0, 0, 0, 0, NULL);
1694 if (result != ERROR_OK)
1695 return ERROR_FLASH_OPERATION_FAILED;
1698 result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
1699 if (result != ERROR_OK)
1702 if (ftfx_fcnfg & (1 << 1))
1703 return ERROR_OK; /* ram ready */
1705 return ERROR_FLASH_OPERATION_FAILED;
1709 static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer,
1710 uint32_t offset, uint32_t count)
1712 int result = ERROR_OK;
1713 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1714 struct kinetis_chip *k_chip = k_bank->k_chip;
1715 uint8_t *buffer_aligned = NULL;
1717 * Kinetis uses different terms for the granularity of
1718 * sector writes, e.g. "phrase" or "128 bits". We use
1719 * the generic term "chunk". The largest possible
1720 * Kinetis "chunk" is 16 bytes (128 bits).
1722 uint32_t prog_section_chunk_bytes = k_bank->sector_size >> 8;
1723 uint32_t prog_size_bytes = k_chip->max_flash_prog_size;
1726 uint32_t size = prog_size_bytes - offset % prog_size_bytes;
1727 uint32_t align_begin = offset % prog_section_chunk_bytes;
1729 uint32_t size_aligned;
1730 uint16_t chunk_count;
1736 align_end = (align_begin + size) % prog_section_chunk_bytes;
1738 align_end = prog_section_chunk_bytes - align_end;
1740 size_aligned = align_begin + size + align_end;
1741 chunk_count = size_aligned / prog_section_chunk_bytes;
1743 if (size != size_aligned) {
1744 /* aligned section: the first, the last or the only */
1745 if (!buffer_aligned)
1746 buffer_aligned = malloc(prog_size_bytes);
1748 memset(buffer_aligned, 0xff, size_aligned);
1749 memcpy(buffer_aligned + align_begin, buffer, size);
1751 result = target_write_memory(bank->target, k_chip->progr_accel_ram,
1752 4, size_aligned / 4, buffer_aligned);
1754 LOG_DEBUG("section @ " TARGET_ADDR_FMT " aligned begin %" PRIu32
1756 bank->base + offset, align_begin, align_end);
1758 result = target_write_memory(bank->target, k_chip->progr_accel_ram,
1759 4, size_aligned / 4, buffer);
1761 LOG_DEBUG("write section @ " TARGET_ADDR_FMT " with length %" PRIu32
1763 bank->base + offset, size);
1765 if (result != ERROR_OK) {
1766 LOG_ERROR("target_write_memory failed");
1770 /* execute section-write command */
1771 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTWRITE,
1772 k_bank->prog_base + offset - align_begin,
1773 chunk_count>>8, chunk_count, 0, 0,
1774 0, 0, 0, 0, &ftfx_fstat);
1776 if (result != ERROR_OK) {
1777 LOG_ERROR("Error writing section at " TARGET_ADDR_FMT,
1778 bank->base + offset);
1782 if (ftfx_fstat & 0x01) {
1783 LOG_ERROR("Flash write error at " TARGET_ADDR_FMT,
1784 bank->base + offset);
1785 if (k_bank->prog_base == 0 && offset == FCF_ADDRESS + FCF_SIZE
1786 && (k_chip->flash_support & FS_WIDTH_256BIT)) {
1787 LOG_ERROR("Flash write immediately after the end of Flash Config Field shows error");
1788 LOG_ERROR("because the flash memory is 256 bits wide (data were written correctly).");
1789 LOG_ERROR("Either change the linker script to add a gap of 16 bytes after FCF");
1790 LOG_ERROR("or set 'kinetis fcf_source write'");
1801 free(buffer_aligned);
1806 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
1807 uint32_t offset, uint32_t count)
1810 bool fallback = false;
1811 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1812 struct kinetis_chip *k_chip = k_bank->k_chip;
1814 if (!(k_chip->flash_support & FS_PROGRAM_SECTOR)) {
1815 /* fallback to longword write */
1817 LOG_INFO("This device supports Program Longword execution only.");
1819 result = kinetis_make_ram_ready(bank->target);
1820 if (result != ERROR_OK) {
1822 LOG_WARNING("FlexRAM not ready, fallback to slow longword write.");
1826 LOG_DEBUG("flash write @ " TARGET_ADDR_FMT, bank->base + offset);
1829 /* program section command */
1830 kinetis_write_sections(bank, buffer, offset, count);
1831 } else if (k_chip->flash_support & FS_PROGRAM_LONGWORD) {
1832 /* program longword command, not supported in FTFE */
1833 uint8_t *new_buffer = NULL;
1835 /* check word alignment */
1837 LOG_ERROR("offset 0x%" PRIx32 " breaks the required alignment", offset);
1838 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1842 uint32_t old_count = count;
1843 count = (old_count | 3) + 1;
1844 new_buffer = malloc(count);
1845 if (new_buffer == NULL) {
1846 LOG_ERROR("odd number of bytes to write and no memory "
1847 "for padding buffer");
1850 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
1851 "and padding with 0xff", old_count, count);
1852 memset(new_buffer + old_count, 0xff, count - old_count);
1853 buffer = memcpy(new_buffer, buffer, old_count);
1856 uint32_t words_remaining = count / 4;
1858 kinetis_disable_wdog(k_chip);
1860 /* try using a block write */
1861 result = kinetis_write_block(bank, buffer, offset, words_remaining);
1863 if (result == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1864 /* if block write failed (no sufficient working area),
1865 * we use normal (slow) single word accesses */
1866 LOG_WARNING("couldn't use block writes, falling back to single "
1869 while (words_remaining) {
1872 LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
1874 result = kinetis_ftfx_command(bank->target, FTFx_CMD_LWORDPROG, k_bank->prog_base + offset,
1875 buffer[3], buffer[2], buffer[1], buffer[0],
1876 0, 0, 0, 0, &ftfx_fstat);
1878 if (result != ERROR_OK) {
1879 LOG_ERROR("Error writing longword at " TARGET_ADDR_FMT,
1880 bank->base + offset);
1884 if (ftfx_fstat & 0x01)
1885 LOG_ERROR("Flash write error at " TARGET_ADDR_FMT,
1886 bank->base + offset);
1897 LOG_ERROR("Flash write strategy not implemented");
1898 return ERROR_FLASH_OPERATION_FAILED;
1901 kinetis_invalidate_flash_cache(k_chip);
1906 static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
1907 uint32_t offset, uint32_t count)
1910 bool set_fcf = false;
1911 bool fcf_in_data_valid = false;
1913 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1914 struct kinetis_chip *k_chip = k_bank->k_chip;
1915 uint8_t fcf_buffer[FCF_SIZE];
1916 uint8_t fcf_current[FCF_SIZE];
1917 uint8_t fcf_in_data[FCF_SIZE];
1919 result = kinetis_check_run_mode(k_chip);
1920 if (result != ERROR_OK)
1923 /* reset error flags */
1924 result = kinetis_ftfx_prepare(bank->target);
1925 if (result != ERROR_OK)
1928 if (k_bank->prog_base == 0 && !allow_fcf_writes) {
1929 if (bank->sectors[1].offset <= FCF_ADDRESS)
1930 sect = 1; /* 1kb sector, FCF in 2nd sector */
1932 if (offset < bank->sectors[sect].offset + bank->sectors[sect].size
1933 && offset + count > bank->sectors[sect].offset)
1934 set_fcf = true; /* write to any part of sector with FCF */
1938 kinetis_fill_fcf(bank, fcf_buffer);
1940 fcf_in_data_valid = offset <= FCF_ADDRESS
1941 && offset + count >= FCF_ADDRESS + FCF_SIZE;
1942 if (fcf_in_data_valid) {
1943 memcpy(fcf_in_data, buffer + FCF_ADDRESS - offset, FCF_SIZE);
1944 if (memcmp(fcf_in_data + FCF_FPROT, fcf_buffer, 4)) {
1945 fcf_in_data_valid = false;
1946 LOG_INFO("Flash protection requested in programmed file differs from current setting.");
1948 if (fcf_in_data[FCF_FDPROT] != fcf_buffer[FCF_FDPROT]) {
1949 fcf_in_data_valid = false;
1950 LOG_INFO("Data flash protection requested in programmed file differs from current setting.");
1952 if ((fcf_in_data[FCF_FSEC] & 3) != 2) {
1953 fcf_in_data_valid = false;
1954 LOG_INFO("Device security requested in programmed file!");
1955 } else if (k_chip->flash_support & FS_ECC
1956 && fcf_in_data[FCF_FSEC] != fcf_buffer[FCF_FSEC]) {
1957 fcf_in_data_valid = false;
1958 LOG_INFO("Strange unsecure mode 0x%02" PRIx8
1959 "requested in programmed file!",
1960 fcf_in_data[FCF_FSEC]);
1962 if ((k_chip->flash_support & FS_ECC || fcf_fopt_configured)
1963 && fcf_in_data[FCF_FOPT] != fcf_fopt) {
1964 fcf_in_data_valid = false;
1965 LOG_INFO("FOPT requested in programmed file differs from current setting.");
1967 if (!fcf_in_data_valid)
1968 LOG_INFO("Expect verify errors at FCF (0x408-0x40f).");
1972 if (set_fcf && !fcf_in_data_valid) {
1973 if (offset < FCF_ADDRESS) {
1974 /* write part preceding FCF */
1975 result = kinetis_write_inner(bank, buffer, offset, FCF_ADDRESS - offset);
1976 if (result != ERROR_OK)
1980 result = target_read_memory(bank->target, bank->base + FCF_ADDRESS, 4, FCF_SIZE / 4, fcf_current);
1981 if (result == ERROR_OK && memcmp(fcf_current, fcf_buffer, FCF_SIZE) == 0)
1985 /* write FCF if differs from flash - eliminate multiple writes */
1986 result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1987 if (result != ERROR_OK)
1991 LOG_WARNING("Flash Configuration Field written.");
1992 LOG_WARNING("Reset or power off the device to make settings effective.");
1994 if (offset + count > FCF_ADDRESS + FCF_SIZE) {
1995 uint32_t delta = FCF_ADDRESS + FCF_SIZE - offset;
1996 /* write part after FCF */
1997 result = kinetis_write_inner(bank, buffer + delta, FCF_ADDRESS + FCF_SIZE, count - delta);
2002 /* no FCF fiddling, normal write */
2003 return kinetis_write_inner(bank, buffer, offset, count);
2008 static int kinetis_probe_chip(struct kinetis_chip *k_chip)
2011 uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg1_depart;
2012 uint8_t fcfg2_pflsh;
2013 uint32_t ee_size = 0;
2014 uint32_t pflash_size_k, nvm_size_k, dflash_size_k;
2015 uint32_t pflash_size_m;
2016 unsigned num_blocks = 0;
2017 unsigned maxaddr_shift = 13;
2018 struct target *target = k_chip->target;
2020 unsigned familyid = 0, subfamid = 0;
2021 unsigned cpu_mhz = 120;
2022 bool use_nvm_marking = false;
2023 char flash_marking[12], nvm_marking[2];
2026 k_chip->probed = false;
2027 k_chip->pflash_sector_size = 0;
2028 k_chip->pflash_base = 0;
2029 k_chip->nvm_base = 0x10000000;
2030 k_chip->progr_accel_ram = FLEXRAM;
2034 if (k_chip->sim_base)
2035 result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2037 result = target_read_u32(target, SIM_BASE + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2038 if (result == ERROR_OK)
2039 k_chip->sim_base = SIM_BASE;
2041 result = target_read_u32(target, SIM_BASE_KL28 + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2042 if (result == ERROR_OK)
2043 k_chip->sim_base = SIM_BASE_KL28;
2046 if (result != ERROR_OK)
2049 if ((k_chip->sim_sdid & (~KINETIS_SDID_K_SERIES_MASK)) == 0) {
2050 /* older K-series MCU */
2051 uint32_t mcu_type = k_chip->sim_sdid & KINETIS_K_SDID_TYPE_MASK;
2052 k_chip->cache_type = KINETIS_CACHE_K;
2053 k_chip->watchdog_type = KINETIS_WDOG_K;
2056 case KINETIS_K_SDID_K10_M50:
2057 case KINETIS_K_SDID_K20_M50:
2059 k_chip->pflash_sector_size = 1<<10;
2060 k_chip->nvm_sector_size = 1<<10;
2062 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2064 case KINETIS_K_SDID_K10_M72:
2065 case KINETIS_K_SDID_K20_M72:
2066 case KINETIS_K_SDID_K30_M72:
2067 case KINETIS_K_SDID_K30_M100:
2068 case KINETIS_K_SDID_K40_M72:
2069 case KINETIS_K_SDID_K40_M100:
2070 case KINETIS_K_SDID_K50_M72:
2071 /* 2kB sectors, 1kB FlexNVM sectors */
2072 k_chip->pflash_sector_size = 2<<10;
2073 k_chip->nvm_sector_size = 1<<10;
2075 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2076 k_chip->max_flash_prog_size = 1<<10;
2078 case KINETIS_K_SDID_K10_M100:
2079 case KINETIS_K_SDID_K20_M100:
2080 case KINETIS_K_SDID_K11:
2081 case KINETIS_K_SDID_K12:
2082 case KINETIS_K_SDID_K21_M50:
2083 case KINETIS_K_SDID_K22_M50:
2084 case KINETIS_K_SDID_K51_M72:
2085 case KINETIS_K_SDID_K53:
2086 case KINETIS_K_SDID_K60_M100:
2088 k_chip->pflash_sector_size = 2<<10;
2089 k_chip->nvm_sector_size = 2<<10;
2091 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2093 case KINETIS_K_SDID_K21_M120:
2094 case KINETIS_K_SDID_K22_M120:
2095 /* 4kB sectors (MK21FN1M0, MK21FX512, MK22FN1M0, MK22FX512) */
2096 k_chip->pflash_sector_size = 4<<10;
2097 k_chip->max_flash_prog_size = 1<<10;
2098 k_chip->nvm_sector_size = 4<<10;
2100 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2102 case KINETIS_K_SDID_K10_M120:
2103 case KINETIS_K_SDID_K20_M120:
2104 case KINETIS_K_SDID_K60_M150:
2105 case KINETIS_K_SDID_K70_M150:
2107 k_chip->pflash_sector_size = 4<<10;
2108 k_chip->nvm_sector_size = 4<<10;
2110 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2113 LOG_ERROR("Unsupported K-family FAMID");
2116 for (size_t idx = 0; idx < ARRAY_SIZE(kinetis_types_old); idx++) {
2117 if (kinetis_types_old[idx].sdid == mcu_type) {
2118 strcpy(name, kinetis_types_old[idx].name);
2119 use_nvm_marking = true;
2125 /* Newer K-series or KL series MCU */
2126 familyid = (k_chip->sim_sdid & KINETIS_SDID_FAMILYID_MASK) >> KINETIS_SDID_FAMILYID_SHIFT;
2127 subfamid = (k_chip->sim_sdid & KINETIS_SDID_SUBFAMID_MASK) >> KINETIS_SDID_SUBFAMID_SHIFT;
2129 switch (k_chip->sim_sdid & KINETIS_SDID_SERIESID_MASK) {
2130 case KINETIS_SDID_SERIESID_K:
2131 use_nvm_marking = true;
2132 k_chip->cache_type = KINETIS_CACHE_K;
2133 k_chip->watchdog_type = KINETIS_WDOG_K;
2135 switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2136 case KINETIS_SDID_FAMILYID_K0X | KINETIS_SDID_SUBFAMID_KX2:
2137 /* K02FN64, K02FN128: FTFA, 2kB sectors */
2138 k_chip->pflash_sector_size = 2<<10;
2140 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2144 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX2: {
2145 /* MK24FN1M reports as K22, this should detect it (according to errata note 1N83J) */
2147 result = target_read_u32(target, k_chip->sim_base + SIM_SOPT1_OFFSET, &sopt1);
2148 if (result != ERROR_OK)
2151 if (((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN1M) &&
2152 ((sopt1 & KINETIS_SOPT1_RAMSIZE_MASK) == KINETIS_SOPT1_RAMSIZE_K24FN1M)) {
2154 k_chip->pflash_sector_size = 4<<10;
2156 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2157 k_chip->max_flash_prog_size = 1<<10;
2158 subfamid = 4; /* errata 1N83J fix */
2161 if ((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN128
2162 || (k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN256
2163 || (k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN512) {
2164 /* K22 with new-style SDID - smaller pflash with FTFA, 2kB sectors */
2165 k_chip->pflash_sector_size = 2<<10;
2166 /* autodetect 1 or 2 blocks */
2167 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2170 LOG_ERROR("Unsupported Kinetis K22 DIEID");
2173 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX4:
2174 k_chip->pflash_sector_size = 4<<10;
2175 if ((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN256) {
2176 /* K24FN256 - smaller pflash with FTFA */
2178 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2181 /* K24FN1M without errata 7534 */
2183 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2184 k_chip->max_flash_prog_size = 1<<10;
2187 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX1: /* errata 7534 - should be K63 */
2188 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX2: /* errata 7534 - should be K64 */
2189 subfamid += 2; /* errata 7534 fix */
2191 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX3:
2193 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX4:
2194 /* K64FN1M0, K64FX512 */
2195 k_chip->pflash_sector_size = 4<<10;
2196 k_chip->nvm_sector_size = 4<<10;
2197 k_chip->max_flash_prog_size = 1<<10;
2199 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2202 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX6:
2204 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX6:
2205 /* K66FN2M0, K66FX1M0 */
2206 k_chip->pflash_sector_size = 4<<10;
2207 k_chip->nvm_sector_size = 4<<10;
2208 k_chip->max_flash_prog_size = 1<<10;
2210 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_ECC;
2214 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX7:
2216 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX8:
2218 k_chip->pflash_sector_size = 4<<10;
2219 k_chip->max_flash_prog_size = 1<<10;
2221 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_ECC;
2225 case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX0:
2226 case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX1:
2227 case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX2:
2228 /* K80FN256, K81FN256, K82FN256 */
2229 k_chip->pflash_sector_size = 4<<10;
2231 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_NO_CMD_BLOCKSTAT;
2235 case KINETIS_SDID_FAMILYID_KL8X | KINETIS_SDID_SUBFAMID_KX1:
2236 case KINETIS_SDID_FAMILYID_KL8X | KINETIS_SDID_SUBFAMID_KX2:
2237 /* KL81Z128, KL82Z128 */
2238 k_chip->pflash_sector_size = 2<<10;
2240 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_NO_CMD_BLOCKSTAT;
2241 k_chip->cache_type = KINETIS_CACHE_L;
2243 use_nvm_marking = false;
2244 snprintf(name, sizeof(name), "MKL8%uZ%%s7",
2249 LOG_ERROR("Unsupported Kinetis FAMILYID SUBFAMID");
2252 if (name[0] == '\0')
2253 snprintf(name, sizeof(name), "MK%u%uF%%s%u",
2254 familyid, subfamid, cpu_mhz / 10);
2257 case KINETIS_SDID_SERIESID_KL:
2259 k_chip->pflash_sector_size = 1<<10;
2260 k_chip->nvm_sector_size = 1<<10;
2261 /* autodetect 1 or 2 blocks */
2262 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2263 k_chip->cache_type = KINETIS_CACHE_L;
2264 k_chip->watchdog_type = KINETIS_WDOG_COP;
2267 switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2268 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX3:
2269 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX3:
2273 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX8:
2275 k_chip->pflash_sector_size = 2<<10;
2277 k_chip->watchdog_type = KINETIS_WDOG32_KL28;
2278 k_chip->sysmodectrlr_type = KINETIS_SMC32;
2282 snprintf(name, sizeof(name), "MKL%u%uZ%%s%u",
2283 familyid, subfamid, cpu_mhz / 10);
2286 case KINETIS_SDID_SERIESID_KW:
2287 /* Newer KW-series (all KW series except KW2xD, KW01Z) */
2289 switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2290 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX0:
2292 case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX0:
2294 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX0:
2296 /* FTFA, 1kB sectors */
2297 k_chip->pflash_sector_size = 1<<10;
2298 k_chip->nvm_sector_size = 1<<10;
2299 /* autodetect 1 or 2 blocks */
2300 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2301 k_chip->cache_type = KINETIS_CACHE_L;
2302 k_chip->watchdog_type = KINETIS_WDOG_COP;
2304 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX1:
2306 case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX1:
2308 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX1:
2310 /* FTFA, 2kB sectors */
2311 k_chip->pflash_sector_size = 2<<10;
2312 k_chip->nvm_sector_size = 2<<10;
2313 /* autodetect 1 or 2 blocks */
2314 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2315 k_chip->cache_type = KINETIS_CACHE_L;
2316 k_chip->watchdog_type = KINETIS_WDOG_COP;
2319 LOG_ERROR("Unsupported KW FAMILYID SUBFAMID");
2321 snprintf(name, sizeof(name), "MKW%u%uZ%%s%u",
2322 familyid, subfamid, cpu_mhz / 10);
2325 case KINETIS_SDID_SERIESID_KV:
2327 k_chip->watchdog_type = KINETIS_WDOG_K;
2328 switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2329 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX0:
2330 /* KV10: FTFA, 1kB sectors */
2331 k_chip->pflash_sector_size = 1<<10;
2333 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2334 k_chip->cache_type = KINETIS_CACHE_L;
2335 strcpy(name, "MKV10Z%s7");
2338 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX1:
2339 /* KV11: FTFA, 2kB sectors */
2340 k_chip->pflash_sector_size = 2<<10;
2342 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2343 k_chip->cache_type = KINETIS_CACHE_L;
2344 strcpy(name, "MKV11Z%s7");
2347 case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX0:
2348 /* KV30: FTFA, 2kB sectors, 1 block */
2349 case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX1:
2350 /* KV31: FTFA, 2kB sectors, 2 blocks */
2351 k_chip->pflash_sector_size = 2<<10;
2352 /* autodetect 1 or 2 blocks */
2353 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2354 k_chip->cache_type = KINETIS_CACHE_K;
2357 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX2:
2358 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX4:
2359 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX6:
2360 /* KV4x: FTFA, 4kB sectors */
2361 k_chip->pflash_sector_size = 4<<10;
2363 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2364 k_chip->cache_type = KINETIS_CACHE_K;
2368 case KINETIS_SDID_FAMILYID_K5X | KINETIS_SDID_SUBFAMID_KX6:
2369 case KINETIS_SDID_FAMILYID_K5X | KINETIS_SDID_SUBFAMID_KX8:
2370 /* KV5x: FTFE, 8kB sectors */
2371 k_chip->pflash_sector_size = 8<<10;
2372 k_chip->max_flash_prog_size = 1<<10;
2375 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_WIDTH_256BIT | FS_ECC;
2376 k_chip->pflash_base = 0x10000000;
2377 k_chip->progr_accel_ram = 0x18000000;
2382 LOG_ERROR("Unsupported KV FAMILYID SUBFAMID");
2385 if (name[0] == '\0')
2386 snprintf(name, sizeof(name), "MKV%u%uF%%s%u",
2387 familyid, subfamid, cpu_mhz / 10);
2390 case KINETIS_SDID_SERIESID_KE:
2392 k_chip->watchdog_type = KINETIS_WDOG32_KE1X;
2393 switch (k_chip->sim_sdid &
2394 (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK | KINETIS_SDID_PROJECTID_MASK)) {
2395 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xZ:
2396 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX5 | KINETIS_SDID_PROJECTID_KE1xZ:
2397 /* KE1xZ: FTFE, 2kB sectors */
2398 k_chip->pflash_sector_size = 2<<10;
2399 k_chip->nvm_sector_size = 2<<10;
2400 k_chip->max_flash_prog_size = 1<<9;
2402 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2403 k_chip->cache_type = KINETIS_CACHE_L;
2406 snprintf(name, sizeof(name), "MKE%u%uZ%%s%u",
2407 familyid, subfamid, cpu_mhz / 10);
2410 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xF:
2411 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX6 | KINETIS_SDID_PROJECTID_KE1xF:
2412 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX8 | KINETIS_SDID_PROJECTID_KE1xF:
2413 /* KE1xF: FTFE, 4kB sectors */
2414 k_chip->pflash_sector_size = 4<<10;
2415 k_chip->nvm_sector_size = 2<<10;
2416 k_chip->max_flash_prog_size = 1<<10;
2418 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2419 k_chip->cache_type = KINETIS_CACHE_MSCM;
2422 snprintf(name, sizeof(name), "MKE%u%uF%%s%u",
2423 familyid, subfamid, cpu_mhz / 10);
2427 LOG_ERROR("Unsupported KE FAMILYID SUBFAMID");
2432 LOG_ERROR("Unsupported K-series");
2436 if (k_chip->pflash_sector_size == 0) {
2437 LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32, k_chip->sim_sdid);
2438 return ERROR_FLASH_OPER_UNSUPPORTED;
2441 result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &k_chip->sim_fcfg1);
2442 if (result != ERROR_OK)
2445 result = target_read_u32(target, k_chip->sim_base + SIM_FCFG2_OFFSET, &k_chip->sim_fcfg2);
2446 if (result != ERROR_OK)
2449 LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, k_chip->sim_sdid,
2450 k_chip->sim_fcfg1, k_chip->sim_fcfg2);
2452 fcfg1_nvmsize = (uint8_t)((k_chip->sim_fcfg1 >> 28) & 0x0f);
2453 fcfg1_pfsize = (uint8_t)((k_chip->sim_fcfg1 >> 24) & 0x0f);
2454 fcfg1_eesize = (uint8_t)((k_chip->sim_fcfg1 >> 16) & 0x0f);
2455 fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
2457 fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
2458 k_chip->fcfg2_maxaddr0_shifted = ((k_chip->sim_fcfg2 >> 24) & 0x7f) << maxaddr_shift;
2459 k_chip->fcfg2_maxaddr1_shifted = ((k_chip->sim_fcfg2 >> 16) & 0x7f) << maxaddr_shift;
2461 if (num_blocks == 0)
2462 num_blocks = k_chip->fcfg2_maxaddr1_shifted ? 2 : 1;
2463 else if (k_chip->fcfg2_maxaddr1_shifted == 0 && num_blocks >= 2 && fcfg2_pflsh) {
2464 /* fcfg2_maxaddr1 may be zero due to partitioning whole NVM as EEPROM backup
2465 * Do not adjust block count in this case! */
2467 LOG_WARNING("MAXADDR1 is zero, number of flash banks adjusted to 1");
2468 } else if (k_chip->fcfg2_maxaddr1_shifted != 0 && num_blocks == 1) {
2470 LOG_WARNING("MAXADDR1 is non zero, number of flash banks adjusted to 2");
2473 /* when the PFLSH bit is set, there is no FlexNVM/FlexRAM */
2475 switch (fcfg1_nvmsize) {
2481 k_chip->nvm_size = 1 << (14 + (fcfg1_nvmsize >> 1));
2484 if (k_chip->pflash_sector_size >= 4<<10)
2485 k_chip->nvm_size = 512<<10;
2488 k_chip->nvm_size = 256<<10;
2491 k_chip->nvm_size = 0;
2495 switch (fcfg1_eesize) {
2506 ee_size = (16 << (10 - fcfg1_eesize));
2513 switch (fcfg1_depart) {
2520 k_chip->dflash_size = k_chip->nvm_size - (4096 << fcfg1_depart);
2524 k_chip->dflash_size = 0;
2531 k_chip->dflash_size = 4096 << (fcfg1_depart & 0x7);
2534 k_chip->dflash_size = k_chip->nvm_size;
2539 switch (fcfg1_pfsize) {
2541 k_chip->pflash_size = 8192;
2550 k_chip->pflash_size = 1 << (14 + (fcfg1_pfsize >> 1));
2553 /* a peculiar case: Freescale states different sizes for 0xf
2554 * KL03P24M48SF0RM 32 KB .... duplicate of code 0x3
2555 * K02P64M100SFARM 128 KB ... duplicate of code 0x7
2556 * K22P121M120SF8RM 256 KB ... duplicate of code 0x9
2557 * K22P121M120SF7RM 512 KB ... duplicate of code 0xb
2558 * K22P100M120SF5RM 1024 KB ... duplicate of code 0xd
2559 * K26P169M180SF5RM 2048 KB ... the only unique value
2560 * fcfg2_maxaddr0 seems to be the only clue to pflash_size
2561 * Checking fcfg2_maxaddr0 in bank probe is pointless then
2564 k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks;
2566 k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks / 2;
2567 if (k_chip->pflash_size != 2048<<10)
2568 LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %u KB", k_chip->pflash_size>>10);
2572 k_chip->pflash_size = 0;
2576 if (k_chip->flash_support & FS_PROGRAM_SECTOR && k_chip->max_flash_prog_size == 0) {
2577 k_chip->max_flash_prog_size = k_chip->pflash_sector_size;
2578 /* Program section size is equal to sector size by default */
2582 k_chip->num_pflash_blocks = num_blocks;
2583 k_chip->num_nvm_blocks = 0;
2585 k_chip->num_pflash_blocks = (num_blocks + 1) / 2;
2586 k_chip->num_nvm_blocks = num_blocks - k_chip->num_pflash_blocks;
2589 if (use_nvm_marking) {
2590 nvm_marking[0] = k_chip->num_nvm_blocks ? 'X' : 'N';
2591 nvm_marking[1] = '\0';
2593 nvm_marking[0] = '\0';
2595 pflash_size_k = k_chip->pflash_size / 1024;
2596 pflash_size_m = pflash_size_k / 1024;
2598 snprintf(flash_marking, sizeof(flash_marking), "%s%" PRIu32 "M0xxx", nvm_marking, pflash_size_m);
2600 snprintf(flash_marking, sizeof(flash_marking), "%s%" PRIu32 "xxx", nvm_marking, pflash_size_k);
2602 snprintf(k_chip->name, sizeof(k_chip->name), name, flash_marking);
2603 LOG_INFO("Kinetis %s detected: %u flash blocks", k_chip->name, num_blocks);
2604 LOG_INFO("%u PFlash banks: %" PRIu32 "k total", k_chip->num_pflash_blocks, pflash_size_k);
2605 if (k_chip->num_nvm_blocks) {
2606 nvm_size_k = k_chip->nvm_size / 1024;
2607 dflash_size_k = k_chip->dflash_size / 1024;
2608 LOG_INFO("%u FlexNVM banks: %" PRIu32 "k total, %" PRIu32 "k available as data flash, %" PRIu32 "bytes FlexRAM",
2609 k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size);
2612 k_chip->probed = true;
2615 kinetis_create_missing_banks(k_chip);
2620 static int kinetis_probe(struct flash_bank *bank)
2623 uint8_t fcfg2_maxaddr0, fcfg2_pflsh, fcfg2_maxaddr1;
2624 unsigned num_blocks, first_nvm_bank;
2626 struct kinetis_flash_bank *k_bank = bank->driver_priv;
2627 struct kinetis_chip *k_chip;
2630 k_chip = k_bank->k_chip;
2632 k_bank->probed = false;
2634 if (!k_chip->probed) {
2635 result = kinetis_probe_chip(k_chip);
2636 if (result != ERROR_OK)
2640 num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
2641 first_nvm_bank = k_chip->num_pflash_blocks;
2643 if (k_bank->bank_number < k_chip->num_pflash_blocks) {
2644 /* pflash, banks start at address zero */
2645 k_bank->flash_class = FC_PFLASH;
2646 bank->size = (k_chip->pflash_size / k_chip->num_pflash_blocks);
2647 bank->base = k_chip->pflash_base + bank->size * k_bank->bank_number;
2648 k_bank->prog_base = 0x00000000 + bank->size * k_bank->bank_number;
2649 k_bank->sector_size = k_chip->pflash_sector_size;
2650 /* pflash is divided into 32 protection areas for
2651 * parts with more than 32K of PFlash. For parts with
2652 * less the protection unit is set to 1024 bytes */
2653 k_bank->protection_size = MAX(k_chip->pflash_size / 32, 1024);
2654 bank->num_prot_blocks = bank->size / k_bank->protection_size;
2655 k_bank->protection_block = bank->num_prot_blocks * k_bank->bank_number;
2657 size_k = bank->size / 1024;
2658 LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k PFlash, FTFx base 0x%08" PRIx32 ", sect %u",
2659 k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
2661 } else if (k_bank->bank_number < num_blocks) {
2662 /* nvm, banks start at address 0x10000000 */
2663 unsigned nvm_ord = k_bank->bank_number - first_nvm_bank;
2666 k_bank->flash_class = FC_FLEX_NVM;
2667 bank->size = k_chip->nvm_size / k_chip->num_nvm_blocks;
2668 bank->base = k_chip->nvm_base + bank->size * nvm_ord;
2669 k_bank->prog_base = 0x00800000 + bank->size * nvm_ord;
2670 k_bank->sector_size = k_chip->nvm_sector_size;
2671 if (k_chip->dflash_size == 0) {
2672 k_bank->protection_size = 0;
2675 for (i = k_chip->dflash_size; ~i & 1; i >>= 1)
2678 k_bank->protection_size = k_chip->dflash_size / 8; /* data flash size = 2^^n */
2680 k_bank->protection_size = k_chip->nvm_size / 8; /* TODO: verify on SF1, not documented in RM */
2682 bank->num_prot_blocks = 8 / k_chip->num_nvm_blocks;
2683 k_bank->protection_block = bank->num_prot_blocks * nvm_ord;
2685 /* EEPROM backup part of FlexNVM is not accessible, use dflash_size as a limit */
2686 if (k_chip->dflash_size > bank->size * nvm_ord)
2687 limit = k_chip->dflash_size - bank->size * nvm_ord;
2691 if (bank->size > limit) {
2693 LOG_DEBUG("FlexNVM bank %u limited to 0x%08" PRIx32 " due to active EEPROM backup",
2694 k_bank->bank_number, limit);
2697 size_k = bank->size / 1024;
2698 LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k FlexNVM, FTFx base 0x%08" PRIx32 ", sect %u",
2699 k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
2702 LOG_ERROR("Cannot determine parameters for bank %u, only %u banks on device",
2703 k_bank->bank_number, num_blocks);
2704 return ERROR_FLASH_BANK_INVALID;
2707 fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
2708 fcfg2_maxaddr0 = (uint8_t)((k_chip->sim_fcfg2 >> 24) & 0x7f);
2709 fcfg2_maxaddr1 = (uint8_t)((k_chip->sim_fcfg2 >> 16) & 0x7f);
2711 if (k_bank->bank_number == 0 && k_chip->fcfg2_maxaddr0_shifted != bank->size)
2712 LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
2713 " please report to OpenOCD mailing list", fcfg2_maxaddr0);
2716 if (k_bank->bank_number == 1 && k_chip->fcfg2_maxaddr1_shifted != bank->size)
2717 LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
2718 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
2720 if (k_bank->bank_number == first_nvm_bank
2721 && k_chip->fcfg2_maxaddr1_shifted != k_chip->dflash_size)
2722 LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed,"
2723 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
2726 if (bank->sectors) {
2727 free(bank->sectors);
2728 bank->sectors = NULL;
2730 if (bank->prot_blocks) {
2731 free(bank->prot_blocks);
2732 bank->prot_blocks = NULL;
2735 if (k_bank->sector_size == 0) {
2736 LOG_ERROR("Unknown sector size for bank %u", bank->bank_number);
2737 return ERROR_FLASH_BANK_INVALID;
2740 bank->num_sectors = bank->size / k_bank->sector_size;
2742 if (bank->num_sectors > 0) {
2743 /* FlexNVM bank can be used for EEPROM backup therefore zero sized */
2744 bank->sectors = alloc_block_array(0, k_bank->sector_size, bank->num_sectors);
2748 bank->prot_blocks = alloc_block_array(0, k_bank->protection_size, bank->num_prot_blocks);
2749 if (!bank->prot_blocks)
2753 bank->num_prot_blocks = 0;
2756 k_bank->probed = true;
2761 static int kinetis_auto_probe(struct flash_bank *bank)
2763 struct kinetis_flash_bank *k_bank = bank->driver_priv;
2765 if (k_bank && k_bank->probed)
2768 return kinetis_probe(bank);
2771 static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
2773 const char *bank_class_names[] = {
2774 "(ANY)", "PFlash", "FlexNVM", "FlexRAM"
2777 struct kinetis_flash_bank *k_bank = bank->driver_priv;
2778 struct kinetis_chip *k_chip = k_bank->k_chip;
2779 uint32_t size_k = bank->size / 1024;
2781 snprintf(buf, buf_size,
2782 "%s %s: %" PRIu32 "k %s bank %s at " TARGET_ADDR_FMT,
2783 bank->driver->name, k_chip->name,
2784 size_k, bank_class_names[k_bank->flash_class],
2785 bank->name, bank->base);
2790 static int kinetis_blank_check(struct flash_bank *bank)
2792 struct kinetis_flash_bank *k_bank = bank->driver_priv;
2793 struct kinetis_chip *k_chip = k_bank->k_chip;
2796 /* suprisingly blank check does not work in VLPR and HSRUN modes */
2797 result = kinetis_check_run_mode(k_chip);
2798 if (result != ERROR_OK)
2801 /* reset error flags */
2802 result = kinetis_ftfx_prepare(bank->target);
2803 if (result != ERROR_OK)
2806 if (k_bank->flash_class == FC_PFLASH || k_bank->flash_class == FC_FLEX_NVM) {
2807 bool block_dirty = true;
2808 bool use_block_cmd = !(k_chip->flash_support & FS_NO_CMD_BLOCKSTAT);
2811 if (use_block_cmd && k_bank->flash_class == FC_FLEX_NVM) {
2812 uint8_t fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
2813 /* block operation cannot be used on FlexNVM when EEPROM backup partition is set */
2814 if (fcfg1_depart != 0xf && fcfg1_depart != 0)
2815 use_block_cmd = false;
2818 if (use_block_cmd) {
2819 /* check if whole bank is blank */
2820 result = kinetis_ftfx_command(bank->target, FTFx_CMD_BLOCKSTAT, k_bank->prog_base,
2821 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
2823 if (result != ERROR_OK)
2824 kinetis_ftfx_clear_error(bank->target);
2825 else if ((ftfx_fstat & 0x01) == 0)
2826 block_dirty = false;
2830 /* the whole bank is not erased, check sector-by-sector */
2831 for (unsigned int i = 0; i < bank->num_sectors; i++) {
2833 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTSTAT,
2834 k_bank->prog_base + bank->sectors[i].offset,
2835 1, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
2837 if (result == ERROR_OK) {
2838 bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
2840 LOG_DEBUG("Ignoring errored PFlash sector blank-check");
2841 kinetis_ftfx_clear_error(bank->target);
2842 bank->sectors[i].is_erased = -1;
2846 /* the whole bank is erased, update all sectors */
2847 for (unsigned int i = 0; i < bank->num_sectors; i++)
2848 bank->sectors[i].is_erased = 1;
2851 LOG_WARNING("kinetis_blank_check not supported yet for FlexRAM");
2852 return ERROR_FLASH_OPERATION_FAILED;
2859 COMMAND_HANDLER(kinetis_nvm_partition)
2863 unsigned num_blocks, first_nvm_bank;
2864 unsigned long par, log2 = 0, ee1 = 0, ee2 = 0;
2865 enum { SHOW_INFO, DF_SIZE, EEBKP_SIZE } sz_type = SHOW_INFO;
2867 uint8_t load_flex_ram = 1;
2868 uint8_t ee_size_code = 0x3f;
2869 uint8_t flex_nvm_partition_code = 0;
2870 uint8_t ee_split = 3;
2871 struct target *target = get_current_target(CMD_CTX);
2872 struct kinetis_chip *k_chip;
2875 k_chip = kinetis_get_chip(target);
2877 if (CMD_ARGC >= 2) {
2878 if (strcmp(CMD_ARGV[0], "dataflash") == 0)
2880 else if (strcmp(CMD_ARGV[0], "eebkp") == 0)
2881 sz_type = EEBKP_SIZE;
2883 par = strtoul(CMD_ARGV[1], NULL, 10);
2884 while (par >> (log2 + 3))
2889 if (k_chip == NULL) {
2890 LOG_ERROR("Chip not probed.");
2893 result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &sim_fcfg1);
2894 if (result != ERROR_OK)
2897 flex_nvm_partition_code = (uint8_t)((sim_fcfg1 >> 8) & 0x0f);
2898 switch (flex_nvm_partition_code) {
2900 command_print(CMD, "No EEPROM backup, data flash only");
2908 command_print(CMD, "EEPROM backup %d KB", 4 << flex_nvm_partition_code);
2911 command_print(CMD, "No data flash, EEPROM backup only");
2919 command_print(CMD, "data flash %d KB", 4 << (flex_nvm_partition_code & 7));
2922 command_print(CMD, "No EEPROM backup, data flash only (DEPART not set)");
2925 command_print(CMD, "Unsupported EEPROM backup size code 0x%02" PRIx8, flex_nvm_partition_code);
2930 flex_nvm_partition_code = 0x8 | log2;
2934 flex_nvm_partition_code = log2;
2939 ee1 = ee2 = strtoul(CMD_ARGV[2], NULL, 10) / 2;
2940 else if (CMD_ARGC >= 4) {
2941 ee1 = strtoul(CMD_ARGV[2], NULL, 10);
2942 ee2 = strtoul(CMD_ARGV[3], NULL, 10);
2945 enable = ee1 + ee2 > 0;
2947 for (log2 = 2; ; log2++) {
2948 if (ee1 + ee2 == (16u << 10) >> log2)
2950 if (ee1 + ee2 > (16u << 10) >> log2 || log2 >= 9) {
2951 LOG_ERROR("Unsupported EEPROM size");
2952 return ERROR_FLASH_OPERATION_FAILED;
2958 else if (ee1 * 7 == ee2)
2960 else if (ee1 != ee2) {
2961 LOG_ERROR("Unsupported EEPROM sizes ratio");
2962 return ERROR_FLASH_OPERATION_FAILED;
2965 ee_size_code = log2 | ee_split << 4;
2969 COMMAND_PARSE_ON_OFF(CMD_ARGV[4], enable);
2973 LOG_INFO("DEPART 0x%" PRIx8 ", EEPROM size code 0x%" PRIx8,
2974 flex_nvm_partition_code, ee_size_code);
2976 result = kinetis_check_run_mode(k_chip);
2977 if (result != ERROR_OK)
2980 /* reset error flags */
2981 result = kinetis_ftfx_prepare(target);
2982 if (result != ERROR_OK)
2985 result = kinetis_ftfx_command(target, FTFx_CMD_PGMPART, load_flex_ram,
2986 ee_size_code, flex_nvm_partition_code, 0, 0,
2988 if (result != ERROR_OK)
2991 command_print(CMD, "FlexNVM partition set. Please reset MCU.");
2994 first_nvm_bank = k_chip->num_pflash_blocks;
2995 num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
2996 for (bank_idx = first_nvm_bank; bank_idx < num_blocks; bank_idx++)
2997 k_chip->banks[bank_idx].probed = false; /* re-probe before next use */
2998 k_chip->probed = false;
3001 command_print(CMD, "FlexNVM banks will be re-probed to set new data flash size.");
3005 COMMAND_HANDLER(kinetis_fcf_source_handler)
3008 return ERROR_COMMAND_SYNTAX_ERROR;
3010 if (CMD_ARGC == 1) {
3011 if (strcmp(CMD_ARGV[0], "write") == 0)
3012 allow_fcf_writes = true;
3013 else if (strcmp(CMD_ARGV[0], "protection") == 0)
3014 allow_fcf_writes = false;
3016 return ERROR_COMMAND_SYNTAX_ERROR;
3019 if (allow_fcf_writes) {
3020 command_print(CMD, "Arbitrary Flash Configuration Field writes enabled.");
3021 command_print(CMD, "Protection info writes to FCF disabled.");
3022 LOG_WARNING("BEWARE: incorrect flash configuration may permanently lock the device.");
3024 command_print(CMD, "Protection info writes to Flash Configuration Field enabled.");
3025 command_print(CMD, "Arbitrary FCF writes disabled. Mode safe from unwanted locking of the device.");
3031 COMMAND_HANDLER(kinetis_fopt_handler)
3034 return ERROR_COMMAND_SYNTAX_ERROR;
3036 if (CMD_ARGC == 1) {
3037 fcf_fopt = (uint8_t)strtoul(CMD_ARGV[0], NULL, 0);
3038 fcf_fopt_configured = true;
3040 command_print(CMD, "FCF_FOPT 0x%02" PRIx8, fcf_fopt);
3046 COMMAND_HANDLER(kinetis_create_banks_handler)
3049 return ERROR_COMMAND_SYNTAX_ERROR;
3051 create_banks = true;
3057 static const struct command_registration kinetis_security_command_handlers[] = {
3059 .name = "check_security",
3060 .mode = COMMAND_EXEC,
3061 .help = "Check status of device security lock",
3063 .handler = kinetis_check_flash_security_status,
3067 .mode = COMMAND_EXEC,
3068 .help = "Issue a halt via the MDM-AP",
3070 .handler = kinetis_mdm_halt,
3073 .name = "mass_erase",
3074 .mode = COMMAND_EXEC,
3075 .help = "Issue a complete flash erase via the MDM-AP",
3077 .handler = kinetis_mdm_mass_erase,
3081 .mode = COMMAND_EXEC,
3082 .help = "Issue a reset via the MDM-AP",
3084 .handler = kinetis_mdm_reset,
3086 COMMAND_REGISTRATION_DONE
3089 static const struct command_registration kinetis_exec_command_handlers[] = {
3092 .mode = COMMAND_ANY,
3093 .help = "MDM-AP command group",
3095 .chain = kinetis_security_command_handlers,
3098 .name = "disable_wdog",
3099 .mode = COMMAND_EXEC,
3100 .help = "Disable the watchdog timer",
3102 .handler = kinetis_disable_wdog_handler,
3105 .name = "nvm_partition",
3106 .mode = COMMAND_EXEC,
3107 .help = "Show/set data flash or EEPROM backup size in kilobytes,"
3108 " set two EEPROM sizes in bytes and FlexRAM loading during reset",
3109 .usage = "('info'|'dataflash' size|'eebkp' size) [eesize1 eesize2] ['on'|'off']",
3110 .handler = kinetis_nvm_partition,
3113 .name = "fcf_source",
3114 .mode = COMMAND_EXEC,
3115 .help = "Use protection as a source for Flash Configuration Field or allow writing arbitrary values to the FCF"
3116 " Mode 'protection' is safe from unwanted locking of the device.",
3117 .usage = "['protection'|'write']",
3118 .handler = kinetis_fcf_source_handler,
3122 .mode = COMMAND_EXEC,
3123 .help = "FCF_FOPT value source in 'kinetis fcf_source protection' mode",
3125 .handler = kinetis_fopt_handler,
3128 .name = "create_banks",
3129 .mode = COMMAND_CONFIG,
3130 .help = "Driver creates additional banks if device with two/four flash blocks is probed",
3131 .handler = kinetis_create_banks_handler,
3134 COMMAND_REGISTRATION_DONE
3137 static const struct command_registration kinetis_command_handler[] = {
3140 .mode = COMMAND_ANY,
3141 .help = "Kinetis flash controller commands",
3143 .chain = kinetis_exec_command_handlers,
3145 COMMAND_REGISTRATION_DONE
3150 const struct flash_driver kinetis_flash = {
3152 .commands = kinetis_command_handler,
3153 .flash_bank_command = kinetis_flash_bank_command,
3154 .erase = kinetis_erase,
3155 .protect = kinetis_protect,
3156 .write = kinetis_write,
3157 .read = default_flash_read,
3158 .probe = kinetis_probe,
3159 .auto_probe = kinetis_auto_probe,
3160 .erase_check = kinetis_blank_check,
3161 .protect_check = kinetis_protect_check,
3162 .info = kinetis_info,
3163 .free_driver_priv = kinetis_free_driver_priv,