1 /***************************************************************************
2 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
3 * Modified by Megan Wachs <megan@sifive.com> from the original stmsmi.c *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
19 /* The Freedom E SPI controller is a SPI bus controller
20 * specifically designed for SPI Flash Memories on Freedom E platforms.
22 * Two working modes are available:
23 * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
24 * on the bus. Writes are only possible in this mode.
25 * - HW mode: Memory content is directly
26 * accessible in CPU memory space. CPU can read and execute memory content.
30 * To have flash memory mapped in CPU memory space, the controller
31 * must have "HW mode" enabled.
32 * 1) The command "reset init" has to initialize the controller and put
33 * it in HW mode (this is actually the default out of reset for Freedom E systems).
34 * 2) every command in this file have to return to prompt in HW mode. */
42 #include <jtag/jtag.h>
43 #include <helper/time_support.h>
44 #include <target/algorithm.h>
45 #include "target/riscv/riscv.h"
47 /* Register offsets */
49 #define FESPI_REG_SCKDIV 0x00
50 #define FESPI_REG_SCKMODE 0x04
51 #define FESPI_REG_CSID 0x10
52 #define FESPI_REG_CSDEF 0x14
53 #define FESPI_REG_CSMODE 0x18
55 #define FESPI_REG_DCSSCK 0x28
56 #define FESPI_REG_DSCKCS 0x2a
57 #define FESPI_REG_DINTERCS 0x2c
58 #define FESPI_REG_DINTERXFR 0x2e
60 #define FESPI_REG_FMT 0x40
61 #define FESPI_REG_TXFIFO 0x48
62 #define FESPI_REG_RXFIFO 0x4c
63 #define FESPI_REG_TXCTRL 0x50
64 #define FESPI_REG_RXCTRL 0x54
66 #define FESPI_REG_FCTRL 0x60
67 #define FESPI_REG_FFMT 0x64
69 #define FESPI_REG_IE 0x70
70 #define FESPI_REG_IP 0x74
74 #define FESPI_SCK_POL 0x1
75 #define FESPI_SCK_PHA 0x2
77 #define FESPI_FMT_PROTO(x) ((x) & 0x3)
78 #define FESPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
79 #define FESPI_FMT_DIR(x) (((x) & 0x1) << 3)
80 #define FESPI_FMT_LEN(x) (((x) & 0xf) << 16)
83 #define FESPI_TXWM(x) ((x) & 0xffff)
85 #define FESPI_RXWM(x) ((x) & 0xffff)
87 #define FESPI_IP_TXWM 0x1
88 #define FESPI_IP_RXWM 0x2
90 #define FESPI_FCTRL_EN 0x1
92 #define FESPI_INSN_CMD_EN 0x1
93 #define FESPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
94 #define FESPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
95 #define FESPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
96 #define FESPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
97 #define FESPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
98 #define FESPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
99 #define FESPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
103 #define FESPI_CSMODE_AUTO 0
104 #define FESPI_CSMODE_HOLD 2
105 #define FESPI_CSMODE_OFF 3
107 #define FESPI_DIR_RX 0
108 #define FESPI_DIR_TX 1
110 #define FESPI_PROTO_S 0
111 #define FESPI_PROTO_D 1
112 #define FESPI_PROTO_Q 2
114 #define FESPI_ENDIAN_MSB 0
115 #define FESPI_ENDIAN_LSB 1
119 #define FESPI_CMD_TIMEOUT (100)
120 #define FESPI_PROBE_TIMEOUT (100)
121 #define FESPI_MAX_TIMEOUT (3000)
124 struct fespi_flash_bank {
126 target_addr_t ctrl_base;
127 const struct flash_device *dev;
130 struct fespi_target {
136 /* TODO !!! What is the right naming convention here? */
137 static const struct fespi_target target_devices[] = {
138 /* name, tap_idcode, ctrl_base */
139 { "Freedom E310-G000 SPI Flash", 0x10e31913 , 0x10014000 },
140 { "Freedom E310-G002 SPI Flash", 0x20000913 , 0x10014000 },
144 FLASH_BANK_COMMAND_HANDLER(fespi_flash_bank_command)
146 struct fespi_flash_bank *fespi_info;
148 LOG_DEBUG("%s", __func__);
151 return ERROR_COMMAND_SYNTAX_ERROR;
153 fespi_info = malloc(sizeof(struct fespi_flash_bank));
154 if (fespi_info == NULL) {
155 LOG_ERROR("not enough memory");
159 bank->driver_priv = fespi_info;
160 fespi_info->probed = 0;
161 fespi_info->ctrl_base = 0;
163 COMMAND_PARSE_ADDRESS(CMD_ARGV[6], fespi_info->ctrl_base);
164 LOG_DEBUG("ASSUMING FESPI device at ctrl_base = " TARGET_ADDR_FMT,
165 fespi_info->ctrl_base);
171 static int fespi_read_reg(struct flash_bank *bank, uint32_t *value, target_addr_t address)
173 struct target *target = bank->target;
174 struct fespi_flash_bank *fespi_info = bank->driver_priv;
176 int result = target_read_u32(target, fespi_info->ctrl_base + address, value);
177 if (result != ERROR_OK) {
178 LOG_ERROR("fespi_read_reg() error at " TARGET_ADDR_FMT,
179 fespi_info->ctrl_base + address);
185 static int fespi_write_reg(struct flash_bank *bank, target_addr_t address, uint32_t value)
187 struct target *target = bank->target;
188 struct fespi_flash_bank *fespi_info = bank->driver_priv;
190 int result = target_write_u32(target, fespi_info->ctrl_base + address, value);
191 if (result != ERROR_OK) {
192 LOG_ERROR("fespi_write_reg() error writing 0x%x to " TARGET_ADDR_FMT,
193 value, fespi_info->ctrl_base + address);
199 static int fespi_disable_hw_mode(struct flash_bank *bank)
202 if (fespi_read_reg(bank, &fctrl, FESPI_REG_FCTRL) != ERROR_OK)
204 return fespi_write_reg(bank, FESPI_REG_FCTRL, fctrl & ~FESPI_FCTRL_EN);
207 static int fespi_enable_hw_mode(struct flash_bank *bank)
210 if (fespi_read_reg(bank, &fctrl, FESPI_REG_FCTRL) != ERROR_OK)
212 return fespi_write_reg(bank, FESPI_REG_FCTRL, fctrl | FESPI_FCTRL_EN);
215 static int fespi_set_dir(struct flash_bank *bank, bool dir)
218 if (fespi_read_reg(bank, &fmt, FESPI_REG_FMT) != ERROR_OK)
221 return fespi_write_reg(bank, FESPI_REG_FMT,
222 (fmt & ~(FESPI_FMT_DIR(0xFFFFFFFF))) | FESPI_FMT_DIR(dir));
225 static int fespi_txwm_wait(struct flash_bank *bank)
227 int64_t start = timeval_ms();
231 if (fespi_read_reg(bank, &ip, FESPI_REG_IP) != ERROR_OK)
233 if (ip & FESPI_IP_TXWM)
235 int64_t now = timeval_ms();
236 if (now - start > 1000) {
237 LOG_ERROR("ip.txwm didn't get set.");
238 return ERROR_TARGET_TIMEOUT;
245 static int fespi_tx(struct flash_bank *bank, uint8_t in)
247 int64_t start = timeval_ms();
251 if (fespi_read_reg(bank, &txfifo, FESPI_REG_TXFIFO) != ERROR_OK)
255 int64_t now = timeval_ms();
256 if (now - start > 1000) {
257 LOG_ERROR("txfifo stayed negative.");
258 return ERROR_TARGET_TIMEOUT;
262 return fespi_write_reg(bank, FESPI_REG_TXFIFO, in);
265 static int fespi_rx(struct flash_bank *bank, uint8_t *out)
267 int64_t start = timeval_ms();
271 if (fespi_read_reg(bank, &value, FESPI_REG_RXFIFO) != ERROR_OK)
275 int64_t now = timeval_ms();
276 if (now - start > 1000) {
277 LOG_ERROR("rxfifo didn't go positive (value=0x%x).", value);
278 return ERROR_TARGET_TIMEOUT;
288 /* TODO!!! Why don't we need to call this after writing? */
289 static int fespi_wip(struct flash_bank *bank, int timeout)
293 fespi_set_dir(bank, FESPI_DIR_RX);
295 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
297 endtime = timeval_ms() + timeout;
299 fespi_tx(bank, SPIFLASH_READ_STATUS);
300 if (fespi_rx(bank, NULL) != ERROR_OK)
308 if (fespi_rx(bank, &rx) != ERROR_OK)
310 if ((rx & SPIFLASH_BSY_BIT) == 0) {
311 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
313 fespi_set_dir(bank, FESPI_DIR_TX);
316 } while (timeval_ms() < endtime);
318 LOG_ERROR("timeout");
322 static int fespi_erase_sector(struct flash_bank *bank, int sector)
324 struct fespi_flash_bank *fespi_info = bank->driver_priv;
327 retval = fespi_tx(bank, SPIFLASH_WRITE_ENABLE);
328 if (retval != ERROR_OK)
330 retval = fespi_txwm_wait(bank);
331 if (retval != ERROR_OK)
334 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
336 retval = fespi_tx(bank, fespi_info->dev->erase_cmd);
337 if (retval != ERROR_OK)
339 sector = bank->sectors[sector].offset;
340 retval = fespi_tx(bank, sector >> 16);
341 if (retval != ERROR_OK)
343 retval = fespi_tx(bank, sector >> 8);
344 if (retval != ERROR_OK)
346 retval = fespi_tx(bank, sector);
347 if (retval != ERROR_OK)
349 retval = fespi_txwm_wait(bank);
350 if (retval != ERROR_OK)
352 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
355 retval = fespi_wip(bank, FESPI_MAX_TIMEOUT);
356 if (retval != ERROR_OK)
362 static int fespi_erase(struct flash_bank *bank, int first, int last)
364 struct target *target = bank->target;
365 struct fespi_flash_bank *fespi_info = bank->driver_priv;
366 int retval = ERROR_OK;
369 LOG_DEBUG("%s: from sector %d to sector %d", __func__, first, last);
371 if (target->state != TARGET_HALTED) {
372 LOG_ERROR("Target not halted");
373 return ERROR_TARGET_NOT_HALTED;
376 if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
377 LOG_ERROR("Flash sector invalid");
378 return ERROR_FLASH_SECTOR_INVALID;
381 if (!(fespi_info->probed)) {
382 LOG_ERROR("Flash bank not probed");
383 return ERROR_FLASH_BANK_NOT_PROBED;
386 for (sector = first; sector <= last; sector++) {
387 if (bank->sectors[sector].is_protected) {
388 LOG_ERROR("Flash sector %d protected", sector);
393 if (fespi_info->dev->erase_cmd == 0x00)
394 return ERROR_FLASH_OPER_UNSUPPORTED;
396 if (fespi_write_reg(bank, FESPI_REG_TXCTRL, FESPI_TXWM(1)) != ERROR_OK)
398 retval = fespi_txwm_wait(bank);
399 if (retval != ERROR_OK) {
400 LOG_ERROR("WM Didn't go high before attempting.");
404 /* Disable Hardware accesses*/
405 if (fespi_disable_hw_mode(bank) != ERROR_OK)
409 retval = fespi_wip(bank, FESPI_PROBE_TIMEOUT);
410 if (retval != ERROR_OK)
413 for (sector = first; sector <= last; sector++) {
414 retval = fespi_erase_sector(bank, sector);
415 if (retval != ERROR_OK)
420 /* Switch to HW mode before return to prompt */
422 if (fespi_enable_hw_mode(bank) != ERROR_OK)
427 static int fespi_protect(struct flash_bank *bank, int set,
432 for (sector = first; sector <= last; sector++)
433 bank->sectors[sector].is_protected = set;
437 static int slow_fespi_write_buffer(struct flash_bank *bank,
438 const uint8_t *buffer, uint32_t offset, uint32_t len)
442 if (offset & 0xFF000000) {
443 LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%x",
448 /* TODO!!! assert that len < page size */
450 fespi_tx(bank, SPIFLASH_WRITE_ENABLE);
451 fespi_txwm_wait(bank);
453 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
456 fespi_tx(bank, SPIFLASH_PAGE_PROGRAM);
458 fespi_tx(bank, offset >> 16);
459 fespi_tx(bank, offset >> 8);
460 fespi_tx(bank, offset);
462 for (ii = 0; ii < len; ii++)
463 fespi_tx(bank, buffer[ii]);
465 fespi_txwm_wait(bank);
467 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
475 static const uint8_t algorithm_bin[] = {
476 #include "../../../contrib/loaders/flash/fespi/fespi.inc"
480 #define STEP_TXWM_WAIT 12
481 #define STEP_WRITE_REG 16
482 #define STEP_WIP_WAIT 20
483 #define STEP_SET_DIR 24
484 #define STEP_NOP 0xff
486 struct algorithm_steps {
492 static struct algorithm_steps *as_new(void)
494 struct algorithm_steps *as = calloc(1, sizeof(struct algorithm_steps));
496 as->steps = malloc(as->size * sizeof(as->steps[0]));
500 static struct algorithm_steps *as_delete(struct algorithm_steps *as)
502 for (unsigned step = 0; step < as->used; step++) {
503 free(as->steps[step]);
504 as->steps[step] = NULL;
511 static int as_empty(struct algorithm_steps *as)
513 for (unsigned s = 0; s < as->used; s++) {
514 if (as->steps[s][0] != STEP_NOP)
520 /* Return size of compiled program. */
521 static unsigned as_compile(struct algorithm_steps *as, uint8_t *target,
522 unsigned target_size)
525 bool finish_early = false;
526 for (unsigned s = 0; s < as->used && !finish_early; s++) {
527 unsigned bytes_left = target_size - offset;
528 switch (as->steps[s][0]) {
533 unsigned size = as->steps[s][1];
534 if (size + 3 > bytes_left) {
538 memcpy(target + offset, as->steps[s], size + 2);
543 if (4 > bytes_left) {
547 memcpy(target + offset, as->steps[s], 3);
551 if (3 > bytes_left) {
555 memcpy(target + offset, as->steps[s], 2);
560 if (2 > bytes_left) {
564 memcpy(target + offset, as->steps[s], 1);
571 as->steps[s][0] = STEP_NOP;
573 assert(offset + 1 <= target_size);
574 target[offset++] = STEP_EXIT;
576 LOG_DEBUG("%d-byte program:", offset);
577 for (unsigned i = 0; i < offset;) {
579 for (unsigned x = 0; i < offset && x < 16; x++, i++)
580 sprintf(buf + x*3, "%02x ", target[i]);
581 LOG_DEBUG("%s", buf);
587 static void as_add_step(struct algorithm_steps *as, uint8_t *step)
589 if (as->used == as->size) {
591 as->steps = realloc(as->steps, sizeof(as->steps[0]) * as->size);
592 LOG_DEBUG("Increased size to 0x%x", as->size);
594 as->steps[as->used] = step;
598 static void as_add_tx(struct algorithm_steps *as, unsigned count, const uint8_t *data)
600 LOG_DEBUG("count=%d", count);
602 unsigned step_count = MIN(count, 255);
603 uint8_t *step = malloc(step_count + 2);
605 step[1] = step_count;
606 memcpy(step + 2, data, step_count);
607 as_add_step(as, step);
613 static void as_add_tx1(struct algorithm_steps *as, uint8_t byte)
617 as_add_tx(as, 1, data);
620 static void as_add_write_reg(struct algorithm_steps *as, uint8_t offset, uint8_t data)
622 uint8_t *step = malloc(3);
623 step[0] = STEP_WRITE_REG;
626 as_add_step(as, step);
629 static void as_add_txwm_wait(struct algorithm_steps *as)
631 uint8_t *step = malloc(1);
632 step[0] = STEP_TXWM_WAIT;
633 as_add_step(as, step);
636 static void as_add_wip_wait(struct algorithm_steps *as)
638 uint8_t *step = malloc(1);
639 step[0] = STEP_WIP_WAIT;
640 as_add_step(as, step);
643 static void as_add_set_dir(struct algorithm_steps *as, bool dir)
645 uint8_t *step = malloc(2);
646 step[0] = STEP_SET_DIR;
647 step[1] = FESPI_FMT_DIR(dir);
648 as_add_step(as, step);
651 /* This should write something less than or equal to a page.*/
652 static int steps_add_buffer_write(struct algorithm_steps *as,
653 const uint8_t *buffer, uint32_t chip_offset, uint32_t len)
655 if (chip_offset & 0xFF000000) {
656 LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%x",
661 as_add_tx1(as, SPIFLASH_WRITE_ENABLE);
662 as_add_txwm_wait(as);
663 as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
666 SPIFLASH_PAGE_PROGRAM,
671 as_add_tx(as, sizeof(setup), setup);
673 as_add_tx(as, len, buffer);
674 as_add_txwm_wait(as);
675 as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
678 as_add_set_dir(as, FESPI_DIR_RX);
679 as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
681 as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
682 as_add_set_dir(as, FESPI_DIR_TX);
687 static int steps_execute(struct algorithm_steps *as,
688 struct flash_bank *bank, struct working_area *algorithm_wa,
689 struct working_area *data_wa)
691 struct target *target = bank->target;
692 struct fespi_flash_bank *fespi_info = bank->driver_priv;
693 uint32_t ctrl_base = fespi_info->ctrl_base;
694 int xlen = riscv_xlen(target);
696 struct reg_param reg_params[2];
697 init_reg_param(®_params[0], "a0", xlen, PARAM_OUT);
698 init_reg_param(®_params[1], "a1", xlen, PARAM_OUT);
699 buf_set_u64(reg_params[0].value, 0, xlen, ctrl_base);
700 buf_set_u64(reg_params[1].value, 0, xlen, data_wa->address);
702 int retval = ERROR_OK;
703 while (!as_empty(as)) {
705 uint8_t *data_buf = malloc(data_wa->size);
706 unsigned bytes = as_compile(as, data_buf, data_wa->size);
707 retval = target_write_buffer(target, data_wa->address, bytes,
710 if (retval != ERROR_OK) {
711 LOG_ERROR("Failed to write data to " TARGET_ADDR_FMT ": %d",
712 data_wa->address, retval);
716 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
717 algorithm_wa->address, algorithm_wa->address + 4,
719 if (retval != ERROR_OK) {
720 LOG_ERROR("Failed to execute algorithm at " TARGET_ADDR_FMT ": %d",
721 algorithm_wa->address, retval);
727 destroy_reg_param(®_params[1]);
728 destroy_reg_param(®_params[0]);
732 static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
733 uint32_t offset, uint32_t count)
735 struct target *target = bank->target;
736 struct fespi_flash_bank *fespi_info = bank->driver_priv;
737 uint32_t cur_count, page_size, page_offset;
739 int retval = ERROR_OK;
741 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
742 __func__, offset, count);
744 if (target->state != TARGET_HALTED) {
745 LOG_ERROR("Target not halted");
746 return ERROR_TARGET_NOT_HALTED;
749 if (offset + count > fespi_info->dev->size_in_bytes) {
750 LOG_WARNING("Write past end of flash. Extra data discarded.");
751 count = fespi_info->dev->size_in_bytes - offset;
754 /* Check sector protection */
755 for (sector = 0; sector < bank->num_sectors; sector++) {
756 /* Start offset in or before this sector? */
757 /* End offset in or behind this sector? */
759 (bank->sectors[sector].offset + bank->sectors[sector].size))
760 && ((offset + count - 1) >= bank->sectors[sector].offset)
761 && bank->sectors[sector].is_protected) {
762 LOG_ERROR("Flash sector %d protected", sector);
767 struct working_area *algorithm_wa;
768 if (target_alloc_working_area(target, sizeof(algorithm_bin),
769 &algorithm_wa) != ERROR_OK) {
770 LOG_WARNING("Couldn't allocate %zd-byte working area.",
771 sizeof(algorithm_bin));
774 retval = target_write_buffer(target, algorithm_wa->address,
775 sizeof(algorithm_bin), algorithm_bin);
776 if (retval != ERROR_OK) {
777 LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
778 algorithm_wa->address, retval);
779 target_free_working_area(target, algorithm_wa);
784 struct working_area *data_wa = NULL;
785 unsigned data_wa_size = 2 * count;
787 if (data_wa_size < 128) {
788 LOG_WARNING("Couldn't allocate data working area.");
789 target_free_working_area(target, algorithm_wa);
792 if (target_alloc_working_area_try(target, data_wa_size, &data_wa) ==
800 /* If no valid page_size, use reasonable default. */
801 page_size = fespi_info->dev->pagesize ?
802 fespi_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
804 fespi_txwm_wait(bank);
806 /* Disable Hardware accesses*/
807 if (fespi_disable_hw_mode(bank) != ERROR_OK)
810 struct algorithm_steps *as = as_new();
813 retval = fespi_wip(bank, FESPI_PROBE_TIMEOUT);
814 if (retval != ERROR_OK)
817 page_offset = offset % page_size;
818 /* central part, aligned words */
820 /* clip block at page boundary */
821 if (page_offset + count > page_size)
822 cur_count = page_size - page_offset;
827 retval = steps_add_buffer_write(as, buffer, offset, cur_count);
829 retval = slow_fespi_write_buffer(bank, buffer, offset, cur_count);
830 if (retval != ERROR_OK)
840 retval = steps_execute(as, bank, algorithm_wa, data_wa);
844 target_free_working_area(target, data_wa);
845 target_free_working_area(target, algorithm_wa);
850 /* Switch to HW mode before return to prompt */
851 if (fespi_enable_hw_mode(bank) != ERROR_OK)
856 /* Return ID of flash device */
857 /* On exit, SW mode is kept */
858 static int fespi_read_flash_id(struct flash_bank *bank, uint32_t *id)
860 struct target *target = bank->target;
863 if (target->state != TARGET_HALTED) {
864 LOG_ERROR("Target not halted");
865 return ERROR_TARGET_NOT_HALTED;
868 fespi_txwm_wait(bank);
871 retval = fespi_wip(bank, FESPI_PROBE_TIMEOUT);
872 if (retval != ERROR_OK)
875 fespi_set_dir(bank, FESPI_DIR_RX);
877 /* Send SPI command "read ID" */
878 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
881 fespi_tx(bank, SPIFLASH_READ_ID);
882 /* Send dummy bytes to actually read the ID.*/
887 /* read ID from Receive Register */
889 if (fespi_rx(bank, NULL) != ERROR_OK)
892 if (fespi_rx(bank, &rx) != ERROR_OK)
895 if (fespi_rx(bank, &rx) != ERROR_OK)
898 if (fespi_rx(bank, &rx) != ERROR_OK)
902 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
905 fespi_set_dir(bank, FESPI_DIR_TX);
910 static int fespi_probe(struct flash_bank *bank)
912 struct target *target = bank->target;
913 struct fespi_flash_bank *fespi_info = bank->driver_priv;
914 struct flash_sector *sectors;
915 uint32_t id = 0; /* silence uninitialized warning */
916 const struct fespi_target *target_device;
920 if (fespi_info->probed)
922 fespi_info->probed = 0;
924 if (fespi_info->ctrl_base == 0) {
925 for (target_device = target_devices ; target_device->name ; ++target_device)
926 if (target_device->tap_idcode == target->tap->idcode)
929 if (!target_device->name) {
930 LOG_ERROR("Device ID 0x%" PRIx32 " is not known as FESPI capable",
931 target->tap->idcode);
935 fespi_info->ctrl_base = target_device->ctrl_base;
937 LOG_DEBUG("Valid FESPI on device %s at address " TARGET_ADDR_FMT,
938 target_device->name, bank->base);
941 LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
942 " with ctrl at " TARGET_ADDR_FMT, fespi_info->ctrl_base,
946 /* read and decode flash ID; returns in SW mode */
947 if (fespi_write_reg(bank, FESPI_REG_TXCTRL, FESPI_TXWM(1)) != ERROR_OK)
949 fespi_set_dir(bank, FESPI_DIR_TX);
951 /* Disable Hardware accesses*/
952 if (fespi_disable_hw_mode(bank) != ERROR_OK)
955 retval = fespi_read_flash_id(bank, &id);
957 if (fespi_enable_hw_mode(bank) != ERROR_OK)
959 if (retval != ERROR_OK)
962 fespi_info->dev = NULL;
963 for (const struct flash_device *p = flash_devices; p->name ; p++)
964 if (p->device_id == id) {
969 if (!fespi_info->dev) {
970 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
974 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
975 fespi_info->dev->name, fespi_info->dev->device_id);
977 /* Set correct size value */
978 bank->size = fespi_info->dev->size_in_bytes;
980 if (bank->size <= (1UL << 16))
981 LOG_WARNING("device needs 2-byte addresses - not implemented");
982 if (bank->size > (1UL << 24))
983 LOG_WARNING("device needs paging or 4-byte addresses - not implemented");
985 /* if no sectors, treat whole bank as single sector */
986 sectorsize = fespi_info->dev->sectorsize ?
987 fespi_info->dev->sectorsize : fespi_info->dev->size_in_bytes;
989 /* create and fill sectors array */
990 bank->num_sectors = fespi_info->dev->size_in_bytes / sectorsize;
991 sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
992 if (sectors == NULL) {
993 LOG_ERROR("not enough memory");
997 for (int sector = 0; sector < bank->num_sectors; sector++) {
998 sectors[sector].offset = sector * sectorsize;
999 sectors[sector].size = sectorsize;
1000 sectors[sector].is_erased = -1;
1001 sectors[sector].is_protected = 0;
1004 bank->sectors = sectors;
1005 fespi_info->probed = 1;
1009 static int fespi_auto_probe(struct flash_bank *bank)
1011 struct fespi_flash_bank *fespi_info = bank->driver_priv;
1012 if (fespi_info->probed)
1014 return fespi_probe(bank);
1017 static int fespi_protect_check(struct flash_bank *bank)
1019 /* Nothing to do. Protection is only handled in SW. */
1023 static int get_fespi_info(struct flash_bank *bank, char *buf, int buf_size)
1025 struct fespi_flash_bank *fespi_info = bank->driver_priv;
1027 if (!(fespi_info->probed)) {
1028 snprintf(buf, buf_size,
1029 "\nFESPI flash bank not probed yet\n");
1033 snprintf(buf, buf_size, "\nFESPI flash information:\n"
1034 " Device \'%s\' (ID 0x%08" PRIx32 ")\n",
1035 fespi_info->dev->name, fespi_info->dev->device_id);
1040 const struct flash_driver fespi_flash = {
1042 .flash_bank_command = fespi_flash_bank_command,
1043 .erase = fespi_erase,
1044 .protect = fespi_protect,
1045 .write = fespi_write,
1046 .read = default_flash_read,
1047 .probe = fespi_probe,
1048 .auto_probe = fespi_auto_probe,
1049 .erase_check = default_flash_blank_check,
1050 .protect_check = fespi_protect_check,
1051 .info = get_fespi_info,
1052 .free_driver_priv = default_flash_free_driver_priv