1 /***************************************************************************
2 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
3 * Modified by Megan Wachs <megan@sifive.com> from the original stmsmi.c *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
19 /* The Freedom E SPI controller is a SPI bus controller
20 * specifically designed for SPI Flash Memories on Freedom E platforms.
22 * Two working modes are available:
23 * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
24 * on the bus. Writes are only possible in this mode.
25 * - HW mode: Memory content is directly
26 * accessible in CPU memory space. CPU can read and execute memory content.
30 * To have flash memory mapped in CPU memory space, the controller
31 * must have "HW mode" enabled.
32 * 1) The command "reset init" has to initialize the controller and put
33 * it in HW mode (this is actually the default out of reset for Freedom E systems).
34 * 2) every command in this file have to return to prompt in HW mode. */
42 #include <jtag/jtag.h>
43 #include <helper/time_support.h>
44 #include <target/algorithm.h>
45 #include "target/riscv/riscv.h"
47 /* Register offsets */
49 #define FESPI_REG_SCKDIV 0x00
50 #define FESPI_REG_SCKMODE 0x04
51 #define FESPI_REG_CSID 0x10
52 #define FESPI_REG_CSDEF 0x14
53 #define FESPI_REG_CSMODE 0x18
55 #define FESPI_REG_DCSSCK 0x28
56 #define FESPI_REG_DSCKCS 0x2a
57 #define FESPI_REG_DINTERCS 0x2c
58 #define FESPI_REG_DINTERXFR 0x2e
60 #define FESPI_REG_FMT 0x40
61 #define FESPI_REG_TXFIFO 0x48
62 #define FESPI_REG_RXFIFO 0x4c
63 #define FESPI_REG_TXCTRL 0x50
64 #define FESPI_REG_RXCTRL 0x54
66 #define FESPI_REG_FCTRL 0x60
67 #define FESPI_REG_FFMT 0x64
69 #define FESPI_REG_IE 0x70
70 #define FESPI_REG_IP 0x74
74 #define FESPI_SCK_POL 0x1
75 #define FESPI_SCK_PHA 0x2
77 #define FESPI_FMT_PROTO(x) ((x) & 0x3)
78 #define FESPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
79 #define FESPI_FMT_DIR(x) (((x) & 0x1) << 3)
80 #define FESPI_FMT_LEN(x) (((x) & 0xf) << 16)
83 #define FESPI_TXWM(x) ((x) & 0xffff)
85 #define FESPI_RXWM(x) ((x) & 0xffff)
87 #define FESPI_IP_TXWM 0x1
88 #define FESPI_IP_RXWM 0x2
90 #define FESPI_FCTRL_EN 0x1
92 #define FESPI_INSN_CMD_EN 0x1
93 #define FESPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
94 #define FESPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
95 #define FESPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
96 #define FESPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
97 #define FESPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
98 #define FESPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
99 #define FESPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
103 #define FESPI_CSMODE_AUTO 0
104 #define FESPI_CSMODE_HOLD 2
105 #define FESPI_CSMODE_OFF 3
107 #define FESPI_DIR_RX 0
108 #define FESPI_DIR_TX 1
110 #define FESPI_PROTO_S 0
111 #define FESPI_PROTO_D 1
112 #define FESPI_PROTO_Q 2
114 #define FESPI_ENDIAN_MSB 0
115 #define FESPI_ENDIAN_LSB 1
119 #define FESPI_CMD_TIMEOUT (100)
120 #define FESPI_PROBE_TIMEOUT (100)
121 #define FESPI_MAX_TIMEOUT (3000)
124 struct fespi_flash_bank {
126 target_addr_t ctrl_base;
127 const struct flash_device *dev;
130 struct fespi_target {
136 /* TODO !!! What is the right naming convention here? */
137 static const struct fespi_target target_devices[] = {
138 /* name, tap_idcode, ctrl_base */
139 { "Freedom E310-G000 SPI Flash", 0x10e31913, 0x10014000 },
140 { "Freedom E310-G002 SPI Flash", 0x20000913, 0x10014000 },
144 FLASH_BANK_COMMAND_HANDLER(fespi_flash_bank_command)
146 struct fespi_flash_bank *fespi_info;
148 LOG_DEBUG("%s", __func__);
151 return ERROR_COMMAND_SYNTAX_ERROR;
153 fespi_info = malloc(sizeof(struct fespi_flash_bank));
154 if (fespi_info == NULL) {
155 LOG_ERROR("not enough memory");
159 bank->driver_priv = fespi_info;
160 fespi_info->probed = false;
161 fespi_info->ctrl_base = 0;
163 COMMAND_PARSE_ADDRESS(CMD_ARGV[6], fespi_info->ctrl_base);
164 LOG_DEBUG("ASSUMING FESPI device at ctrl_base = " TARGET_ADDR_FMT,
165 fespi_info->ctrl_base);
171 static int fespi_read_reg(struct flash_bank *bank, uint32_t *value, target_addr_t address)
173 struct target *target = bank->target;
174 struct fespi_flash_bank *fespi_info = bank->driver_priv;
176 int result = target_read_u32(target, fespi_info->ctrl_base + address, value);
177 if (result != ERROR_OK) {
178 LOG_ERROR("fespi_read_reg() error at " TARGET_ADDR_FMT,
179 fespi_info->ctrl_base + address);
185 static int fespi_write_reg(struct flash_bank *bank, target_addr_t address, uint32_t value)
187 struct target *target = bank->target;
188 struct fespi_flash_bank *fespi_info = bank->driver_priv;
190 int result = target_write_u32(target, fespi_info->ctrl_base + address, value);
191 if (result != ERROR_OK) {
192 LOG_ERROR("fespi_write_reg() error writing 0x%" PRIx32 " to " TARGET_ADDR_FMT,
193 value, fespi_info->ctrl_base + address);
199 static int fespi_disable_hw_mode(struct flash_bank *bank)
202 if (fespi_read_reg(bank, &fctrl, FESPI_REG_FCTRL) != ERROR_OK)
204 return fespi_write_reg(bank, FESPI_REG_FCTRL, fctrl & ~FESPI_FCTRL_EN);
207 static int fespi_enable_hw_mode(struct flash_bank *bank)
210 if (fespi_read_reg(bank, &fctrl, FESPI_REG_FCTRL) != ERROR_OK)
212 return fespi_write_reg(bank, FESPI_REG_FCTRL, fctrl | FESPI_FCTRL_EN);
215 static int fespi_set_dir(struct flash_bank *bank, bool dir)
218 if (fespi_read_reg(bank, &fmt, FESPI_REG_FMT) != ERROR_OK)
221 return fespi_write_reg(bank, FESPI_REG_FMT,
222 (fmt & ~(FESPI_FMT_DIR(0xFFFFFFFF))) | FESPI_FMT_DIR(dir));
225 static int fespi_txwm_wait(struct flash_bank *bank)
227 int64_t start = timeval_ms();
231 if (fespi_read_reg(bank, &ip, FESPI_REG_IP) != ERROR_OK)
233 if (ip & FESPI_IP_TXWM)
235 int64_t now = timeval_ms();
236 if (now - start > 1000) {
237 LOG_ERROR("ip.txwm didn't get set.");
238 return ERROR_TARGET_TIMEOUT;
245 static int fespi_tx(struct flash_bank *bank, uint8_t in)
247 int64_t start = timeval_ms();
251 if (fespi_read_reg(bank, &txfifo, FESPI_REG_TXFIFO) != ERROR_OK)
255 int64_t now = timeval_ms();
256 if (now - start > 1000) {
257 LOG_ERROR("txfifo stayed negative.");
258 return ERROR_TARGET_TIMEOUT;
262 return fespi_write_reg(bank, FESPI_REG_TXFIFO, in);
265 static int fespi_rx(struct flash_bank *bank, uint8_t *out)
267 int64_t start = timeval_ms();
271 if (fespi_read_reg(bank, &value, FESPI_REG_RXFIFO) != ERROR_OK)
275 int64_t now = timeval_ms();
276 if (now - start > 1000) {
277 LOG_ERROR("rxfifo didn't go positive (value=0x%" PRIx32 ").", value);
278 return ERROR_TARGET_TIMEOUT;
288 /* TODO!!! Why don't we need to call this after writing? */
289 static int fespi_wip(struct flash_bank *bank, int timeout)
293 fespi_set_dir(bank, FESPI_DIR_RX);
295 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
297 endtime = timeval_ms() + timeout;
299 fespi_tx(bank, SPIFLASH_READ_STATUS);
300 if (fespi_rx(bank, NULL) != ERROR_OK)
308 if (fespi_rx(bank, &rx) != ERROR_OK)
310 if ((rx & SPIFLASH_BSY_BIT) == 0) {
311 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
313 fespi_set_dir(bank, FESPI_DIR_TX);
316 } while (timeval_ms() < endtime);
318 LOG_ERROR("timeout");
322 static int fespi_erase_sector(struct flash_bank *bank, int sector)
324 struct fespi_flash_bank *fespi_info = bank->driver_priv;
327 retval = fespi_tx(bank, SPIFLASH_WRITE_ENABLE);
328 if (retval != ERROR_OK)
330 retval = fespi_txwm_wait(bank);
331 if (retval != ERROR_OK)
334 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
336 retval = fespi_tx(bank, fespi_info->dev->erase_cmd);
337 if (retval != ERROR_OK)
339 sector = bank->sectors[sector].offset;
340 retval = fespi_tx(bank, sector >> 16);
341 if (retval != ERROR_OK)
343 retval = fespi_tx(bank, sector >> 8);
344 if (retval != ERROR_OK)
346 retval = fespi_tx(bank, sector);
347 if (retval != ERROR_OK)
349 retval = fespi_txwm_wait(bank);
350 if (retval != ERROR_OK)
352 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
355 retval = fespi_wip(bank, FESPI_MAX_TIMEOUT);
356 if (retval != ERROR_OK)
362 static int fespi_erase(struct flash_bank *bank, unsigned int first,
365 struct target *target = bank->target;
366 struct fespi_flash_bank *fespi_info = bank->driver_priv;
367 int retval = ERROR_OK;
369 LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
371 if (target->state != TARGET_HALTED) {
372 LOG_ERROR("Target not halted");
373 return ERROR_TARGET_NOT_HALTED;
376 if ((last < first) || (last >= bank->num_sectors)) {
377 LOG_ERROR("Flash sector invalid");
378 return ERROR_FLASH_SECTOR_INVALID;
381 if (!(fespi_info->probed)) {
382 LOG_ERROR("Flash bank not probed");
383 return ERROR_FLASH_BANK_NOT_PROBED;
386 for (unsigned int sector = first; sector <= last; sector++) {
387 if (bank->sectors[sector].is_protected) {
388 LOG_ERROR("Flash sector %u protected", sector);
393 if (fespi_info->dev->erase_cmd == 0x00)
394 return ERROR_FLASH_OPER_UNSUPPORTED;
396 if (fespi_write_reg(bank, FESPI_REG_TXCTRL, FESPI_TXWM(1)) != ERROR_OK)
398 retval = fespi_txwm_wait(bank);
399 if (retval != ERROR_OK) {
400 LOG_ERROR("WM Didn't go high before attempting.");
404 /* Disable Hardware accesses*/
405 if (fespi_disable_hw_mode(bank) != ERROR_OK)
409 retval = fespi_wip(bank, FESPI_PROBE_TIMEOUT);
410 if (retval != ERROR_OK)
413 for (unsigned int sector = first; sector <= last; sector++) {
414 retval = fespi_erase_sector(bank, sector);
415 if (retval != ERROR_OK)
420 /* Switch to HW mode before return to prompt */
422 if (fespi_enable_hw_mode(bank) != ERROR_OK)
427 static int fespi_protect(struct flash_bank *bank, int set,
428 unsigned int first, unsigned int last)
430 for (unsigned int sector = first; sector <= last; sector++)
431 bank->sectors[sector].is_protected = set;
435 static int slow_fespi_write_buffer(struct flash_bank *bank,
436 const uint8_t *buffer, uint32_t offset, uint32_t len)
440 if (offset & 0xFF000000) {
441 LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%" PRIx32,
446 /* TODO!!! assert that len < page size */
448 fespi_tx(bank, SPIFLASH_WRITE_ENABLE);
449 fespi_txwm_wait(bank);
451 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
454 fespi_tx(bank, SPIFLASH_PAGE_PROGRAM);
456 fespi_tx(bank, offset >> 16);
457 fespi_tx(bank, offset >> 8);
458 fespi_tx(bank, offset);
460 for (ii = 0; ii < len; ii++)
461 fespi_tx(bank, buffer[ii]);
463 fespi_txwm_wait(bank);
465 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
473 static const uint8_t algorithm_bin[] = {
474 #include "../../../contrib/loaders/flash/fespi/fespi.inc"
478 #define STEP_TXWM_WAIT 12
479 #define STEP_WRITE_REG 16
480 #define STEP_WIP_WAIT 20
481 #define STEP_SET_DIR 24
482 #define STEP_NOP 0xff
484 struct algorithm_steps {
490 static struct algorithm_steps *as_new(void)
492 struct algorithm_steps *as = calloc(1, sizeof(struct algorithm_steps));
494 as->steps = malloc(as->size * sizeof(as->steps[0]));
498 static struct algorithm_steps *as_delete(struct algorithm_steps *as)
500 for (unsigned step = 0; step < as->used; step++) {
501 free(as->steps[step]);
502 as->steps[step] = NULL;
509 static int as_empty(struct algorithm_steps *as)
511 for (unsigned s = 0; s < as->used; s++) {
512 if (as->steps[s][0] != STEP_NOP)
518 /* Return size of compiled program. */
519 static unsigned as_compile(struct algorithm_steps *as, uint8_t *target,
520 unsigned target_size)
523 bool finish_early = false;
524 for (unsigned s = 0; s < as->used && !finish_early; s++) {
525 unsigned bytes_left = target_size - offset;
526 switch (as->steps[s][0]) {
531 unsigned size = as->steps[s][1];
532 if (size + 3 > bytes_left) {
536 memcpy(target + offset, as->steps[s], size + 2);
541 if (4 > bytes_left) {
545 memcpy(target + offset, as->steps[s], 3);
549 if (3 > bytes_left) {
553 memcpy(target + offset, as->steps[s], 2);
558 if (2 > bytes_left) {
562 memcpy(target + offset, as->steps[s], 1);
569 as->steps[s][0] = STEP_NOP;
571 assert(offset + 1 <= target_size);
572 target[offset++] = STEP_EXIT;
574 LOG_DEBUG("%d-byte program:", offset);
575 for (unsigned i = 0; i < offset;) {
577 for (unsigned x = 0; i < offset && x < 16; x++, i++)
578 sprintf(buf + x*3, "%02x ", target[i]);
579 LOG_DEBUG("%s", buf);
585 static void as_add_step(struct algorithm_steps *as, uint8_t *step)
587 if (as->used == as->size) {
589 as->steps = realloc(as->steps, sizeof(as->steps[0]) * as->size);
590 LOG_DEBUG("Increased size to 0x%x", as->size);
592 as->steps[as->used] = step;
596 static void as_add_tx(struct algorithm_steps *as, unsigned count, const uint8_t *data)
598 LOG_DEBUG("count=%d", count);
600 unsigned step_count = MIN(count, 255);
601 uint8_t *step = malloc(step_count + 2);
603 step[1] = step_count;
604 memcpy(step + 2, data, step_count);
605 as_add_step(as, step);
611 static void as_add_tx1(struct algorithm_steps *as, uint8_t byte)
615 as_add_tx(as, 1, data);
618 static void as_add_write_reg(struct algorithm_steps *as, uint8_t offset, uint8_t data)
620 uint8_t *step = malloc(3);
621 step[0] = STEP_WRITE_REG;
624 as_add_step(as, step);
627 static void as_add_txwm_wait(struct algorithm_steps *as)
629 uint8_t *step = malloc(1);
630 step[0] = STEP_TXWM_WAIT;
631 as_add_step(as, step);
634 static void as_add_wip_wait(struct algorithm_steps *as)
636 uint8_t *step = malloc(1);
637 step[0] = STEP_WIP_WAIT;
638 as_add_step(as, step);
641 static void as_add_set_dir(struct algorithm_steps *as, bool dir)
643 uint8_t *step = malloc(2);
644 step[0] = STEP_SET_DIR;
645 step[1] = FESPI_FMT_DIR(dir);
646 as_add_step(as, step);
649 /* This should write something less than or equal to a page.*/
650 static int steps_add_buffer_write(struct algorithm_steps *as,
651 const uint8_t *buffer, uint32_t chip_offset, uint32_t len)
653 if (chip_offset & 0xFF000000) {
654 LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%" PRIx32,
659 as_add_tx1(as, SPIFLASH_WRITE_ENABLE);
660 as_add_txwm_wait(as);
661 as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
664 SPIFLASH_PAGE_PROGRAM,
669 as_add_tx(as, sizeof(setup), setup);
671 as_add_tx(as, len, buffer);
672 as_add_txwm_wait(as);
673 as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
676 as_add_set_dir(as, FESPI_DIR_RX);
677 as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
679 as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
680 as_add_set_dir(as, FESPI_DIR_TX);
685 static int steps_execute(struct algorithm_steps *as,
686 struct flash_bank *bank, struct working_area *algorithm_wa,
687 struct working_area *data_wa)
689 struct target *target = bank->target;
690 struct fespi_flash_bank *fespi_info = bank->driver_priv;
691 uint32_t ctrl_base = fespi_info->ctrl_base;
692 int xlen = riscv_xlen(target);
694 struct reg_param reg_params[2];
695 init_reg_param(®_params[0], "a0", xlen, PARAM_OUT);
696 init_reg_param(®_params[1], "a1", xlen, PARAM_OUT);
697 buf_set_u64(reg_params[0].value, 0, xlen, ctrl_base);
698 buf_set_u64(reg_params[1].value, 0, xlen, data_wa->address);
700 int retval = ERROR_OK;
701 while (!as_empty(as)) {
703 uint8_t *data_buf = malloc(data_wa->size);
704 unsigned bytes = as_compile(as, data_buf, data_wa->size);
705 retval = target_write_buffer(target, data_wa->address, bytes,
708 if (retval != ERROR_OK) {
709 LOG_ERROR("Failed to write data to " TARGET_ADDR_FMT ": %d",
710 data_wa->address, retval);
714 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
715 algorithm_wa->address, algorithm_wa->address + 4,
717 if (retval != ERROR_OK) {
718 LOG_ERROR("Failed to execute algorithm at " TARGET_ADDR_FMT ": %d",
719 algorithm_wa->address, retval);
725 destroy_reg_param(®_params[1]);
726 destroy_reg_param(®_params[0]);
730 static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
731 uint32_t offset, uint32_t count)
733 struct target *target = bank->target;
734 struct fespi_flash_bank *fespi_info = bank->driver_priv;
735 uint32_t cur_count, page_size, page_offset;
736 int retval = ERROR_OK;
738 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
739 __func__, offset, count);
741 if (target->state != TARGET_HALTED) {
742 LOG_ERROR("Target not halted");
743 return ERROR_TARGET_NOT_HALTED;
746 if (offset + count > fespi_info->dev->size_in_bytes) {
747 LOG_WARNING("Write past end of flash. Extra data discarded.");
748 count = fespi_info->dev->size_in_bytes - offset;
751 /* Check sector protection */
752 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
753 /* Start offset in or before this sector? */
754 /* End offset in or behind this sector? */
756 (bank->sectors[sector].offset + bank->sectors[sector].size))
757 && ((offset + count - 1) >= bank->sectors[sector].offset)
758 && bank->sectors[sector].is_protected) {
759 LOG_ERROR("Flash sector %u protected", sector);
764 struct working_area *algorithm_wa;
765 if (target_alloc_working_area(target, sizeof(algorithm_bin),
766 &algorithm_wa) != ERROR_OK) {
767 LOG_WARNING("Couldn't allocate %zd-byte working area.",
768 sizeof(algorithm_bin));
771 retval = target_write_buffer(target, algorithm_wa->address,
772 sizeof(algorithm_bin), algorithm_bin);
773 if (retval != ERROR_OK) {
774 LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
775 algorithm_wa->address, retval);
776 target_free_working_area(target, algorithm_wa);
781 struct working_area *data_wa = NULL;
782 unsigned data_wa_size = 2 * count;
784 if (data_wa_size < 128) {
785 LOG_WARNING("Couldn't allocate data working area.");
786 target_free_working_area(target, algorithm_wa);
789 if (target_alloc_working_area_try(target, data_wa_size, &data_wa) ==
797 /* If no valid page_size, use reasonable default. */
798 page_size = fespi_info->dev->pagesize ?
799 fespi_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
801 fespi_txwm_wait(bank);
803 /* Disable Hardware accesses*/
804 if (fespi_disable_hw_mode(bank) != ERROR_OK)
807 struct algorithm_steps *as = as_new();
810 retval = fespi_wip(bank, FESPI_PROBE_TIMEOUT);
811 if (retval != ERROR_OK)
814 page_offset = offset % page_size;
815 /* central part, aligned words */
817 /* clip block at page boundary */
818 if (page_offset + count > page_size)
819 cur_count = page_size - page_offset;
824 retval = steps_add_buffer_write(as, buffer, offset, cur_count);
826 retval = slow_fespi_write_buffer(bank, buffer, offset, cur_count);
827 if (retval != ERROR_OK)
837 retval = steps_execute(as, bank, algorithm_wa, data_wa);
841 target_free_working_area(target, data_wa);
842 target_free_working_area(target, algorithm_wa);
847 /* Switch to HW mode before return to prompt */
848 if (fespi_enable_hw_mode(bank) != ERROR_OK)
853 /* Return ID of flash device */
854 /* On exit, SW mode is kept */
855 static int fespi_read_flash_id(struct flash_bank *bank, uint32_t *id)
857 struct target *target = bank->target;
860 if (target->state != TARGET_HALTED) {
861 LOG_ERROR("Target not halted");
862 return ERROR_TARGET_NOT_HALTED;
865 fespi_txwm_wait(bank);
868 retval = fespi_wip(bank, FESPI_PROBE_TIMEOUT);
869 if (retval != ERROR_OK)
872 fespi_set_dir(bank, FESPI_DIR_RX);
874 /* Send SPI command "read ID" */
875 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
878 fespi_tx(bank, SPIFLASH_READ_ID);
879 /* Send dummy bytes to actually read the ID.*/
884 /* read ID from Receive Register */
886 if (fespi_rx(bank, NULL) != ERROR_OK)
889 if (fespi_rx(bank, &rx) != ERROR_OK)
892 if (fespi_rx(bank, &rx) != ERROR_OK)
895 if (fespi_rx(bank, &rx) != ERROR_OK)
899 if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
902 fespi_set_dir(bank, FESPI_DIR_TX);
907 static int fespi_probe(struct flash_bank *bank)
909 struct target *target = bank->target;
910 struct fespi_flash_bank *fespi_info = bank->driver_priv;
911 struct flash_sector *sectors;
912 uint32_t id = 0; /* silence uninitialized warning */
913 const struct fespi_target *target_device;
917 if (fespi_info->probed)
919 fespi_info->probed = false;
921 if (fespi_info->ctrl_base == 0) {
922 for (target_device = target_devices ; target_device->name ; ++target_device)
923 if (target_device->tap_idcode == target->tap->idcode)
926 if (!target_device->name) {
927 LOG_ERROR("Device ID 0x%" PRIx32 " is not known as FESPI capable",
928 target->tap->idcode);
932 fespi_info->ctrl_base = target_device->ctrl_base;
934 LOG_DEBUG("Valid FESPI on device %s at address " TARGET_ADDR_FMT,
935 target_device->name, bank->base);
938 LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
939 " with ctrl at " TARGET_ADDR_FMT, fespi_info->ctrl_base,
943 /* read and decode flash ID; returns in SW mode */
944 if (fespi_write_reg(bank, FESPI_REG_TXCTRL, FESPI_TXWM(1)) != ERROR_OK)
946 fespi_set_dir(bank, FESPI_DIR_TX);
948 /* Disable Hardware accesses*/
949 if (fespi_disable_hw_mode(bank) != ERROR_OK)
952 retval = fespi_read_flash_id(bank, &id);
954 if (fespi_enable_hw_mode(bank) != ERROR_OK)
956 if (retval != ERROR_OK)
959 fespi_info->dev = NULL;
960 for (const struct flash_device *p = flash_devices; p->name ; p++)
961 if (p->device_id == id) {
966 if (!fespi_info->dev) {
967 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
971 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
972 fespi_info->dev->name, fespi_info->dev->device_id);
974 /* Set correct size value */
975 bank->size = fespi_info->dev->size_in_bytes;
977 if (bank->size <= (1UL << 16))
978 LOG_WARNING("device needs 2-byte addresses - not implemented");
979 if (bank->size > (1UL << 24))
980 LOG_WARNING("device needs paging or 4-byte addresses - not implemented");
982 /* if no sectors, treat whole bank as single sector */
983 sectorsize = fespi_info->dev->sectorsize ?
984 fespi_info->dev->sectorsize : fespi_info->dev->size_in_bytes;
986 /* create and fill sectors array */
987 bank->num_sectors = fespi_info->dev->size_in_bytes / sectorsize;
988 sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
989 if (sectors == NULL) {
990 LOG_ERROR("not enough memory");
994 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
995 sectors[sector].offset = sector * sectorsize;
996 sectors[sector].size = sectorsize;
997 sectors[sector].is_erased = -1;
998 sectors[sector].is_protected = 0;
1001 bank->sectors = sectors;
1002 fespi_info->probed = true;
1006 static int fespi_auto_probe(struct flash_bank *bank)
1008 struct fespi_flash_bank *fespi_info = bank->driver_priv;
1009 if (fespi_info->probed)
1011 return fespi_probe(bank);
1014 static int fespi_protect_check(struct flash_bank *bank)
1016 /* Nothing to do. Protection is only handled in SW. */
1020 static int get_fespi_info(struct flash_bank *bank, char *buf, int buf_size)
1022 struct fespi_flash_bank *fespi_info = bank->driver_priv;
1024 if (!(fespi_info->probed)) {
1025 snprintf(buf, buf_size,
1026 "\nFESPI flash bank not probed yet\n");
1030 snprintf(buf, buf_size, "\nFESPI flash information:\n"
1031 " Device \'%s\' (ID 0x%08" PRIx32 ")\n",
1032 fespi_info->dev->name, fespi_info->dev->device_id);
1037 const struct flash_driver fespi_flash = {
1039 .flash_bank_command = fespi_flash_bank_command,
1040 .erase = fespi_erase,
1041 .protect = fespi_protect,
1042 .write = fespi_write,
1043 .read = default_flash_read,
1044 .probe = fespi_probe,
1045 .auto_probe = fespi_auto_probe,
1046 .erase_check = default_flash_blank_check,
1047 .protect_check = fespi_protect_check,
1048 .info = get_fespi_info,
1049 .free_driver_priv = default_flash_free_driver_priv