git.gag.com Git - fw/openocd/blob - src/flash/nor/esirisc_flash.c

   1 /***************************************************************************
   2  *   Copyright (C) 2018 by Square, Inc.                                    *
   3  *   Steven Stallion <stallion@squareup.com>                               *
   4  *   James Zhao <hjz@squareup.com>                                         *
   5  *                                                                         *
   6  *   This program is free software; you can redistribute it and/or modify  *
   7  *   it under the terms of the GNU General Public License as published by  *
   8  *   the Free Software Foundation; either version 2 of the License, or     *
   9  *   (at your option) any later version.                                   *
  10  *                                                                         *
  11  *   This program is distributed in the hope that it will be useful,       *
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  14  *   GNU General Public License for more details.                          *
  15  *                                                                         *
  16  *   You should have received a copy of the GNU General Public License     *
  17  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  18  ***************************************************************************/
  19
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <flash/common.h>
  25 #include <flash/nor/imp.h>
  26 #include <helper/command.h>
  27 #include <helper/log.h>
  28 #include <helper/time_support.h>
  29 #include <helper/types.h>
  30 #include <target/esirisc.h>
  31 #include <target/target.h>
  32
  33 /* eSi-TSMC Flash Registers */
  34 #define CONTROL                         0x00    /* Control Register */
  35 #define TIMING0                         0x04    /* Timing Register 0 */
  36 #define TIMING1                         0x08    /* Timing Register 1 */
  37 #define TIMING2                         0x0c    /* Timing Register 2 */
  38 #define UNLOCK1                         0x18    /* Unlock 1 */
  39 #define UNLOCK2                         0x1c    /* Unlock 2 */
  40 #define ADDRESS                         0x20    /* Erase/Program Address */
  41 #define PB_DATA                         0x24    /* Program Buffer Data */
  42 #define PB_INDEX                        0x28    /* Program Buffer Index */
  43 #define STATUS                          0x2c    /* Status Register */
  44 #define REDUN_0                         0x30    /* Redundant Address 0 */
  45 #define REDUN_1                         0x34    /* Redundant Address 1 */
  46
  47 /* Control Fields */
  48 #define CONTROL_SLM                     (1<<0)  /* Sleep Mode */
  49 #define CONTROL_WP                      (1<<1)  /* Register Write Protect */
  50 #define CONTROL_E                       (1<<3)  /* Erase */
  51 #define CONTROL_EP                      (1<<4)  /* Erase Page */
  52 #define CONTROL_P                       (1<<5)  /* Program Flash */
  53 #define CONTROL_ERC                     (1<<6)  /* Erase Reference Cell */
  54 #define CONTROL_R                       (1<<7)  /* Recall Trim Code */
  55 #define CONTROL_AP                      (1<<8)  /* Auto-Program */
  56
  57 /* Timing Fields */
  58 #define TIMING0_R(x)            (((x) <<  0) & 0x3f)            /* Read Wait States */
  59 #define TIMING0_F(x)            (((x) << 16) & 0xffff0000)      /* Tnvh Clock Cycles */
  60 #define TIMING1_E(x)            (((x) <<  0) & 0xffffff)        /* Tme/Terase/Tre Clock Cycles */
  61 #define TIMING2_P(x)            (((x) <<  0) & 0xffff)          /* Tprog Clock Cycles */
  62 #define TIMING2_H(x)            (((x) << 16) & 0xff0000)        /* Clock Cycles in 100ns */
  63 #define TIMING2_T(x)            (((x) << 24) & 0xf000000)       /* Clock Cycles in 10ns */
  64
  65 /* Status Fields */
  66 #define STATUS_BUSY                     (1<<0)  /* Busy (Erase/Program) */
  67 #define STATUS_WER                      (1<<1)  /* Write Protect Error */
  68 #define STATUS_DR                       (1<<2)  /* Disable Redundancy */
  69 #define STATUS_DIS                      (1<<3)  /* Discharged */
  70 #define STATUS_BO                       (1<<4)  /* Brown Out */
  71
  72 /* Redundant Address Fields */
  73 #define REDUN_R                         (1<<0)                                          /* Used */
  74 #define REDUN_P(x)                      (((x) << 12) & 0x7f000)         /* Redundant Page Address */
  75
  76 /*
  77  * The eSi-TSMC Flash manual provides two sets of timings based on the
  78  * underlying flash process. By default, 90nm is assumed.
  79  */
  80 #if 0 /* 55nm */
  81 #define TNVH                            5000            /* 5us   */
  82 #define TME                                     80000000        /* 80ms  */
  83 #define TERASE                          160000000       /* 160ms */
  84 #define TRE                                     100000000       /* 100ms */
  85 #define TPROG                           8000            /* 8us   */
  86 #else /* 90nm */
  87 #define TNVH                            5000            /* 5us   */
  88 #define TME                                     20000000        /* 20ms  */
  89 #define TERASE                          40000000        /* 40ms  */
  90 #define TRE                                     40000000        /* 40ms  */
  91 #define TPROG                           40000           /* 40us  */
  92 #endif
  93
  94 #define CONTROL_TIMEOUT         5000            /* 5s    */
  95 #define PAGE_SIZE                       4096
  96 #define PB_MAX                          32
  97
  98 #define NUM_NS_PER_S            1000000000ULL
  99
 100 struct esirisc_flash_bank {
 101         bool probed;
 102         uint32_t cfg;
 103         uint32_t clock;
 104         uint32_t wait_states;
 105 };
 106
 107 FLASH_BANK_COMMAND_HANDLER(esirisc_flash_bank_command)
 108 {
 109         struct esirisc_flash_bank *esirisc_info;
 110
 111         if (CMD_ARGC < 9)
 112                 return ERROR_COMMAND_SYNTAX_ERROR;
 113
 114         esirisc_info = calloc(1, sizeof(struct esirisc_flash_bank));
 115
 116         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], esirisc_info->cfg);
 117         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], esirisc_info->clock);
 118         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[8], esirisc_info->wait_states);
 119
 120         bank->driver_priv = esirisc_info;
 121
 122         return ERROR_OK;
 123 }
 124
 125 /*
 126  * Register writes are ignored if the control.WP flag is set; the
 127  * following sequence is required to modify this flag even when
 128  * protection is disabled.
 129  */
 130 static int esirisc_flash_unlock(struct flash_bank *bank)
 131 {
 132         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 133         struct target *target = bank->target;
 134
 135         target_write_u32(target, esirisc_info->cfg + UNLOCK1, 0x7123);
 136         target_write_u32(target, esirisc_info->cfg + UNLOCK2, 0x812a);
 137         target_write_u32(target, esirisc_info->cfg + UNLOCK1, 0xbee1);
 138
 139         return ERROR_OK;
 140 }
 141
 142 static int esirisc_flash_disable_protect(struct flash_bank *bank)
 143 {
 144         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 145         struct target *target = bank->target;
 146         uint32_t control;
 147
 148         target_read_u32(target, esirisc_info->cfg + CONTROL, &control);
 149         if (!(control & CONTROL_WP))
 150                 return ERROR_OK;
 151
 152         esirisc_flash_unlock(bank);
 153
 154         control &= ~CONTROL_WP;
 155
 156         target_write_u32(target, esirisc_info->cfg + CONTROL, control);
 157
 158         return ERROR_OK;
 159 }
 160
 161 static int esirisc_flash_enable_protect(struct flash_bank *bank)
 162 {
 163         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 164         struct target *target = bank->target;
 165         uint32_t control;
 166
 167         target_read_u32(target, esirisc_info->cfg + CONTROL, &control);
 168         if (control & CONTROL_WP)
 169                 return ERROR_OK;
 170
 171         esirisc_flash_unlock(bank);
 172
 173         control |= CONTROL_WP;
 174
 175         target_write_u32(target, esirisc_info->cfg + CONTROL, control);
 176
 177         return ERROR_OK;
 178 }
 179
 180 static int esirisc_flash_check_status(struct flash_bank *bank)
 181 {
 182         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 183         struct target *target = bank->target;
 184         uint32_t status;
 185
 186         target_read_u32(target, esirisc_info->cfg + STATUS, &status);
 187         if (status & STATUS_WER) {
 188                 LOG_ERROR("%s: bad status: 0x%" PRIx32, bank->name, status);
 189                 return ERROR_FLASH_OPERATION_FAILED;
 190         }
 191
 192         return ERROR_OK;
 193 }
 194
 195 static int esirisc_flash_clear_status(struct flash_bank *bank)
 196 {
 197         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 198         struct target *target = bank->target;
 199
 200         target_write_u32(target, esirisc_info->cfg + STATUS, STATUS_WER);
 201
 202         return ERROR_OK;
 203 }
 204
 205 static int esirisc_flash_wait(struct flash_bank *bank, int ms)
 206 {
 207         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 208         struct target *target = bank->target;
 209         uint32_t status;
 210         int64_t t;
 211
 212         t = timeval_ms();
 213         for (;;) {
 214                 target_read_u32(target, esirisc_info->cfg + STATUS, &status);
 215                 if (!(status & STATUS_BUSY))
 216                         return ERROR_OK;
 217
 218                 if ((timeval_ms() - t) > ms)
 219                         return ERROR_TARGET_TIMEOUT;
 220
 221                 keep_alive();
 222         }
 223 }
 224
 225 static int esirisc_flash_control(struct flash_bank *bank, uint32_t control)
 226 {
 227         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 228         struct target *target = bank->target;
 229
 230         esirisc_flash_clear_status(bank);
 231
 232         target_write_u32(target, esirisc_info->cfg + CONTROL, control);
 233
 234         int retval = esirisc_flash_wait(bank, CONTROL_TIMEOUT);
 235         if (retval != ERROR_OK) {
 236                 LOG_ERROR("%s: control timed out: 0x%" PRIx32, bank->name, control);
 237                 return retval;
 238         }
 239
 240         return esirisc_flash_check_status(bank);
 241 }
 242
 243 static int esirisc_flash_recall(struct flash_bank *bank)
 244 {
 245         return esirisc_flash_control(bank, CONTROL_R);
 246 }
 247
 248 static int esirisc_flash_erase(struct flash_bank *bank, int first, int last)
 249 {
 250         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 251         struct target *target = bank->target;
 252         int retval = ERROR_OK;
 253
 254         if (target->state != TARGET_HALTED)
 255                 return ERROR_TARGET_NOT_HALTED;
 256
 257         esirisc_flash_disable_protect(bank);
 258
 259         for (int page = first; page < last; ++page) {
 260                 uint32_t address = page * PAGE_SIZE;
 261
 262                 target_write_u32(target, esirisc_info->cfg + ADDRESS, address);
 263
 264                 retval = esirisc_flash_control(bank, CONTROL_EP);
 265                 if (retval != ERROR_OK) {
 266                         LOG_ERROR("%s: failed to erase address: 0x%" PRIx32, bank->name, address);
 267                         break;
 268                 }
 269         }
 270
 271         esirisc_flash_enable_protect(bank);
 272
 273         return retval;
 274 }
 275
 276 static int esirisc_flash_mass_erase(struct flash_bank *bank)
 277 {
 278         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 279         struct target *target = bank->target;
 280         int retval;
 281
 282         if (target->state != TARGET_HALTED)
 283                 return ERROR_TARGET_NOT_HALTED;
 284
 285         esirisc_flash_disable_protect(bank);
 286
 287         target_write_u32(target, esirisc_info->cfg + ADDRESS, 0);
 288
 289         retval = esirisc_flash_control(bank, CONTROL_E);
 290         if (retval != ERROR_OK)
 291                 LOG_ERROR("%s: failed to mass erase", bank->name);
 292
 293         esirisc_flash_enable_protect(bank);
 294
 295         return retval;
 296 }
 297
 298 /*
 299  * Per TSMC, the reference cell should be erased once per sample. This
 300  * is typically done during wafer sort, however we include support for
 301  * those that may need to calibrate flash at a later time.
 302  */
 303 static int esirisc_flash_ref_erase(struct flash_bank *bank)
 304 {
 305         struct target *target = bank->target;
 306         int retval;
 307
 308         if (target->state != TARGET_HALTED)
 309                 return ERROR_TARGET_NOT_HALTED;
 310
 311         esirisc_flash_disable_protect(bank);
 312
 313         retval = esirisc_flash_control(bank, CONTROL_ERC);
 314         if (retval != ERROR_OK)
 315                 LOG_ERROR("%s: failed to erase reference cell", bank->name);
 316
 317         esirisc_flash_enable_protect(bank);
 318
 319         return retval;
 320 }
 321
 322 static int esirisc_flash_protect(struct flash_bank *bank, int set, int first, int last)
 323 {
 324         struct target *target = bank->target;
 325
 326         if (target->state != TARGET_HALTED)
 327                 return ERROR_TARGET_NOT_HALTED;
 328
 329         if (set)
 330                 esirisc_flash_enable_protect(bank);
 331         else
 332                 esirisc_flash_disable_protect(bank);
 333
 334         return ERROR_OK;
 335 }
 336
 337 static int esirisc_flash_fill_pb(struct flash_bank *bank,
 338                 const uint8_t *buffer, uint32_t count)
 339 {
 340         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 341         struct target *target = bank->target;
 342         struct esirisc_common *esirisc = target_to_esirisc(target);
 343
 344         /*
 345          * The pb_index register is auto-incremented when pb_data is written
 346          * and should be cleared before each operation.
 347          */
 348         target_write_u32(target, esirisc_info->cfg + PB_INDEX, 0);
 349
 350         /*
 351          * The width of the pb_data register depends on the underlying
 352          * target; writing one byte at a time incurs a significant
 353          * performance penalty and should be avoided.
 354          */
 355         while (count > 0) {
 356                 uint32_t max_bytes = DIV_ROUND_UP(esirisc->num_bits, 8);
 357                 uint32_t num_bytes = MIN(count, max_bytes);
 358
 359                 target_write_buffer(target, esirisc_info->cfg + PB_DATA, num_bytes, buffer);
 360
 361                 buffer += num_bytes;
 362                 count -= num_bytes;
 363         }
 364
 365         return ERROR_OK;
 366 }
 367
 368 static int esirisc_flash_write(struct flash_bank *bank,
 369                 const uint8_t *buffer, uint32_t offset, uint32_t count)
 370 {
 371         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 372         struct target *target = bank->target;
 373         int retval = ERROR_OK;
 374
 375         if (target->state != TARGET_HALTED)
 376                 return ERROR_TARGET_NOT_HALTED;
 377
 378         esirisc_flash_disable_protect(bank);
 379
 380         /*
 381          * The address register is auto-incremented based on the contents of
 382          * the pb_index register after each operation completes. It can be
 383          * set once provided pb_index is cleared before each operation.
 384          */
 385         target_write_u32(target, esirisc_info->cfg + ADDRESS, offset);
 386
 387         /*
 388          * Care must be taken when filling the program buffer; a maximum of
 389          * 32 bytes may be written at a time and may not cross a 32-byte
 390          * boundary based on the current offset.
 391          */
 392         while (count > 0) {
 393                 uint32_t max_bytes = PB_MAX - (offset & 0x1f);
 394                 uint32_t num_bytes = MIN(count, max_bytes);
 395
 396                 esirisc_flash_fill_pb(bank, buffer, num_bytes);
 397
 398                 retval = esirisc_flash_control(bank, CONTROL_P);
 399                 if (retval != ERROR_OK) {
 400                         LOG_ERROR("%s: failed to program address: 0x%" PRIx32, bank->name, offset);
 401                         break;
 402                 }
 403
 404                 buffer += num_bytes;
 405                 offset += num_bytes;
 406                 count -= num_bytes;
 407         }
 408
 409         esirisc_flash_enable_protect(bank);
 410
 411         return retval;
 412 }
 413
 414 static uint32_t esirisc_flash_num_cycles(struct flash_bank *bank, uint64_t ns)
 415 {
 416         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 417
 418         /* apply scaling factor to avoid truncation */
 419         uint64_t hz = (uint64_t)esirisc_info->clock * 1000;
 420         uint64_t num_cycles = ((hz / NUM_NS_PER_S) * ns) / 1000;
 421
 422         if (hz % NUM_NS_PER_S > 0)
 423                 num_cycles++;
 424
 425         return num_cycles;
 426 }
 427
 428 static int esirisc_flash_init(struct flash_bank *bank)
 429 {
 430         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 431         struct target *target = bank->target;
 432         uint32_t value;
 433         int retval;
 434
 435         esirisc_flash_disable_protect(bank);
 436
 437         /* initialize timing registers */
 438         value = TIMING0_F(esirisc_flash_num_cycles(bank, TNVH)) |
 439                         TIMING0_R(esirisc_info->wait_states);
 440
 441         LOG_DEBUG("TIMING0: 0x%" PRIx32, value);
 442         target_write_u32(target, esirisc_info->cfg + TIMING0, value);
 443
 444         value = TIMING1_E(esirisc_flash_num_cycles(bank, TERASE));
 445
 446         LOG_DEBUG("TIMING1: 0x%" PRIx32, value);
 447         target_write_u32(target, esirisc_info->cfg + TIMING1, value);
 448
 449         value = TIMING2_T(esirisc_flash_num_cycles(bank, 10))   |
 450                         TIMING2_H(esirisc_flash_num_cycles(bank, 100))  |
 451                         TIMING2_P(esirisc_flash_num_cycles(bank, TPROG));
 452
 453         LOG_DEBUG("TIMING2: 0x%" PRIx32, value);
 454         target_write_u32(target, esirisc_info->cfg + TIMING2, value);
 455
 456         /* recall trim code */
 457         retval = esirisc_flash_recall(bank);
 458         if (retval != ERROR_OK)
 459                 LOG_ERROR("%s: failed to recall trim code", bank->name);
 460
 461         esirisc_flash_enable_protect(bank);
 462
 463         return retval;
 464 }
 465
 466 static int esirisc_flash_probe(struct flash_bank *bank)
 467 {
 468         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 469         struct target *target = bank->target;
 470         int retval;
 471
 472         if (target->state != TARGET_HALTED)
 473                 return ERROR_TARGET_NOT_HALTED;
 474
 475         bank->num_sectors = bank->size / PAGE_SIZE;
 476         bank->sectors = alloc_block_array(0, PAGE_SIZE, bank->num_sectors);
 477
 478         /*
 479          * Register write protection is enforced using a single protection
 480          * block for the entire bank. This is as good as it gets.
 481          */
 482         bank->num_prot_blocks = 1;
 483         bank->prot_blocks = alloc_block_array(0, bank->size, bank->num_prot_blocks);
 484
 485         retval = esirisc_flash_init(bank);
 486         if (retval != ERROR_OK) {
 487                 LOG_ERROR("%s: failed to initialize bank", bank->name);
 488                 return retval;
 489         }
 490
 491         esirisc_info->probed = true;
 492
 493         return ERROR_OK;
 494 }
 495
 496 static int esirisc_flash_auto_probe(struct flash_bank *bank)
 497 {
 498         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 499
 500         if (esirisc_info->probed)
 501                 return ERROR_OK;
 502
 503         return esirisc_flash_probe(bank);
 504 }
 505
 506 static int esirisc_flash_protect_check(struct flash_bank *bank)
 507 {
 508         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 509         struct target *target = bank->target;
 510         uint32_t control;
 511
 512         if (target->state != TARGET_HALTED)
 513                 return ERROR_TARGET_NOT_HALTED;
 514
 515         target_read_u32(target, esirisc_info->cfg + CONTROL, &control);
 516
 517         /* single protection block (also see: esirisc_flash_probe()) */
 518         bank->prot_blocks[0].is_protected = !!(control & CONTROL_WP);
 519
 520         return ERROR_OK;
 521 }
 522
 523 static int esirisc_flash_info(struct flash_bank *bank, char *buf, int buf_size)
 524 {
 525         struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
 526
 527         snprintf(buf, buf_size,
 528                         "%4s cfg at 0x%" PRIx32 ", clock %" PRId32 ", wait_states %" PRId32,
 529                         "",     /* align with first line */
 530                         esirisc_info->cfg,
 531                         esirisc_info->clock,
 532                         esirisc_info->wait_states);
 533
 534         return ERROR_OK;
 535 }
 536
 537 COMMAND_HANDLER(handle_esirisc_flash_mass_erase_command)
 538 {
 539         struct flash_bank *bank;
 540         int retval;
 541
 542         if (CMD_ARGC < 1)
 543                 return ERROR_COMMAND_SYNTAX_ERROR;
 544
 545         retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 546         if (retval != ERROR_OK)
 547                 return retval;
 548
 549         retval = esirisc_flash_mass_erase(bank);
 550
 551         command_print(CMD_CTX, "mass erase %s",
 552                         (retval == ERROR_OK) ? "successful" : "failed");
 553
 554         return retval;
 555 }
 556
 557 COMMAND_HANDLER(handle_esirisc_flash_ref_erase_command)
 558 {
 559         struct flash_bank *bank;
 560         int retval;
 561
 562         if (CMD_ARGC < 1)
 563                 return ERROR_COMMAND_SYNTAX_ERROR;
 564
 565         retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 566         if (retval != ERROR_OK)
 567                 return retval;
 568
 569         retval = esirisc_flash_ref_erase(bank);
 570
 571         command_print(CMD_CTX, "erase reference cell %s",
 572                         (retval == ERROR_OK) ? "successful" : "failed");
 573
 574         return retval;
 575 }
 576
 577 static const struct command_registration esirisc_flash_exec_command_handlers[] = {
 578         {
 579                 .name = "mass_erase",
 580                 .handler = handle_esirisc_flash_mass_erase_command,
 581                 .mode = COMMAND_EXEC,
 582                 .help = "erases all pages in data memory",
 583                 .usage = "bank_id",
 584         },
 585         {
 586                 .name = "ref_erase",
 587                 .handler = handle_esirisc_flash_ref_erase_command,
 588                 .mode = COMMAND_EXEC,
 589                 .help = "erases reference cell (uncommon)",
 590                 .usage = "bank_id",
 591         },
 592         COMMAND_REGISTRATION_DONE
 593 };
 594
 595 static const struct command_registration esirisc_flash_command_handlers[] = {
 596         {
 597                 .name = "esirisc_flash",
 598                 .mode = COMMAND_ANY,
 599                 .help = "eSi-RISC flash command group",
 600                 .usage = "",
 601                 .chain = esirisc_flash_exec_command_handlers,
 602         },
 603         COMMAND_REGISTRATION_DONE
 604 };
 605
 606 struct flash_driver esirisc_flash = {
 607         .name = "esirisc",
 608         .commands = esirisc_flash_command_handlers,
 609         .usage = "flash bank bank_id 'esirisc' base_address size_bytes 0 0 target "
 610                         "cfg_address clock_hz wait_states",
 611         .flash_bank_command = esirisc_flash_bank_command,
 612         .erase = esirisc_flash_erase,
 613         .protect = esirisc_flash_protect,
 614         .write = esirisc_flash_write,
 615         .read = default_flash_read,
 616         .probe = esirisc_flash_probe,
 617         .auto_probe = esirisc_flash_auto_probe,
 618         .erase_check = default_flash_blank_check,
 619         .protect_check = esirisc_flash_protect_check,
 620         .info = esirisc_flash_info,
 621 };