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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *                                                                         *
  11  *   Copyright (C) 2013 by Roman Dmitrienko                                *
  12  *   me@iamroman.org                                                       *
  13  *                                                                         *
  14  *   Copyright (C) 2014 Nemui Trinomius                                    *
  15  *   nemuisan_kawausogasuki@live.jp                                        *
  16  *                                                                         *
  17  *   This program is free software; you can redistribute it and/or modify  *
  18  *   it under the terms of the GNU General Public License as published by  *
  19  *   the Free Software Foundation; either version 2 of the License, or     *
  20  *   (at your option) any later version.                                   *
  21  *                                                                         *
  22  *   This program is distributed in the hope that it will be useful,       *
  23  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  24  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  25  *   GNU General Public License for more details.                          *
  26  *                                                                         *
  27  *   You should have received a copy of the GNU General Public License     *
  28  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  29  ***************************************************************************/
  30
  31 #ifdef HAVE_CONFIG_H
  32 #include "config.h"
  33 #endif
  34
  35 #include "imp.h"
  36 #include <helper/binarybuffer.h>
  37 #include <target/algorithm.h>
  38 #include <target/armv7m.h>
  39 #include <target/cortex_m.h>
  40
  41 #define EFM_FAMILY_ID_GIANT_GECKO       72
  42 #define EFM_FAMILY_ID_LEOPARD_GECKO     74
  43
  44 #define EFM32_FLASH_ERASE_TMO           100
  45 #define EFM32_FLASH_WDATAREADY_TMO      100
  46 #define EFM32_FLASH_WRITE_TMO           100
  47
  48 /* size in bytes, not words; must fit all Gecko devices */
  49 #define LOCKBITS_PAGE_SZ                512
  50
  51 #define EFM32_MSC_INFO_BASE             0x0fe00000
  52
  53 #define EFM32_MSC_USER_DATA             EFM32_MSC_INFO_BASE
  54 #define EFM32_MSC_LOCK_BITS             (EFM32_MSC_INFO_BASE+0x4000)
  55 #define EFM32_MSC_DEV_INFO              (EFM32_MSC_INFO_BASE+0x8000)
  56
  57 /* PAGE_SIZE is not present in Zero, Happy and the original Gecko MCU */
  58 #define EFM32_MSC_DI_PAGE_SIZE          (EFM32_MSC_DEV_INFO+0x1e7)
  59 #define EFM32_MSC_DI_FLASH_SZ           (EFM32_MSC_DEV_INFO+0x1f8)
  60 #define EFM32_MSC_DI_RAM_SZ             (EFM32_MSC_DEV_INFO+0x1fa)
  61 #define EFM32_MSC_DI_PART_NUM           (EFM32_MSC_DEV_INFO+0x1fc)
  62 #define EFM32_MSC_DI_PART_FAMILY        (EFM32_MSC_DEV_INFO+0x1fe)
  63 #define EFM32_MSC_DI_PROD_REV           (EFM32_MSC_DEV_INFO+0x1ff)
  64
  65 #define EFM32_MSC_REGBASE               0x400c0000
  66 #define EFM32_MSC_REGBASE_SERIES1       0x400e0000
  67 #define EFM32_MSC_REG_WRITECTRL         0x008
  68 #define EFM32_MSC_WRITECTRL_WREN_MASK   0x1
  69 #define EFM32_MSC_REG_WRITECMD          0x00c
  70 #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
  71 #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
  72 #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
  73 #define EFM32_MSC_REG_ADDRB             0x010
  74 #define EFM32_MSC_REG_WDATA             0x018
  75 #define EFM32_MSC_REG_STATUS            0x01c
  76 #define EFM32_MSC_STATUS_BUSY_MASK      0x1
  77 #define EFM32_MSC_STATUS_LOCKED_MASK    0x2
  78 #define EFM32_MSC_STATUS_INVADDR_MASK   0x4
  79 #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
  80 #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
  81 #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
  82 #define EFM32_MSC_REG_LOCK              0x03c
  83 #define EFM32_MSC_REG_LOCK_SERIES1      0x040
  84 #define EFM32_MSC_LOCK_LOCKKEY          0x1b71
  85
  86 struct efm32_family_data {
  87         int family_id;
  88         const char *name;
  89
  90         /* EFM32 series (EFM32LG995F is the "old" series 0, while EFR32MG12P132
  91            is the "new" series 1). Determines location of MSC registers. */
  92         int series;
  93
  94         /* Page size in bytes, or 0 to read from EFM32_MSC_DI_PAGE_SIZE */
  95         int page_size;
  96
  97         /* MSC register base address, or 0 to use default */
  98         uint32_t msc_regbase;
  99 };
 100
 101 struct efm32x_flash_bank {
 102         int probed;
 103         uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
 104         uint32_t reg_base;
 105         uint32_t reg_lock;
 106 };
 107
 108 struct efm32_info {
 109         const struct efm32_family_data *family_data;
 110         uint16_t flash_sz_kib;
 111         uint16_t ram_sz_kib;
 112         uint16_t part_num;
 113         uint8_t part_family;
 114         uint8_t prod_rev;
 115         uint16_t page_size;
 116 };
 117
 118 static const struct efm32_family_data efm32_families[] = {
 119                 { 16, "EFR32MG1P Mighty", .series = 1 },
 120                 { 17, "EFR32MG1B Mighty", .series = 1 },
 121                 { 18, "EFR32MG1V Mighty", .series = 1 },
 122                 { 19, "EFR32MG1P Blue", .series = 1 },
 123                 { 20, "EFR32MG1B Blue", .series = 1 },
 124                 { 21, "EFR32MG1V Blue", .series = 1 },
 125                 { 25, "EFR32FG1P Flex", .series = 1 },
 126                 { 26, "EFR32FG1B Flex", .series = 1 },
 127                 { 27, "EFR32FG1V Flex", .series = 1 },
 128                 { 28, "EFR32MG2P Mighty", .series = 1 },
 129                 { 29, "EFR32MG2B Mighty", .series = 1 },
 130                 { 30, "EFR32MG2V Mighty", .series = 1 },
 131                 { 31, "EFR32BG12P Blue", .series = 1 },
 132                 { 32, "EFR32BG12B Blue", .series = 1 },
 133                 { 33, "EFR32BG12V Blue", .series = 1 },
 134                 { 37, "EFR32FG12P Flex", .series = 1 },
 135                 { 38, "EFR32FG12B Flex", .series = 1 },
 136                 { 39, "EFR32FG12V Flex", .series = 1 },
 137                 { 40, "EFR32MG13P Mighty", .series = 1 },
 138                 { 41, "EFR32MG13B Mighty", .series = 1 },
 139                 { 42, "EFR32MG13V Mighty", .series = 1 },
 140                 { 43, "EFR32BG13P Blue", .series = 1 },
 141                 { 44, "EFR32BG13B Blue", .series = 1 },
 142                 { 45, "EFR32BG13V Blue", .series = 1 },
 143                 { 46, "EFR32ZG13P Zen", .series = 1 },
 144                 { 49, "EFR32FG13P Flex", .series = 1 },
 145                 { 50, "EFR32FG13B Flex", .series = 1 },
 146                 { 51, "EFR32FG13V Flex", .series = 1 },
 147                 { 52, "EFR32MG14P Mighty", .series = 1 },
 148                 { 53, "EFR32MG14B Mighty", .series = 1 },
 149                 { 54, "EFR32MG14V Mighty", .series = 1 },
 150                 { 55, "EFR32BG14P Blue", .series = 1 },
 151                 { 56, "EFR32BG14B Blue", .series = 1 },
 152                 { 57, "EFR32BG14V Blue", .series = 1 },
 153                 { 58, "EFR32ZG14P Zen", .series = 1 },
 154                 { 61, "EFR32FG14P Flex", .series = 1 },
 155                 { 62, "EFR32FG14B Flex", .series = 1 },
 156                 { 63, "EFR32FG14V Flex", .series = 1 },
 157                 { 71, "EFM32G", .series = 0, .page_size = 512 },
 158                 { 72, "EFM32GG Giant", .series = 0 },
 159                 { 73, "EFM32TG Tiny", .series = 0, .page_size = 512 },
 160                 { 74, "EFM32LG Leopard", .series = 0 },
 161                 { 75, "EFM32WG Wonder", .series = 0 },
 162                 { 76, "EFM32ZG Zero", .series = 0, .page_size = 1024 },
 163                 { 77, "EFM32HG Happy", .series = 0, .page_size = 1024 },
 164                 { 81, "EFM32PG1B Pearl", .series = 1 },
 165                 { 83, "EFM32JG1B Jade", .series = 1 },
 166                 { 85, "EFM32PG12B Pearl", .series = 1 },
 167                 { 87, "EFM32JG12B Jade", .series = 1 },
 168                 { 89, "EFM32PG13B Pearl", .series = 1 },
 169                 { 91, "EFM32JG13B Jade", .series = 1 },
 170                 { 100, "EFM32GG11B Giant", .series = 1, .msc_regbase = 0x40000000 },
 171                 { 103, "EFM32TG11B Tiny", .series = 1, .msc_regbase = 0x40000000 },
 172                 { 120, "EZR32WG Wonder", .series = 0 },
 173                 { 121, "EZR32LG Leopard", .series = 0 },
 174                 { 122, "EZR32HG Happy", .series = 0, .page_size = 1024 },
 175 };
 176
 177
 178 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 179         uint32_t offset, uint32_t count);
 180
 181 static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
 182 {
 183         return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
 184 }
 185
 186 static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
 187 {
 188         return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
 189 }
 190
 191 static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
 192 {
 193         return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
 194 }
 195
 196 static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
 197 {
 198         return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
 199 }
 200
 201 static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
 202 {
 203         return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
 204 }
 205
 206 static int efm32x_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
 207                                uint32_t *value)
 208 {
 209         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 210         uint32_t base = efm32x_info->reg_base;
 211
 212         return target_read_u32(bank->target, base + offset, value);
 213 }
 214
 215 static int efm32x_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
 216                                uint32_t value)
 217 {
 218         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 219         uint32_t base = efm32x_info->reg_base;
 220
 221         return target_write_u32(bank->target, base + offset, value);
 222 }
 223
 224 static int efm32x_read_info(struct flash_bank *bank,
 225         struct efm32_info *efm32_info)
 226 {
 227         int ret;
 228         uint32_t cpuid = 0;
 229         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 230
 231         memset(efm32_info, 0, sizeof(struct efm32_info));
 232
 233         ret = target_read_u32(bank->target, CPUID, &cpuid);
 234         if (ERROR_OK != ret)
 235                 return ret;
 236
 237         if (((cpuid >> 4) & 0xfff) == 0xc23) {
 238                 /* Cortex-M3 device */
 239         } else if (((cpuid >> 4) & 0xfff) == 0xc24) {
 240                 /* Cortex-M4 device (WONDER GECKO) */
 241         } else if (((cpuid >> 4) & 0xfff) == 0xc60) {
 242                 /* Cortex-M0+ device */
 243         } else {
 244                 LOG_ERROR("Target is not Cortex-Mx Device");
 245                 return ERROR_FAIL;
 246         }
 247
 248         ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
 249         if (ERROR_OK != ret)
 250                 return ret;
 251
 252         ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
 253         if (ERROR_OK != ret)
 254                 return ret;
 255
 256         ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
 257         if (ERROR_OK != ret)
 258                 return ret;
 259
 260         ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
 261         if (ERROR_OK != ret)
 262                 return ret;
 263
 264         ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
 265         if (ERROR_OK != ret)
 266                 return ret;
 267
 268         for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
 269                 if (efm32_families[i].family_id == efm32_info->part_family)
 270                         efm32_info->family_data = &efm32_families[i];
 271         }
 272
 273         if (efm32_info->family_data == NULL) {
 274                 LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
 275                 return ERROR_FAIL;
 276         }
 277
 278         switch (efm32_info->family_data->series) {
 279                 case 0:
 280                         efm32x_info->reg_base = EFM32_MSC_REGBASE;
 281                         efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
 282                         break;
 283                 case 1:
 284                         efm32x_info->reg_base = EFM32_MSC_REGBASE_SERIES1;
 285                         efm32x_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1;
 286                         break;
 287         }
 288
 289         if (efm32_info->family_data->msc_regbase != 0)
 290                 efm32x_info->reg_base = efm32_info->family_data->msc_regbase;
 291
 292         if (efm32_info->family_data->page_size != 0) {
 293                 efm32_info->page_size = efm32_info->family_data->page_size;
 294         } else {
 295                 uint8_t pg_size = 0;
 296                 ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
 297                         &pg_size);
 298                 if (ERROR_OK != ret)
 299                         return ret;
 300
 301                 efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
 302
 303                 if (efm32_info->part_family == EFM_FAMILY_ID_GIANT_GECKO ||
 304                                 efm32_info->part_family == EFM_FAMILY_ID_LEOPARD_GECKO) {
 305                         /* Giant or Leopard Gecko */
 306                         if (efm32_info->prod_rev < 18) {
 307                                 /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
 308                                    for MCUs with PROD_REV < 18 */
 309                                 if (efm32_info->flash_sz_kib < 512)
 310                                         efm32_info->page_size = 2048;
 311                                 else
 312                                         efm32_info->page_size = 4096;
 313                         }
 314                 }
 315
 316                 if ((efm32_info->page_size != 2048) &&
 317                                 (efm32_info->page_size != 4096)) {
 318                         LOG_ERROR("Invalid page size %u", efm32_info->page_size);
 319                         return ERROR_FAIL;
 320                 }
 321         }
 322
 323         return ERROR_OK;
 324 }
 325
 326 /*
 327  * Helper to create a human friendly string describing a part
 328  */
 329 static int efm32x_decode_info(struct efm32_info *info, char *buf, int buf_size)
 330 {
 331         int printed = 0;
 332         printed = snprintf(buf, buf_size, "%s Gecko, rev %d",
 333                         info->family_data->name, info->prod_rev);
 334
 335         if (printed >= buf_size)
 336                 return ERROR_BUF_TOO_SMALL;
 337
 338         return ERROR_OK;
 339 }
 340
 341 /* flash bank efm32 <base> <size> 0 0 <target#>
 342  */
 343 FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
 344 {
 345         struct efm32x_flash_bank *efm32x_info;
 346
 347         if (CMD_ARGC < 6)
 348                 return ERROR_COMMAND_SYNTAX_ERROR;
 349
 350         efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
 351
 352         bank->driver_priv = efm32x_info;
 353         efm32x_info->probed = 0;
 354         memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
 355
 356         return ERROR_OK;
 357 }
 358
 359 /* set or reset given bits in a register */
 360 static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
 361         uint32_t bitmask, int set)
 362 {
 363         int ret = 0;
 364         uint32_t reg_val = 0;
 365
 366         ret = efm32x_read_reg_u32(bank, reg, &reg_val);
 367         if (ERROR_OK != ret)
 368                 return ret;
 369
 370         if (set)
 371                 reg_val |= bitmask;
 372         else
 373                 reg_val &= ~bitmask;
 374
 375         return efm32x_write_reg_u32(bank, reg, reg_val);
 376 }
 377
 378 static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
 379 {
 380         return efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
 381                 EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
 382 }
 383
 384 static int efm32x_msc_lock(struct flash_bank *bank, int lock)
 385 {
 386         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 387         return efm32x_write_reg_u32(bank, efm32x_info->reg_lock,
 388                 (lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
 389 }
 390
 391 static int efm32x_wait_status(struct flash_bank *bank, int timeout,
 392         uint32_t wait_mask, int wait_for_set)
 393 {
 394         int ret = 0;
 395         uint32_t status = 0;
 396
 397         while (1) {
 398                 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 399                 if (ERROR_OK != ret)
 400                         break;
 401
 402                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 403
 404                 if (((status & wait_mask) == 0) && (0 == wait_for_set))
 405                         break;
 406                 else if (((status & wait_mask) != 0) && wait_for_set)
 407                         break;
 408
 409                 if (timeout-- <= 0) {
 410                         LOG_ERROR("timed out waiting for MSC status");
 411                         return ERROR_FAIL;
 412                 }
 413
 414                 alive_sleep(1);
 415         }
 416
 417         if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
 418                 LOG_WARNING("page erase was aborted");
 419
 420         return ret;
 421 }
 422
 423 static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
 424 {
 425         /* this function DOES NOT set WREN; must be set already */
 426         /* 1. write address to ADDRB
 427            2. write LADDRIM
 428            3. check status (INVADDR, LOCKED)
 429            4. write ERASEPAGE
 430            5. wait until !STATUS_BUSY
 431          */
 432         int ret = 0;
 433         uint32_t status = 0;
 434         addr += bank->base;
 435         LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
 436
 437         ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
 438         if (ERROR_OK != ret)
 439                 return ret;
 440
 441         ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
 442                 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 443         if (ERROR_OK != ret)
 444                 return ret;
 445
 446         ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 447         if (ERROR_OK != ret)
 448                 return ret;
 449
 450         LOG_DEBUG("status 0x%" PRIx32, status);
 451
 452         if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
 453                 LOG_ERROR("Page is locked");
 454                 return ERROR_FAIL;
 455         } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
 456                 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
 457                 return ERROR_FAIL;
 458         }
 459
 460         ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
 461                 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
 462         if (ERROR_OK != ret)
 463                 return ret;
 464
 465         return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
 466                 EFM32_MSC_STATUS_BUSY_MASK, 0);
 467 }
 468
 469 static int efm32x_erase(struct flash_bank *bank, int first, int last)
 470 {
 471         struct target *target = bank->target;
 472         int i = 0;
 473         int ret = 0;
 474
 475         if (TARGET_HALTED != target->state) {
 476                 LOG_ERROR("Target not halted");
 477                 return ERROR_TARGET_NOT_HALTED;
 478         }
 479
 480         efm32x_msc_lock(bank, 0);
 481         ret = efm32x_set_wren(bank, 1);
 482         if (ERROR_OK != ret) {
 483                 LOG_ERROR("Failed to enable MSC write");
 484                 return ret;
 485         }
 486
 487         for (i = first; i <= last; i++) {
 488                 ret = efm32x_erase_page(bank, bank->sectors[i].offset);
 489                 if (ERROR_OK != ret)
 490                         LOG_ERROR("Failed to erase page %d", i);
 491         }
 492
 493         ret = efm32x_set_wren(bank, 0);
 494         efm32x_msc_lock(bank, 1);
 495
 496         return ret;
 497 }
 498
 499 static int efm32x_read_lock_data(struct flash_bank *bank)
 500 {
 501         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 502         struct target *target = bank->target;
 503         int i = 0;
 504         int data_size = 0;
 505         uint32_t *ptr = NULL;
 506         int ret = 0;
 507
 508         assert(bank->num_sectors > 0);
 509
 510         /* calculate the number of 32-bit words to read (one lock bit per sector) */
 511         data_size = (bank->num_sectors + 31) / 32;
 512
 513         ptr = efm32x_info->lb_page;
 514
 515         for (i = 0; i < data_size; i++, ptr++) {
 516                 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
 517                 if (ERROR_OK != ret) {
 518                         LOG_ERROR("Failed to read PLW %d", i);
 519                         return ret;
 520                 }
 521         }
 522
 523         /* also, read ULW, DLW, MLW, ALW and CLW words */
 524
 525         /* ULW, word 126 */
 526         ptr = efm32x_info->lb_page + 126;
 527         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
 528         if (ERROR_OK != ret) {
 529                 LOG_ERROR("Failed to read ULW");
 530                 return ret;
 531         }
 532
 533         /* DLW, word 127 */
 534         ptr = efm32x_info->lb_page + 127;
 535         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
 536         if (ERROR_OK != ret) {
 537                 LOG_ERROR("Failed to read DLW");
 538                 return ret;
 539         }
 540
 541         /* MLW, word 125, present in GG, LG, PG, JG, EFR32 */
 542         ptr = efm32x_info->lb_page + 125;
 543         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
 544         if (ERROR_OK != ret) {
 545                 LOG_ERROR("Failed to read MLW");
 546                 return ret;
 547         }
 548
 549         /* ALW, word 124, present in GG, LG, PG, JG, EFR32 */
 550         ptr = efm32x_info->lb_page + 124;
 551         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+124*4, ptr);
 552         if (ERROR_OK != ret) {
 553                 LOG_ERROR("Failed to read ALW");
 554                 return ret;
 555         }
 556
 557         /* CLW1, word 123, present in EFR32 */
 558         ptr = efm32x_info->lb_page + 123;
 559         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+123*4, ptr);
 560         if (ERROR_OK != ret) {
 561                 LOG_ERROR("Failed to read CLW1");
 562                 return ret;
 563         }
 564
 565         /* CLW0, word 122, present in GG, LG, PG, JG, EFR32 */
 566         ptr = efm32x_info->lb_page + 122;
 567         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+122*4, ptr);
 568         if (ERROR_OK != ret) {
 569                 LOG_ERROR("Failed to read CLW0");
 570                 return ret;
 571         }
 572
 573         return ERROR_OK;
 574 }
 575
 576 static int efm32x_write_lock_data(struct flash_bank *bank)
 577 {
 578         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 579         int ret = 0;
 580
 581         ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
 582         if (ERROR_OK != ret) {
 583                 LOG_ERROR("Failed to erase LB page");
 584                 return ret;
 585         }
 586
 587         return efm32x_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS,
 588                 LOCKBITS_PAGE_SZ);
 589 }
 590
 591 static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
 592 {
 593         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 594         uint32_t dw = efm32x_info->lb_page[page >> 5];
 595         uint32_t mask = 0;
 596
 597         mask = 1 << (page & 0x1f);
 598
 599         return (dw & mask) ? 0 : 1;
 600 }
 601
 602 static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
 603 {
 604         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 605         uint32_t *dw = &efm32x_info->lb_page[page >> 5];
 606         uint32_t mask = 0;
 607
 608         mask = 1 << (page & 0x1f);
 609
 610         if (!set)
 611                 *dw |= mask;
 612         else
 613                 *dw &= ~mask;
 614
 615         return ERROR_OK;
 616 }
 617
 618 static int efm32x_protect(struct flash_bank *bank, int set, int first, int last)
 619 {
 620         struct target *target = bank->target;
 621         int i = 0;
 622         int ret = 0;
 623
 624         if (!set) {
 625                 LOG_ERROR("Erase device data to reset page locks");
 626                 return ERROR_FAIL;
 627         }
 628
 629         if (target->state != TARGET_HALTED) {
 630                 LOG_ERROR("Target not halted");
 631                 return ERROR_TARGET_NOT_HALTED;
 632         }
 633
 634         for (i = first; i <= last; i++) {
 635                 ret = efm32x_set_page_lock(bank, i, set);
 636                 if (ERROR_OK != ret) {
 637                         LOG_ERROR("Failed to set lock on page %d", i);
 638                         return ret;
 639                 }
 640         }
 641
 642         ret = efm32x_write_lock_data(bank);
 643         if (ERROR_OK != ret) {
 644                 LOG_ERROR("Failed to write LB page");
 645                 return ret;
 646         }
 647
 648         return ERROR_OK;
 649 }
 650
 651 static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
 652         uint32_t offset, uint32_t count)
 653 {
 654         struct target *target = bank->target;
 655         uint32_t buffer_size = 16384;
 656         struct working_area *write_algorithm;
 657         struct working_area *source;
 658         uint32_t address = bank->base + offset;
 659         struct reg_param reg_params[5];
 660         struct armv7m_algorithm armv7m_info;
 661         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 662         int ret = ERROR_OK;
 663
 664         /* see contrib/loaders/flash/efm32.S for src */
 665         static const uint8_t efm32x_flash_write_code[] = {
 666                 /* #define EFM32_MSC_WRITECTRL_OFFSET      0x008 */
 667                 /* #define EFM32_MSC_WRITECMD_OFFSET       0x00c */
 668                 /* #define EFM32_MSC_ADDRB_OFFSET          0x010 */
 669                 /* #define EFM32_MSC_WDATA_OFFSET          0x018 */
 670                 /* #define EFM32_MSC_STATUS_OFFSET         0x01c */
 671
 672                         0x01, 0x26,    /* movs    r6, #1 */
 673                         0x86, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
 674
 675                 /* wait_fifo: */
 676                         0x16, 0x68,    /* ldr     r6, [r2, #0] */
 677                         0x00, 0x2e,    /* cmp     r6, #0 */
 678                         0x22, 0xd0,    /* beq     exit */
 679                         0x55, 0x68,    /* ldr     r5, [r2, #4] */
 680                         0xb5, 0x42,    /* cmp     r5, r6 */
 681                         0xf9, 0xd0,    /* beq     wait_fifo */
 682
 683                         0x04, 0x61,    /* str     r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
 684                         0x01, 0x26,    /* movs    r6, #1 */
 685                         0xc6, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
 686                         0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
 687                         0x06, 0x27,    /* movs    r7, #6 */
 688                         0x3e, 0x42,    /* tst     r6, r7 */
 689                         0x16, 0xd1,    /* bne     error */
 690
 691                 /* wait_wdataready: */
 692                         0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
 693                         0x08, 0x27,    /* movs    r7, #8 */
 694                         0x3e, 0x42,    /* tst     r6, r7 */
 695                         0xfb, 0xd0,    /* beq     wait_wdataready */
 696
 697                         0x2e, 0x68,    /* ldr     r6, [r5] */
 698                         0x86, 0x61,    /* str     r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
 699                         0x08, 0x26,    /* movs    r6, #8 */
 700                         0xc6, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
 701
 702                         0x04, 0x35,    /* adds    r5, #4 */
 703                         0x04, 0x34,    /* adds    r4, #4 */
 704
 705                 /* busy: */
 706                         0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
 707                         0x01, 0x27,    /* movs    r7, #1 */
 708                         0x3e, 0x42,    /* tst     r6, r7 */
 709                         0xfb, 0xd1,    /* bne     busy */
 710
 711                         0x9d, 0x42,    /* cmp     r5, r3 */
 712                         0x01, 0xd3,    /* bcc     no_wrap */
 713                         0x15, 0x46,    /* mov     r5, r2 */
 714                         0x08, 0x35,    /* adds    r5, #8 */
 715
 716                 /* no_wrap: */
 717                         0x55, 0x60,    /* str     r5, [r2, #4] */
 718                         0x01, 0x39,    /* subs    r1, r1, #1 */
 719                         0x00, 0x29,    /* cmp     r1, #0 */
 720                         0x02, 0xd0,    /* beq     exit */
 721                         0xdb, 0xe7,    /* b       wait_fifo */
 722
 723                 /* error: */
 724                         0x00, 0x20,    /* movs    r0, #0 */
 725                         0x50, 0x60,    /* str     r0, [r2, #4] */
 726
 727                 /* exit: */
 728                         0x30, 0x46,    /* mov     r0, r6 */
 729                         0x00, 0xbe,    /* bkpt    #0 */
 730         };
 731
 732
 733         /* flash write code */
 734         if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
 735                         &write_algorithm) != ERROR_OK) {
 736                 LOG_WARNING("no working area available, can't do block memory writes");
 737                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 738         }
 739
 740         ret = target_write_buffer(target, write_algorithm->address,
 741                         sizeof(efm32x_flash_write_code), efm32x_flash_write_code);
 742         if (ret != ERROR_OK)
 743                 return ret;
 744
 745         /* memory buffer */
 746         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 747                 buffer_size /= 2;
 748                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 749                 if (buffer_size <= 256) {
 750                         /* we already allocated the writing code, but failed to get a
 751                          * buffer, free the algorithm */
 752                         target_free_working_area(target, write_algorithm);
 753
 754                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 755                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 756                 }
 757         }
 758
 759         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 760         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (word-32bit) */
 761         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 762         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 763         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 764
 765         buf_set_u32(reg_params[0].value, 0, 32, efm32x_info->reg_base);
 766         buf_set_u32(reg_params[1].value, 0, 32, count);
 767         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 768         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 769         buf_set_u32(reg_params[4].value, 0, 32, address);
 770
 771         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 772         armv7m_info.core_mode = ARM_MODE_THREAD;
 773
 774         ret = target_run_flash_async_algorithm(target, buf, count, 4,
 775                         0, NULL,
 776                         5, reg_params,
 777                         source->address, source->size,
 778                         write_algorithm->address, 0,
 779                         &armv7m_info);
 780
 781         if (ret == ERROR_FLASH_OPERATION_FAILED) {
 782                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 783                                 buf_get_u32(reg_params[4].value, 0, 32));
 784
 785                 if (buf_get_u32(reg_params[0].value, 0, 32) &
 786                                 EFM32_MSC_STATUS_LOCKED_MASK) {
 787                         LOG_ERROR("flash memory write protected");
 788                 }
 789
 790                 if (buf_get_u32(reg_params[0].value, 0, 32) &
 791                                 EFM32_MSC_STATUS_INVADDR_MASK) {
 792                         LOG_ERROR("invalid flash memory write address");
 793                 }
 794         }
 795
 796         target_free_working_area(target, source);
 797         target_free_working_area(target, write_algorithm);
 798
 799         destroy_reg_param(&reg_params[0]);
 800         destroy_reg_param(&reg_params[1]);
 801         destroy_reg_param(&reg_params[2]);
 802         destroy_reg_param(&reg_params[3]);
 803         destroy_reg_param(&reg_params[4]);
 804
 805         return ret;
 806 }
 807
 808 static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
 809         uint32_t val)
 810 {
 811         /* this function DOES NOT set WREN; must be set already */
 812         /* 1. write address to ADDRB
 813            2. write LADDRIM
 814            3. check status (INVADDR, LOCKED)
 815            4. wait for WDATAREADY
 816            5. write data to WDATA
 817            6. write WRITECMD_WRITEONCE to WRITECMD
 818            7. wait until !STATUS_BUSY
 819          */
 820
 821         /* FIXME: EFM32G ref states (7.3.2) that writes should be
 822          * performed twice per dword */
 823
 824         int ret = 0;
 825         uint32_t status = 0;
 826
 827         /* if not called, GDB errors will be reported during large writes */
 828         keep_alive();
 829
 830         ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
 831         if (ERROR_OK != ret)
 832                 return ret;
 833
 834         ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
 835                 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 836         if (ERROR_OK != ret)
 837                 return ret;
 838
 839         ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 840         if (ERROR_OK != ret)
 841                 return ret;
 842
 843         LOG_DEBUG("status 0x%" PRIx32, status);
 844
 845         if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
 846                 LOG_ERROR("Page is locked");
 847                 return ERROR_FAIL;
 848         } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
 849                 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
 850                 return ERROR_FAIL;
 851         }
 852
 853         ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
 854                 EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
 855         if (ERROR_OK != ret) {
 856                 LOG_ERROR("Wait for WDATAREADY failed");
 857                 return ret;
 858         }
 859
 860         ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
 861         if (ERROR_OK != ret) {
 862                 LOG_ERROR("WDATA write failed");
 863                 return ret;
 864         }
 865
 866         ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
 867                 EFM32_MSC_WRITECMD_WRITEONCE_MASK);
 868         if (ERROR_OK != ret) {
 869                 LOG_ERROR("WRITECMD write failed");
 870                 return ret;
 871         }
 872
 873         ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
 874                 EFM32_MSC_STATUS_BUSY_MASK, 0);
 875         if (ERROR_OK != ret) {
 876                 LOG_ERROR("Wait for BUSY failed");
 877                 return ret;
 878         }
 879
 880         return ERROR_OK;
 881 }
 882
 883 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 884                 uint32_t offset, uint32_t count)
 885 {
 886         struct target *target = bank->target;
 887         uint8_t *new_buffer = NULL;
 888
 889         if (target->state != TARGET_HALTED) {
 890                 LOG_ERROR("Target not halted");
 891                 return ERROR_TARGET_NOT_HALTED;
 892         }
 893
 894         if (offset & 0x3) {
 895                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte "
 896                         "alignment", offset);
 897                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 898         }
 899
 900         if (count & 0x3) {
 901                 uint32_t old_count = count;
 902                 count = (old_count | 3) + 1;
 903                 new_buffer = malloc(count);
 904                 if (new_buffer == NULL) {
 905                         LOG_ERROR("odd number of bytes to write and no memory "
 906                                 "for padding buffer");
 907                         return ERROR_FAIL;
 908                 }
 909                 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
 910                         "and padding with 0xff", old_count, count);
 911                 memset(new_buffer, 0xff, count);
 912                 buffer = memcpy(new_buffer, buffer, old_count);
 913         }
 914
 915         uint32_t words_remaining = count / 4;
 916         int retval, retval2;
 917
 918         /* unlock flash registers */
 919         efm32x_msc_lock(bank, 0);
 920         retval = efm32x_set_wren(bank, 1);
 921         if (retval != ERROR_OK)
 922                 goto cleanup;
 923
 924         /* try using a block write */
 925         retval = efm32x_write_block(bank, buffer, offset, words_remaining);
 926
 927         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 928                 /* if block write failed (no sufficient working area),
 929                  * we use normal (slow) single word accesses */
 930                 LOG_WARNING("couldn't use block writes, falling back to single "
 931                         "memory accesses");
 932
 933                 while (words_remaining > 0) {
 934                         uint32_t value;
 935                         memcpy(&value, buffer, sizeof(uint32_t));
 936
 937                         retval = efm32x_write_word(bank, offset, value);
 938                         if (retval != ERROR_OK)
 939                                 goto reset_pg_and_lock;
 940
 941                         words_remaining--;
 942                         buffer += 4;
 943                         offset += 4;
 944                 }
 945         }
 946
 947 reset_pg_and_lock:
 948         retval2 = efm32x_set_wren(bank, 0);
 949         efm32x_msc_lock(bank, 1);
 950         if (retval == ERROR_OK)
 951                 retval = retval2;
 952
 953 cleanup:
 954         if (new_buffer)
 955                 free(new_buffer);
 956
 957         return retval;
 958 }
 959
 960 static int efm32x_probe(struct flash_bank *bank)
 961 {
 962         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 963         struct efm32_info efm32_mcu_info;
 964         int ret;
 965         int i;
 966         uint32_t base_address = 0x00000000;
 967         char buf[256];
 968
 969         efm32x_info->probed = 0;
 970         memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
 971
 972         ret = efm32x_read_info(bank, &efm32_mcu_info);
 973         if (ERROR_OK != ret)
 974                 return ret;
 975
 976         ret = efm32x_decode_info(&efm32_mcu_info, buf, sizeof(buf));
 977         if (ERROR_OK != ret)
 978                 return ret;
 979
 980         LOG_INFO("detected part: %s", buf);
 981         LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
 982         LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
 983
 984         assert(0 != efm32_mcu_info.page_size);
 985
 986         int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
 987                 efm32_mcu_info.page_size;
 988
 989         assert(num_pages > 0);
 990
 991         if (bank->sectors) {
 992                 free(bank->sectors);
 993                 bank->sectors = NULL;
 994         }
 995
 996         bank->base = base_address;
 997         bank->size = (num_pages * efm32_mcu_info.page_size);
 998         bank->num_sectors = num_pages;
 999
1000         ret = efm32x_read_lock_data(bank);
1001         if (ERROR_OK != ret) {
1002                 LOG_ERROR("Failed to read LB data");
1003                 return ret;
1004         }
1005
1006         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1007
1008         for (i = 0; i < num_pages; i++) {
1009                 bank->sectors[i].offset = i * efm32_mcu_info.page_size;
1010                 bank->sectors[i].size = efm32_mcu_info.page_size;
1011                 bank->sectors[i].is_erased = -1;
1012                 bank->sectors[i].is_protected = 1;
1013         }
1014
1015         efm32x_info->probed = 1;
1016
1017         return ERROR_OK;
1018 }
1019
1020 static int efm32x_auto_probe(struct flash_bank *bank)
1021 {
1022         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
1023         if (efm32x_info->probed)
1024                 return ERROR_OK;
1025         return efm32x_probe(bank);
1026 }
1027
1028 static int efm32x_protect_check(struct flash_bank *bank)
1029 {
1030         struct target *target = bank->target;
1031         int ret = 0;
1032         int i = 0;
1033
1034         if (target->state != TARGET_HALTED) {
1035                 LOG_ERROR("Target not halted");
1036                 return ERROR_TARGET_NOT_HALTED;
1037         }
1038
1039         ret = efm32x_read_lock_data(bank);
1040         if (ERROR_OK != ret) {
1041                 LOG_ERROR("Failed to read LB data");
1042                 return ret;
1043         }
1044
1045         assert(NULL != bank->sectors);
1046
1047         for (i = 0; i < bank->num_sectors; i++)
1048                 bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
1049
1050         return ERROR_OK;
1051 }
1052
1053 static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1054 {
1055         struct efm32_info info;
1056         int ret = 0;
1057
1058         ret = efm32x_read_info(bank, &info);
1059         if (ERROR_OK != ret) {
1060                 LOG_ERROR("Failed to read EFM32 info");
1061                 return ret;
1062         }
1063
1064         return efm32x_decode_info(&info, buf, buf_size);
1065 }
1066
1067 COMMAND_HANDLER(efm32x_handle_debuglock_command)
1068 {
1069         struct target *target = NULL;
1070
1071         if (CMD_ARGC < 1)
1072                 return ERROR_COMMAND_SYNTAX_ERROR;
1073
1074         struct flash_bank *bank;
1075         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1076         if (ERROR_OK != retval)
1077                 return retval;
1078
1079         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
1080
1081         target = bank->target;
1082
1083         if (target->state != TARGET_HALTED) {
1084                 LOG_ERROR("Target not halted");
1085                 return ERROR_TARGET_NOT_HALTED;
1086         }
1087
1088         uint32_t *ptr;
1089         ptr = efm32x_info->lb_page + 127;
1090         *ptr = 0;
1091
1092         retval = efm32x_write_lock_data(bank);
1093         if (ERROR_OK != retval) {
1094                 LOG_ERROR("Failed to write LB page");
1095                 return retval;
1096         }
1097
1098         command_print(CMD, "efm32x debug interface locked, reset the device to apply");
1099
1100         return ERROR_OK;
1101 }
1102
1103 static const struct command_registration efm32x_exec_command_handlers[] = {
1104         {
1105                 .name = "debuglock",
1106                 .handler = efm32x_handle_debuglock_command,
1107                 .mode = COMMAND_EXEC,
1108                 .usage = "bank_id",
1109                 .help = "Lock the debug interface of the device.",
1110         },
1111         COMMAND_REGISTRATION_DONE
1112 };
1113
1114 static const struct command_registration efm32x_command_handlers[] = {
1115         {
1116                 .name = "efm32",
1117                 .mode = COMMAND_ANY,
1118                 .help = "efm32 flash command group",
1119                 .usage = "",
1120                 .chain = efm32x_exec_command_handlers,
1121         },
1122         COMMAND_REGISTRATION_DONE
1123 };
1124
1125 const struct flash_driver efm32_flash = {
1126         .name = "efm32",
1127         .commands = efm32x_command_handlers,
1128         .flash_bank_command = efm32x_flash_bank_command,
1129         .erase = efm32x_erase,
1130         .protect = efm32x_protect,
1131         .write = efm32x_write,
1132         .read = default_flash_read,
1133         .probe = efm32x_probe,
1134         .auto_probe = efm32x_auto_probe,
1135         .erase_check = default_flash_blank_check,
1136         .protect_check = efm32x_protect_check,
1137         .info = get_efm32x_info,
1138         .free_driver_priv = default_flash_free_driver_priv,
1139 };