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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *                                                                         *
  11  *   Copyright (C) 2013 by Roman Dmitrienko                                *
  12  *   me@iamroman.org                                                       *
  13  *                                                                         *
  14  *   Copyright (C) 2014 Nemui Trinomius                                    *
  15  *   nemuisan_kawausogasuki@live.jp                                        *
  16  *                                                                         *
  17  *   This program is free software; you can redistribute it and/or modify  *
  18  *   it under the terms of the GNU General Public License as published by  *
  19  *   the Free Software Foundation; either version 2 of the License, or     *
  20  *   (at your option) any later version.                                   *
  21  *                                                                         *
  22  *   This program is distributed in the hope that it will be useful,       *
  23  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  24  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  25  *   GNU General Public License for more details.                          *
  26  *                                                                         *
  27  *   You should have received a copy of the GNU General Public License     *
  28  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  29  ***************************************************************************/
  30
  31 #ifdef HAVE_CONFIG_H
  32 #include "config.h"
  33 #endif
  34
  35 #include "imp.h"
  36 #include <helper/binarybuffer.h>
  37 #include <target/algorithm.h>
  38 #include <target/armv7m.h>
  39 #include <target/cortex_m.h>
  40
  41 #define EFM_FAMILY_ID_GIANT_GECKO       72
  42 #define EFM_FAMILY_ID_LEOPARD_GECKO     74
  43
  44 #define EFM32_FLASH_ERASE_TMO           100
  45 #define EFM32_FLASH_WDATAREADY_TMO      100
  46 #define EFM32_FLASH_WRITE_TMO           100
  47
  48 /* size in bytes, not words; must fit all Gecko devices */
  49 #define LOCKBITS_PAGE_SZ                512
  50
  51 #define EFM32_MSC_INFO_BASE             0x0fe00000
  52
  53 #define EFM32_MSC_USER_DATA             EFM32_MSC_INFO_BASE
  54 #define EFM32_MSC_LOCK_BITS             (EFM32_MSC_INFO_BASE+0x4000)
  55 #define EFM32_MSC_DEV_INFO              (EFM32_MSC_INFO_BASE+0x8000)
  56
  57 /* PAGE_SIZE is not present in Zero, Happy and the original Gecko MCU */
  58 #define EFM32_MSC_DI_PAGE_SIZE          (EFM32_MSC_DEV_INFO+0x1e7)
  59 #define EFM32_MSC_DI_FLASH_SZ           (EFM32_MSC_DEV_INFO+0x1f8)
  60 #define EFM32_MSC_DI_RAM_SZ             (EFM32_MSC_DEV_INFO+0x1fa)
  61 #define EFM32_MSC_DI_PART_NUM           (EFM32_MSC_DEV_INFO+0x1fc)
  62 #define EFM32_MSC_DI_PART_FAMILY        (EFM32_MSC_DEV_INFO+0x1fe)
  63 #define EFM32_MSC_DI_PROD_REV           (EFM32_MSC_DEV_INFO+0x1ff)
  64
  65 #define EFM32_MSC_REGBASE               0x400c0000
  66 #define EFM32_MSC_REGBASE_SERIES1       0x400e0000
  67 #define EFM32_MSC_REG_WRITECTRL         0x008
  68 #define EFM32_MSC_WRITECTRL_WREN_MASK   0x1
  69 #define EFM32_MSC_REG_WRITECMD          0x00c
  70 #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
  71 #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
  72 #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
  73 #define EFM32_MSC_REG_ADDRB             0x010
  74 #define EFM32_MSC_REG_WDATA             0x018
  75 #define EFM32_MSC_REG_STATUS            0x01c
  76 #define EFM32_MSC_STATUS_BUSY_MASK      0x1
  77 #define EFM32_MSC_STATUS_LOCKED_MASK    0x2
  78 #define EFM32_MSC_STATUS_INVADDR_MASK   0x4
  79 #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
  80 #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
  81 #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
  82 #define EFM32_MSC_REG_LOCK              0x03c
  83 #define EFM32_MSC_REG_LOCK_SERIES1      0x040
  84 #define EFM32_MSC_LOCK_LOCKKEY          0x1b71
  85
  86 struct efm32_family_data {
  87         int family_id;
  88         const char *name;
  89
  90         /* EFM32 series (EFM32LG995F is the "old" series 0, while EFR32MG12P132
  91            is the "new" series 1). Determines location of MSC registers. */
  92         int series;
  93
  94         /* Page size in bytes, or 0 to read from EFM32_MSC_DI_PAGE_SIZE */
  95         int page_size;
  96
  97         /* MSC register base address, or 0 to use default */
  98         uint32_t msc_regbase;
  99 };
 100
 101 struct efm32x_flash_bank {
 102         int probed;
 103         uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
 104         uint32_t reg_base;
 105         uint32_t reg_lock;
 106 };
 107
 108 struct efm32_info {
 109         const struct efm32_family_data *family_data;
 110         uint16_t flash_sz_kib;
 111         uint16_t ram_sz_kib;
 112         uint16_t part_num;
 113         uint8_t part_family;
 114         uint8_t prod_rev;
 115         uint16_t page_size;
 116 };
 117
 118 static const struct efm32_family_data efm32_families[] = {
 119                 { 16, "EFR32MG1P Mighty", .series = 1 },
 120                 { 17, "EFR32MG1B Mighty", .series = 1 },
 121                 { 18, "EFR32MG1V Mighty", .series = 1 },
 122                 { 19, "EFR32MG1P Blue", .series = 1 },
 123                 { 20, "EFR32MG1B Blue", .series = 1 },
 124                 { 21, "EFR32MG1V Blue", .series = 1 },
 125                 { 25, "EFR32FG1P Flex", .series = 1 },
 126                 { 26, "EFR32FG1B Flex", .series = 1 },
 127                 { 27, "EFR32FG1V Flex", .series = 1 },
 128                 { 28, "EFR32MG2P Mighty", .series = 1 },
 129                 { 29, "EFR32MG2B Mighty", .series = 1 },
 130                 { 30, "EFR32MG2V Mighty", .series = 1 },
 131                 { 31, "EFR32BG12P Blue", .series = 1 },
 132                 { 32, "EFR32BG12B Blue", .series = 1 },
 133                 { 33, "EFR32BG12V Blue", .series = 1 },
 134                 { 37, "EFR32FG12P Flex", .series = 1 },
 135                 { 38, "EFR32FG12B Flex", .series = 1 },
 136                 { 39, "EFR32FG12V Flex", .series = 1 },
 137                 { 40, "EFR32MG13P Mighty", .series = 1 },
 138                 { 41, "EFR32MG13B Mighty", .series = 1 },
 139                 { 42, "EFR32MG13V Mighty", .series = 1 },
 140                 { 43, "EFR32BG13P Blue", .series = 1 },
 141                 { 44, "EFR32BG13B Blue", .series = 1 },
 142                 { 45, "EFR32BG13V Blue", .series = 1 },
 143                 { 49, "EFR32FG13P Flex", .series = 1 },
 144                 { 50, "EFR32FG13B Flex", .series = 1 },
 145                 { 51, "EFR32FG13V Flex", .series = 1 },
 146                 { 52, "EFR32MG14P Mighty", .series = 1 },
 147                 { 53, "EFR32MG14B Mighty", .series = 1 },
 148                 { 54, "EFR32MG14V Mighty", .series = 1 },
 149                 { 55, "EFR32BG14P Blue", .series = 1 },
 150                 { 56, "EFR32BG14B Blue", .series = 1 },
 151                 { 57, "EFR32BG14V Blue", .series = 1 },
 152                 { 61, "EFR32FG14P Flex", .series = 1 },
 153                 { 62, "EFR32FG14B Flex", .series = 1 },
 154                 { 63, "EFR32FG14V Flex", .series = 1 },
 155                 { 71, "EFM32G", .series = 0, .page_size = 512 },
 156                 { 72, "EFM32GG Giant", .series = 0 },
 157                 { 73, "EFM32TG Tiny", .series = 0, .page_size = 512 },
 158                 { 74, "EFM32LG Leopard", .series = 0 },
 159                 { 75, "EFM32WG Wonder", .series = 0 },
 160                 { 76, "EFM32ZG Zero", .series = 0, .page_size = 1024 },
 161                 { 77, "EFM32HG Happy", .series = 0, .page_size = 1024 },
 162                 { 81, "EFM32PG1B Pearl", .series = 1 },
 163                 { 83, "EFM32JG1B Jade", .series = 1 },
 164                 { 85, "EFM32PG12B Pearl", .series = 1 },
 165                 { 87, "EFM32JG12B Jade", .series = 1 },
 166                 { 89, "EFM32PG13B Pearl", .series = 1 },
 167                 { 91, "EFM32JG13B Jade", .series = 1 },
 168                 { 100, "EFM32GG11B Giant", .series = 1, .msc_regbase = 0x40000000 },
 169                 { 103, "EFM32TG11B Tiny", .series = 1, .msc_regbase = 0x40000000 },
 170                 { 120, "EZR32WG Wonder", .series = 0 },
 171                 { 121, "EZR32LG Leopard", .series = 0 },
 172                 { 122, "EZR32HG Happy", .series = 0, .page_size = 1024 },
 173 };
 174
 175
 176 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 177         uint32_t offset, uint32_t count);
 178
 179 static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
 180 {
 181         return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
 182 }
 183
 184 static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
 185 {
 186         return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
 187 }
 188
 189 static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
 190 {
 191         return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
 192 }
 193
 194 static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
 195 {
 196         return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
 197 }
 198
 199 static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
 200 {
 201         return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
 202 }
 203
 204 static int efm32x_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
 205                                uint32_t *value)
 206 {
 207         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 208         uint32_t base = efm32x_info->reg_base;
 209
 210         return target_read_u32(bank->target, base + offset, value);
 211 }
 212
 213 static int efm32x_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
 214                                uint32_t value)
 215 {
 216         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 217         uint32_t base = efm32x_info->reg_base;
 218
 219         return target_write_u32(bank->target, base + offset, value);
 220 }
 221
 222 static int efm32x_read_info(struct flash_bank *bank,
 223         struct efm32_info *efm32_info)
 224 {
 225         int ret;
 226         uint32_t cpuid = 0;
 227         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 228
 229         memset(efm32_info, 0, sizeof(struct efm32_info));
 230
 231         ret = target_read_u32(bank->target, CPUID, &cpuid);
 232         if (ERROR_OK != ret)
 233                 return ret;
 234
 235         if (((cpuid >> 4) & 0xfff) == 0xc23) {
 236                 /* Cortex-M3 device */
 237         } else if (((cpuid >> 4) & 0xfff) == 0xc24) {
 238                 /* Cortex-M4 device (WONDER GECKO) */
 239         } else if (((cpuid >> 4) & 0xfff) == 0xc60) {
 240                 /* Cortex-M0+ device */
 241         } else {
 242                 LOG_ERROR("Target is not Cortex-Mx Device");
 243                 return ERROR_FAIL;
 244         }
 245
 246         ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
 247         if (ERROR_OK != ret)
 248                 return ret;
 249
 250         ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
 251         if (ERROR_OK != ret)
 252                 return ret;
 253
 254         ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
 255         if (ERROR_OK != ret)
 256                 return ret;
 257
 258         ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
 259         if (ERROR_OK != ret)
 260                 return ret;
 261
 262         ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
 263         if (ERROR_OK != ret)
 264                 return ret;
 265
 266         for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
 267                 if (efm32_families[i].family_id == efm32_info->part_family)
 268                         efm32_info->family_data = &efm32_families[i];
 269         }
 270
 271         if (efm32_info->family_data == NULL) {
 272                 LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
 273                 return ERROR_FAIL;
 274         }
 275
 276         switch (efm32_info->family_data->series) {
 277                 case 0:
 278                         efm32x_info->reg_base = EFM32_MSC_REGBASE;
 279                         efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
 280                         break;
 281                 case 1:
 282                         efm32x_info->reg_base = EFM32_MSC_REGBASE_SERIES1;
 283                         efm32x_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1;
 284                         break;
 285         }
 286
 287         if (efm32_info->family_data->msc_regbase != 0)
 288                 efm32x_info->reg_base = efm32_info->family_data->msc_regbase;
 289
 290         if (efm32_info->family_data->page_size != 0) {
 291                 efm32_info->page_size = efm32_info->family_data->page_size;
 292         } else {
 293                 uint8_t pg_size = 0;
 294                 ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
 295                         &pg_size);
 296                 if (ERROR_OK != ret)
 297                         return ret;
 298
 299                 efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
 300
 301                 if (efm32_info->part_family == EFM_FAMILY_ID_GIANT_GECKO ||
 302                                 efm32_info->part_family == EFM_FAMILY_ID_LEOPARD_GECKO) {
 303                         /* Giant or Leopard Gecko */
 304                         if (efm32_info->prod_rev < 18) {
 305                                 /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
 306                                    for MCUs with PROD_REV < 18 */
 307                                 if (efm32_info->flash_sz_kib < 512)
 308                                         efm32_info->page_size = 2048;
 309                                 else
 310                                         efm32_info->page_size = 4096;
 311                         }
 312                 }
 313
 314                 if ((efm32_info->page_size != 2048) &&
 315                                 (efm32_info->page_size != 4096)) {
 316                         LOG_ERROR("Invalid page size %u", efm32_info->page_size);
 317                         return ERROR_FAIL;
 318                 }
 319         }
 320
 321         return ERROR_OK;
 322 }
 323
 324 /*
 325  * Helper to create a human friendly string describing a part
 326  */
 327 static int efm32x_decode_info(struct efm32_info *info, char *buf, int buf_size)
 328 {
 329         int printed = 0;
 330         printed = snprintf(buf, buf_size, "%s Gecko, rev %d",
 331                         info->family_data->name, info->prod_rev);
 332
 333         if (printed >= buf_size)
 334                 return ERROR_BUF_TOO_SMALL;
 335
 336         return ERROR_OK;
 337 }
 338
 339 /* flash bank efm32 <base> <size> 0 0 <target#>
 340  */
 341 FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
 342 {
 343         struct efm32x_flash_bank *efm32x_info;
 344
 345         if (CMD_ARGC < 6)
 346                 return ERROR_COMMAND_SYNTAX_ERROR;
 347
 348         efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
 349
 350         bank->driver_priv = efm32x_info;
 351         efm32x_info->probed = 0;
 352         memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
 353
 354         return ERROR_OK;
 355 }
 356
 357 /* set or reset given bits in a register */
 358 static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
 359         uint32_t bitmask, int set)
 360 {
 361         int ret = 0;
 362         uint32_t reg_val = 0;
 363
 364         ret = efm32x_read_reg_u32(bank, reg, &reg_val);
 365         if (ERROR_OK != ret)
 366                 return ret;
 367
 368         if (set)
 369                 reg_val |= bitmask;
 370         else
 371                 reg_val &= ~bitmask;
 372
 373         return efm32x_write_reg_u32(bank, reg, reg_val);
 374 }
 375
 376 static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
 377 {
 378         return efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
 379                 EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
 380 }
 381
 382 static int efm32x_msc_lock(struct flash_bank *bank, int lock)
 383 {
 384         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 385         return efm32x_write_reg_u32(bank, efm32x_info->reg_lock,
 386                 (lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
 387 }
 388
 389 static int efm32x_wait_status(struct flash_bank *bank, int timeout,
 390         uint32_t wait_mask, int wait_for_set)
 391 {
 392         int ret = 0;
 393         uint32_t status = 0;
 394
 395         while (1) {
 396                 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 397                 if (ERROR_OK != ret)
 398                         break;
 399
 400                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 401
 402                 if (((status & wait_mask) == 0) && (0 == wait_for_set))
 403                         break;
 404                 else if (((status & wait_mask) != 0) && wait_for_set)
 405                         break;
 406
 407                 if (timeout-- <= 0) {
 408                         LOG_ERROR("timed out waiting for MSC status");
 409                         return ERROR_FAIL;
 410                 }
 411
 412                 alive_sleep(1);
 413         }
 414
 415         if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
 416                 LOG_WARNING("page erase was aborted");
 417
 418         return ret;
 419 }
 420
 421 static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
 422 {
 423         /* this function DOES NOT set WREN; must be set already */
 424         /* 1. write address to ADDRB
 425            2. write LADDRIM
 426            3. check status (INVADDR, LOCKED)
 427            4. write ERASEPAGE
 428            5. wait until !STATUS_BUSY
 429          */
 430         int ret = 0;
 431         uint32_t status = 0;
 432         addr += bank->base;
 433         LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
 434
 435         ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
 436         if (ERROR_OK != ret)
 437                 return ret;
 438
 439         ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
 440                 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 441         if (ERROR_OK != ret)
 442                 return ret;
 443
 444         ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 445         if (ERROR_OK != ret)
 446                 return ret;
 447
 448         LOG_DEBUG("status 0x%" PRIx32, status);
 449
 450         if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
 451                 LOG_ERROR("Page is locked");
 452                 return ERROR_FAIL;
 453         } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
 454                 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
 455                 return ERROR_FAIL;
 456         }
 457
 458         ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
 459                 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
 460         if (ERROR_OK != ret)
 461                 return ret;
 462
 463         return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
 464                 EFM32_MSC_STATUS_BUSY_MASK, 0);
 465 }
 466
 467 static int efm32x_erase(struct flash_bank *bank, int first, int last)
 468 {
 469         struct target *target = bank->target;
 470         int i = 0;
 471         int ret = 0;
 472
 473         if (TARGET_HALTED != target->state) {
 474                 LOG_ERROR("Target not halted");
 475                 return ERROR_TARGET_NOT_HALTED;
 476         }
 477
 478         efm32x_msc_lock(bank, 0);
 479         ret = efm32x_set_wren(bank, 1);
 480         if (ERROR_OK != ret) {
 481                 LOG_ERROR("Failed to enable MSC write");
 482                 return ret;
 483         }
 484
 485         for (i = first; i <= last; i++) {
 486                 ret = efm32x_erase_page(bank, bank->sectors[i].offset);
 487                 if (ERROR_OK != ret)
 488                         LOG_ERROR("Failed to erase page %d", i);
 489         }
 490
 491         ret = efm32x_set_wren(bank, 0);
 492         efm32x_msc_lock(bank, 1);
 493
 494         return ret;
 495 }
 496
 497 static int efm32x_read_lock_data(struct flash_bank *bank)
 498 {
 499         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 500         struct target *target = bank->target;
 501         int i = 0;
 502         int data_size = 0;
 503         uint32_t *ptr = NULL;
 504         int ret = 0;
 505
 506         assert(bank->num_sectors > 0);
 507
 508         /* calculate the number of 32-bit words to read (one lock bit per sector) */
 509         data_size = (bank->num_sectors + 31) / 32;
 510
 511         ptr = efm32x_info->lb_page;
 512
 513         for (i = 0; i < data_size; i++, ptr++) {
 514                 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
 515                 if (ERROR_OK != ret) {
 516                         LOG_ERROR("Failed to read PLW %d", i);
 517                         return ret;
 518                 }
 519         }
 520
 521         /* also, read ULW, DLW, MLW, ALW and CLW words */
 522
 523         /* ULW, word 126 */
 524         ptr = efm32x_info->lb_page + 126;
 525         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
 526         if (ERROR_OK != ret) {
 527                 LOG_ERROR("Failed to read ULW");
 528                 return ret;
 529         }
 530
 531         /* DLW, word 127 */
 532         ptr = efm32x_info->lb_page + 127;
 533         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
 534         if (ERROR_OK != ret) {
 535                 LOG_ERROR("Failed to read DLW");
 536                 return ret;
 537         }
 538
 539         /* MLW, word 125, present in GG, LG, PG, JG, EFR32 */
 540         ptr = efm32x_info->lb_page + 125;
 541         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
 542         if (ERROR_OK != ret) {
 543                 LOG_ERROR("Failed to read MLW");
 544                 return ret;
 545         }
 546
 547         /* ALW, word 124, present in GG, LG, PG, JG, EFR32 */
 548         ptr = efm32x_info->lb_page + 124;
 549         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+124*4, ptr);
 550         if (ERROR_OK != ret) {
 551                 LOG_ERROR("Failed to read ALW");
 552                 return ret;
 553         }
 554
 555         /* CLW1, word 123, present in EFR32 */
 556         ptr = efm32x_info->lb_page + 123;
 557         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+123*4, ptr);
 558         if (ERROR_OK != ret) {
 559                 LOG_ERROR("Failed to read CLW1");
 560                 return ret;
 561         }
 562
 563         /* CLW0, word 122, present in GG, LG, PG, JG, EFR32 */
 564         ptr = efm32x_info->lb_page + 122;
 565         ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+122*4, ptr);
 566         if (ERROR_OK != ret) {
 567                 LOG_ERROR("Failed to read CLW0");
 568                 return ret;
 569         }
 570
 571         return ERROR_OK;
 572 }
 573
 574 static int efm32x_write_lock_data(struct flash_bank *bank)
 575 {
 576         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 577         int ret = 0;
 578
 579         ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
 580         if (ERROR_OK != ret) {
 581                 LOG_ERROR("Failed to erase LB page");
 582                 return ret;
 583         }
 584
 585         return efm32x_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS,
 586                 LOCKBITS_PAGE_SZ);
 587 }
 588
 589 static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
 590 {
 591         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 592         uint32_t dw = efm32x_info->lb_page[page >> 5];
 593         uint32_t mask = 0;
 594
 595         mask = 1 << (page & 0x1f);
 596
 597         return (dw & mask) ? 0 : 1;
 598 }
 599
 600 static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
 601 {
 602         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 603         uint32_t *dw = &efm32x_info->lb_page[page >> 5];
 604         uint32_t mask = 0;
 605
 606         mask = 1 << (page & 0x1f);
 607
 608         if (!set)
 609                 *dw |= mask;
 610         else
 611                 *dw &= ~mask;
 612
 613         return ERROR_OK;
 614 }
 615
 616 static int efm32x_protect(struct flash_bank *bank, int set, int first, int last)
 617 {
 618         struct target *target = bank->target;
 619         int i = 0;
 620         int ret = 0;
 621
 622         if (!set) {
 623                 LOG_ERROR("Erase device data to reset page locks");
 624                 return ERROR_FAIL;
 625         }
 626
 627         if (target->state != TARGET_HALTED) {
 628                 LOG_ERROR("Target not halted");
 629                 return ERROR_TARGET_NOT_HALTED;
 630         }
 631
 632         for (i = first; i <= last; i++) {
 633                 ret = efm32x_set_page_lock(bank, i, set);
 634                 if (ERROR_OK != ret) {
 635                         LOG_ERROR("Failed to set lock on page %d", i);
 636                         return ret;
 637                 }
 638         }
 639
 640         ret = efm32x_write_lock_data(bank);
 641         if (ERROR_OK != ret) {
 642                 LOG_ERROR("Failed to write LB page");
 643                 return ret;
 644         }
 645
 646         return ERROR_OK;
 647 }
 648
 649 static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
 650         uint32_t offset, uint32_t count)
 651 {
 652         struct target *target = bank->target;
 653         uint32_t buffer_size = 16384;
 654         struct working_area *write_algorithm;
 655         struct working_area *source;
 656         uint32_t address = bank->base + offset;
 657         struct reg_param reg_params[5];
 658         struct armv7m_algorithm armv7m_info;
 659         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 660         int ret = ERROR_OK;
 661
 662         /* see contrib/loaders/flash/efm32.S for src */
 663         static const uint8_t efm32x_flash_write_code[] = {
 664                 /* #define EFM32_MSC_WRITECTRL_OFFSET      0x008 */
 665                 /* #define EFM32_MSC_WRITECMD_OFFSET       0x00c */
 666                 /* #define EFM32_MSC_ADDRB_OFFSET          0x010 */
 667                 /* #define EFM32_MSC_WDATA_OFFSET          0x018 */
 668                 /* #define EFM32_MSC_STATUS_OFFSET         0x01c */
 669
 670                         0x01, 0x26,    /* movs    r6, #1 */
 671                         0x86, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
 672
 673                 /* wait_fifo: */
 674                         0x16, 0x68,    /* ldr     r6, [r2, #0] */
 675                         0x00, 0x2e,    /* cmp     r6, #0 */
 676                         0x22, 0xd0,    /* beq     exit */
 677                         0x55, 0x68,    /* ldr     r5, [r2, #4] */
 678                         0xb5, 0x42,    /* cmp     r5, r6 */
 679                         0xf9, 0xd0,    /* beq     wait_fifo */
 680
 681                         0x04, 0x61,    /* str     r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
 682                         0x01, 0x26,    /* movs    r6, #1 */
 683                         0xc6, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
 684                         0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
 685                         0x06, 0x27,    /* movs    r7, #6 */
 686                         0x3e, 0x42,    /* tst     r6, r7 */
 687                         0x16, 0xd1,    /* bne     error */
 688
 689                 /* wait_wdataready: */
 690                         0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
 691                         0x08, 0x27,    /* movs    r7, #8 */
 692                         0x3e, 0x42,    /* tst     r6, r7 */
 693                         0xfb, 0xd0,    /* beq     wait_wdataready */
 694
 695                         0x2e, 0x68,    /* ldr     r6, [r5] */
 696                         0x86, 0x61,    /* str     r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
 697                         0x08, 0x26,    /* movs    r6, #8 */
 698                         0xc6, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
 699
 700                         0x04, 0x35,    /* adds    r5, #4 */
 701                         0x04, 0x34,    /* adds    r4, #4 */
 702
 703                 /* busy: */
 704                         0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
 705                         0x01, 0x27,    /* movs    r7, #1 */
 706                         0x3e, 0x42,    /* tst     r6, r7 */
 707                         0xfb, 0xd1,    /* bne     busy */
 708
 709                         0x9d, 0x42,    /* cmp     r5, r3 */
 710                         0x01, 0xd3,    /* bcc     no_wrap */
 711                         0x15, 0x46,    /* mov     r5, r2 */
 712                         0x08, 0x35,    /* adds    r5, #8 */
 713
 714                 /* no_wrap: */
 715                         0x55, 0x60,    /* str     r5, [r2, #4] */
 716                         0x01, 0x39,    /* subs    r1, r1, #1 */
 717                         0x00, 0x29,    /* cmp     r1, #0 */
 718                         0x02, 0xd0,    /* beq     exit */
 719                         0xdb, 0xe7,    /* b       wait_fifo */
 720
 721                 /* error: */
 722                         0x00, 0x20,    /* movs    r0, #0 */
 723                         0x50, 0x60,    /* str     r0, [r2, #4] */
 724
 725                 /* exit: */
 726                         0x30, 0x46,    /* mov     r0, r6 */
 727                         0x00, 0xbe,    /* bkpt    #0 */
 728         };
 729
 730
 731         /* flash write code */
 732         if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
 733                         &write_algorithm) != ERROR_OK) {
 734                 LOG_WARNING("no working area available, can't do block memory writes");
 735                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 736         }
 737
 738         ret = target_write_buffer(target, write_algorithm->address,
 739                         sizeof(efm32x_flash_write_code), efm32x_flash_write_code);
 740         if (ret != ERROR_OK)
 741                 return ret;
 742
 743         /* memory buffer */
 744         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 745                 buffer_size /= 2;
 746                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 747                 if (buffer_size <= 256) {
 748                         /* we already allocated the writing code, but failed to get a
 749                          * buffer, free the algorithm */
 750                         target_free_working_area(target, write_algorithm);
 751
 752                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 753                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 754                 }
 755         }
 756
 757         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 758         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (word-32bit) */
 759         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 760         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 761         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 762
 763         buf_set_u32(reg_params[0].value, 0, 32, efm32x_info->reg_base);
 764         buf_set_u32(reg_params[1].value, 0, 32, count);
 765         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 766         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 767         buf_set_u32(reg_params[4].value, 0, 32, address);
 768
 769         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 770         armv7m_info.core_mode = ARM_MODE_THREAD;
 771
 772         ret = target_run_flash_async_algorithm(target, buf, count, 4,
 773                         0, NULL,
 774                         5, reg_params,
 775                         source->address, source->size,
 776                         write_algorithm->address, 0,
 777                         &armv7m_info);
 778
 779         if (ret == ERROR_FLASH_OPERATION_FAILED) {
 780                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 781                                 buf_get_u32(reg_params[4].value, 0, 32));
 782
 783                 if (buf_get_u32(reg_params[0].value, 0, 32) &
 784                                 EFM32_MSC_STATUS_LOCKED_MASK) {
 785                         LOG_ERROR("flash memory write protected");
 786                 }
 787
 788                 if (buf_get_u32(reg_params[0].value, 0, 32) &
 789                                 EFM32_MSC_STATUS_INVADDR_MASK) {
 790                         LOG_ERROR("invalid flash memory write address");
 791                 }
 792         }
 793
 794         target_free_working_area(target, source);
 795         target_free_working_area(target, write_algorithm);
 796
 797         destroy_reg_param(&reg_params[0]);
 798         destroy_reg_param(&reg_params[1]);
 799         destroy_reg_param(&reg_params[2]);
 800         destroy_reg_param(&reg_params[3]);
 801         destroy_reg_param(&reg_params[4]);
 802
 803         return ret;
 804 }
 805
 806 static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
 807         uint32_t val)
 808 {
 809         /* this function DOES NOT set WREN; must be set already */
 810         /* 1. write address to ADDRB
 811            2. write LADDRIM
 812            3. check status (INVADDR, LOCKED)
 813            4. wait for WDATAREADY
 814            5. write data to WDATA
 815            6. write WRITECMD_WRITEONCE to WRITECMD
 816            7. wait until !STATUS_BUSY
 817          */
 818
 819         /* FIXME: EFM32G ref states (7.3.2) that writes should be
 820          * performed twice per dword */
 821
 822         int ret = 0;
 823         uint32_t status = 0;
 824
 825         /* if not called, GDB errors will be reported during large writes */
 826         keep_alive();
 827
 828         ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
 829         if (ERROR_OK != ret)
 830                 return ret;
 831
 832         ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
 833                 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 834         if (ERROR_OK != ret)
 835                 return ret;
 836
 837         ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 838         if (ERROR_OK != ret)
 839                 return ret;
 840
 841         LOG_DEBUG("status 0x%" PRIx32, status);
 842
 843         if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
 844                 LOG_ERROR("Page is locked");
 845                 return ERROR_FAIL;
 846         } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
 847                 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
 848                 return ERROR_FAIL;
 849         }
 850
 851         ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
 852                 EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
 853         if (ERROR_OK != ret) {
 854                 LOG_ERROR("Wait for WDATAREADY failed");
 855                 return ret;
 856         }
 857
 858         ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
 859         if (ERROR_OK != ret) {
 860                 LOG_ERROR("WDATA write failed");
 861                 return ret;
 862         }
 863
 864         ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
 865                 EFM32_MSC_WRITECMD_WRITEONCE_MASK);
 866         if (ERROR_OK != ret) {
 867                 LOG_ERROR("WRITECMD write failed");
 868                 return ret;
 869         }
 870
 871         ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
 872                 EFM32_MSC_STATUS_BUSY_MASK, 0);
 873         if (ERROR_OK != ret) {
 874                 LOG_ERROR("Wait for BUSY failed");
 875                 return ret;
 876         }
 877
 878         return ERROR_OK;
 879 }
 880
 881 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 882                 uint32_t offset, uint32_t count)
 883 {
 884         struct target *target = bank->target;
 885         uint8_t *new_buffer = NULL;
 886
 887         if (target->state != TARGET_HALTED) {
 888                 LOG_ERROR("Target not halted");
 889                 return ERROR_TARGET_NOT_HALTED;
 890         }
 891
 892         if (offset & 0x3) {
 893                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte "
 894                         "alignment", offset);
 895                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 896         }
 897
 898         if (count & 0x3) {
 899                 uint32_t old_count = count;
 900                 count = (old_count | 3) + 1;
 901                 new_buffer = malloc(count);
 902                 if (new_buffer == NULL) {
 903                         LOG_ERROR("odd number of bytes to write and no memory "
 904                                 "for padding buffer");
 905                         return ERROR_FAIL;
 906                 }
 907                 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
 908                         "and padding with 0xff", old_count, count);
 909                 memset(new_buffer, 0xff, count);
 910                 buffer = memcpy(new_buffer, buffer, old_count);
 911         }
 912
 913         uint32_t words_remaining = count / 4;
 914         int retval, retval2;
 915
 916         /* unlock flash registers */
 917         efm32x_msc_lock(bank, 0);
 918         retval = efm32x_set_wren(bank, 1);
 919         if (retval != ERROR_OK)
 920                 goto cleanup;
 921
 922         /* try using a block write */
 923         retval = efm32x_write_block(bank, buffer, offset, words_remaining);
 924
 925         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 926                 /* if block write failed (no sufficient working area),
 927                  * we use normal (slow) single word accesses */
 928                 LOG_WARNING("couldn't use block writes, falling back to single "
 929                         "memory accesses");
 930
 931                 while (words_remaining > 0) {
 932                         uint32_t value;
 933                         memcpy(&value, buffer, sizeof(uint32_t));
 934
 935                         retval = efm32x_write_word(bank, offset, value);
 936                         if (retval != ERROR_OK)
 937                                 goto reset_pg_and_lock;
 938
 939                         words_remaining--;
 940                         buffer += 4;
 941                         offset += 4;
 942                 }
 943         }
 944
 945 reset_pg_and_lock:
 946         retval2 = efm32x_set_wren(bank, 0);
 947         efm32x_msc_lock(bank, 1);
 948         if (retval == ERROR_OK)
 949                 retval = retval2;
 950
 951 cleanup:
 952         if (new_buffer)
 953                 free(new_buffer);
 954
 955         return retval;
 956 }
 957
 958 static int efm32x_probe(struct flash_bank *bank)
 959 {
 960         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
 961         struct efm32_info efm32_mcu_info;
 962         int ret;
 963         int i;
 964         uint32_t base_address = 0x00000000;
 965         char buf[256];
 966
 967         efm32x_info->probed = 0;
 968         memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
 969
 970         ret = efm32x_read_info(bank, &efm32_mcu_info);
 971         if (ERROR_OK != ret)
 972                 return ret;
 973
 974         ret = efm32x_decode_info(&efm32_mcu_info, buf, sizeof(buf));
 975         if (ERROR_OK != ret)
 976                 return ret;
 977
 978         LOG_INFO("detected part: %s", buf);
 979         LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
 980         LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
 981
 982         assert(0 != efm32_mcu_info.page_size);
 983
 984         int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
 985                 efm32_mcu_info.page_size;
 986
 987         assert(num_pages > 0);
 988
 989         if (bank->sectors) {
 990                 free(bank->sectors);
 991                 bank->sectors = NULL;
 992         }
 993
 994         bank->base = base_address;
 995         bank->size = (num_pages * efm32_mcu_info.page_size);
 996         bank->num_sectors = num_pages;
 997
 998         ret = efm32x_read_lock_data(bank);
 999         if (ERROR_OK != ret) {
1000                 LOG_ERROR("Failed to read LB data");
1001                 return ret;
1002         }
1003
1004         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1005
1006         for (i = 0; i < num_pages; i++) {
1007                 bank->sectors[i].offset = i * efm32_mcu_info.page_size;
1008                 bank->sectors[i].size = efm32_mcu_info.page_size;
1009                 bank->sectors[i].is_erased = -1;
1010                 bank->sectors[i].is_protected = 1;
1011         }
1012
1013         efm32x_info->probed = 1;
1014
1015         return ERROR_OK;
1016 }
1017
1018 static int efm32x_auto_probe(struct flash_bank *bank)
1019 {
1020         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
1021         if (efm32x_info->probed)
1022                 return ERROR_OK;
1023         return efm32x_probe(bank);
1024 }
1025
1026 static int efm32x_protect_check(struct flash_bank *bank)
1027 {
1028         struct target *target = bank->target;
1029         int ret = 0;
1030         int i = 0;
1031
1032         if (target->state != TARGET_HALTED) {
1033                 LOG_ERROR("Target not halted");
1034                 return ERROR_TARGET_NOT_HALTED;
1035         }
1036
1037         ret = efm32x_read_lock_data(bank);
1038         if (ERROR_OK != ret) {
1039                 LOG_ERROR("Failed to read LB data");
1040                 return ret;
1041         }
1042
1043         assert(NULL != bank->sectors);
1044
1045         for (i = 0; i < bank->num_sectors; i++)
1046                 bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
1047
1048         return ERROR_OK;
1049 }
1050
1051 static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1052 {
1053         struct efm32_info info;
1054         int ret = 0;
1055
1056         ret = efm32x_read_info(bank, &info);
1057         if (ERROR_OK != ret) {
1058                 LOG_ERROR("Failed to read EFM32 info");
1059                 return ret;
1060         }
1061
1062         return efm32x_decode_info(&info, buf, buf_size);
1063 }
1064
1065 COMMAND_HANDLER(efm32x_handle_debuglock_command)
1066 {
1067         struct target *target = NULL;
1068
1069         if (CMD_ARGC < 1)
1070                 return ERROR_COMMAND_SYNTAX_ERROR;
1071
1072         struct flash_bank *bank;
1073         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1074         if (ERROR_OK != retval)
1075                 return retval;
1076
1077         struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
1078
1079         target = bank->target;
1080
1081         if (target->state != TARGET_HALTED) {
1082                 LOG_ERROR("Target not halted");
1083                 return ERROR_TARGET_NOT_HALTED;
1084         }
1085
1086         uint32_t *ptr;
1087         ptr = efm32x_info->lb_page + 127;
1088         *ptr = 0;
1089
1090         retval = efm32x_write_lock_data(bank);
1091         if (ERROR_OK != retval) {
1092                 LOG_ERROR("Failed to write LB page");
1093                 return retval;
1094         }
1095
1096         command_print(CMD, "efm32x debug interface locked, reset the device to apply");
1097
1098         return ERROR_OK;
1099 }
1100
1101 static const struct command_registration efm32x_exec_command_handlers[] = {
1102         {
1103                 .name = "debuglock",
1104                 .handler = efm32x_handle_debuglock_command,
1105                 .mode = COMMAND_EXEC,
1106                 .usage = "bank_id",
1107                 .help = "Lock the debug interface of the device.",
1108         },
1109         COMMAND_REGISTRATION_DONE
1110 };
1111
1112 static const struct command_registration efm32x_command_handlers[] = {
1113         {
1114                 .name = "efm32",
1115                 .mode = COMMAND_ANY,
1116                 .help = "efm32 flash command group",
1117                 .usage = "",
1118                 .chain = efm32x_exec_command_handlers,
1119         },
1120         COMMAND_REGISTRATION_DONE
1121 };
1122
1123 const struct flash_driver efm32_flash = {
1124         .name = "efm32",
1125         .commands = efm32x_command_handlers,
1126         .flash_bank_command = efm32x_flash_bank_command,
1127         .erase = efm32x_erase,
1128         .protect = efm32x_protect,
1129         .write = efm32x_write,
1130         .read = default_flash_read,
1131         .probe = efm32x_probe,
1132         .auto_probe = efm32x_auto_probe,
1133         .erase_check = default_flash_blank_check,
1134         .protect_check = efm32x_protect_check,
1135         .info = get_efm32x_info,
1136         .free_driver_priv = default_flash_free_driver_priv,
1137 };