]> git.gag.com Git - fw/openocd/blob - src/flash/nor/avrf.c
NOR/CFI: review scope of functions
[fw/openocd] / src / flash / nor / avrf.c
1 /***************************************************************************
2  *   Copyright (C) 2009 by Simon Qian                                      *
3  *   SimonQian@SimonQian.com                                               *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "imp.h"
25 #include "avrf.h"
26 #include <target/avrt.h>
27
28
29 /* AVR_JTAG_Instructions */
30 #define AVR_JTAG_INS_LEN                                                        4
31 // Public Instructions:
32 #define AVR_JTAG_INS_EXTEST                                                     0x00
33 #define AVR_JTAG_INS_IDCODE                                                     0x01
34 #define AVR_JTAG_INS_SAMPLE_PRELOAD                                     0x02
35 #define AVR_JTAG_INS_BYPASS                                                     0x0F
36 // AVR Specified Public Instructions:
37 #define AVR_JTAG_INS_AVR_RESET                                          0x0C
38 #define AVR_JTAG_INS_PROG_ENABLE                                        0x04
39 #define AVR_JTAG_INS_PROG_COMMANDS                                      0x05
40 #define AVR_JTAG_INS_PROG_PAGELOAD                                      0x06
41 #define AVR_JTAG_INS_PROG_PAGEREAD                                      0x07
42
43 // Data Registers:
44 #define AVR_JTAG_REG_Bypass_Len                                         1
45 #define AVR_JTAG_REG_DeviceID_Len                                       32
46
47 #define AVR_JTAG_REG_Reset_Len                                          1
48 #define AVR_JTAG_REG_JTAGID_Len                                         32
49 #define AVR_JTAG_REG_ProgrammingEnable_Len                      16
50 #define AVR_JTAG_REG_ProgrammingCommand_Len                     15
51 #define AVR_JTAG_REG_FlashDataByte_Len                          16
52
53 static struct avrf_type avft_chips_info[] =
54 {
55 /*      name, chip_id,  flash_page_size, flash_page_num,
56  *                      eeprom_page_size, eeprom_page_num
57  */
58         {"atmega128",   0x9702, 256, 512, 8, 512},
59         {"at90can128",  0x9781, 256, 512, 8, 512},
60 };
61
62 int avr_jtag_sendinstr(struct jtag_tap *tap, uint8_t *ir_in, uint8_t ir_out);
63 int avr_jtag_senddat(struct jtag_tap *tap, uint32_t *dr_in, uint32_t dr_out, int len);
64
65 int mcu_write_ir(struct jtag_tap *tap, uint8_t *ir_in, uint8_t *ir_out, int ir_len, int rti);
66 int mcu_write_dr(struct jtag_tap *tap, uint8_t *ir_in, uint8_t *ir_out, int dr_len, int rti);
67 int mcu_write_ir_u8(struct jtag_tap *tap, uint8_t *ir_in, uint8_t ir_out, int ir_len, int rti);
68 int mcu_write_dr_u8(struct jtag_tap *tap, uint8_t *ir_in, uint8_t ir_out, int dr_len, int rti);
69 int mcu_write_ir_u16(struct jtag_tap *tap, uint16_t *ir_in, uint16_t ir_out, int ir_len, int rti);
70 int mcu_write_dr_u16(struct jtag_tap *tap, uint16_t *ir_in, uint16_t ir_out, int dr_len, int rti);
71 int mcu_write_ir_u32(struct jtag_tap *tap, uint32_t *ir_in, uint32_t ir_out, int ir_len, int rti);
72 int mcu_write_dr_u32(struct jtag_tap *tap, uint32_t *ir_in, uint32_t ir_out, int dr_len, int rti);
73 int mcu_execute_queue(void);
74
75 /* avr program functions */
76 static int avr_jtag_reset(struct avr_common *avr, uint32_t reset)
77 {
78         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_AVR_RESET);
79         avr_jtag_senddat(avr->jtag_info.tap, NULL, reset ,AVR_JTAG_REG_Reset_Len);
80
81         return ERROR_OK;
82 }
83
84 static int avr_jtag_read_jtagid(struct avr_common *avr, uint32_t *id)
85 {
86         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_IDCODE);
87         avr_jtag_senddat(avr->jtag_info.tap, id, 0, AVR_JTAG_REG_JTAGID_Len);
88
89         return ERROR_OK;
90 }
91
92 static int avr_jtagprg_enterprogmode(struct avr_common *avr)
93 {
94         avr_jtag_reset(avr, 1);
95
96         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
97         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xA370, AVR_JTAG_REG_ProgrammingEnable_Len);
98
99         return ERROR_OK;
100 }
101
102 static int avr_jtagprg_leaveprogmode(struct avr_common *avr)
103 {
104         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
105         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2300, AVR_JTAG_REG_ProgrammingCommand_Len);
106         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
107
108         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
109         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0, AVR_JTAG_REG_ProgrammingEnable_Len);
110
111         avr_jtag_reset(avr, 0);
112
113         return ERROR_OK;
114 }
115
116 static int avr_jtagprg_chiperase(struct avr_common *avr)
117 {
118         uint32_t poll_value;
119
120         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
121         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2380, AVR_JTAG_REG_ProgrammingCommand_Len);
122         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3180, AVR_JTAG_REG_ProgrammingCommand_Len);
123         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
124         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
125
126         do {
127                 poll_value = 0;
128                 avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
129                 if (ERROR_OK != mcu_execute_queue())
130                 {
131                         return ERROR_FAIL;
132                 }
133                 LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
134         } while (!(poll_value & 0x0200));
135
136         return ERROR_OK;
137 }
138
139 static int avr_jtagprg_writeflashpage(struct avr_common *avr, uint8_t *page_buf, uint32_t buf_size, uint32_t addr, uint32_t page_size)
140 {
141         uint32_t i, poll_value;
142
143         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
144         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2310, AVR_JTAG_REG_ProgrammingCommand_Len);
145
146         // load addr high byte
147         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0700 | ((addr >> 9) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
148
149         // load addr low byte
150         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0300 | ((addr >> 1) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
151
152         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_PAGELOAD);
153
154         for (i = 0; i < page_size; i++)
155         {
156                 if (i < buf_size)
157                 {
158                         avr_jtag_senddat(avr->jtag_info.tap, NULL, page_buf[i], 8);
159                 }
160                 else
161                 {
162                         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xFF, 8);
163                 }
164         }
165
166         avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
167
168         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
169         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3500, AVR_JTAG_REG_ProgrammingCommand_Len);
170         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
171         avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
172
173         do {
174                 poll_value = 0;
175                 avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
176                 if (ERROR_OK != mcu_execute_queue())
177                 {
178                         return ERROR_FAIL;
179                 }
180                 LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
181         } while (!(poll_value & 0x0200));
182
183         return ERROR_OK;
184 }
185
186 FLASH_BANK_COMMAND_HANDLER(avrf_flash_bank_command)
187 {
188         struct avrf_flash_bank *avrf_info;
189
190         if (CMD_ARGC < 6)
191         {
192                 LOG_WARNING("incomplete flash_bank avr configuration");
193                 return ERROR_FLASH_BANK_INVALID;
194         }
195
196         avrf_info = malloc(sizeof(struct avrf_flash_bank));
197         bank->driver_priv = avrf_info;
198
199         avrf_info->probed = 0;
200
201         return ERROR_OK;
202 }
203
204 static int avrf_erase(struct flash_bank *bank, int first, int last)
205 {
206         struct target *target = bank->target;
207         struct avr_common *avr = target->arch_info;
208         int status;
209
210         LOG_DEBUG("%s", __FUNCTION__);
211
212         if (target->state != TARGET_HALTED)
213         {
214                 LOG_ERROR("Target not halted");
215                 return ERROR_TARGET_NOT_HALTED;
216         }
217
218         status = avr_jtagprg_enterprogmode(avr);
219         if (status != ERROR_OK)
220                 return status;
221
222         status = avr_jtagprg_chiperase(avr);
223         if (status != ERROR_OK)
224                 return status;
225
226         return avr_jtagprg_leaveprogmode(avr);
227 }
228
229 static int avrf_protect(struct flash_bank *bank, int set, int first, int last)
230 {
231         LOG_INFO("%s", __FUNCTION__);
232         return ERROR_OK;
233 }
234
235 static int avrf_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
236 {
237         struct target *target = bank->target;
238         struct avr_common *avr = target->arch_info;
239         uint32_t cur_size, cur_buffer_size, page_size;
240
241         if (bank->target->state != TARGET_HALTED)
242         {
243                 LOG_ERROR("Target not halted");
244                 return ERROR_TARGET_NOT_HALTED;
245         }
246
247         page_size = bank->sectors[0].size;
248         if ((offset % page_size) != 0)
249         {
250                 LOG_WARNING("offset 0x%" PRIx32 " breaks required %" PRIu32 "-byte alignment", offset, page_size);
251                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
252         }
253
254         LOG_DEBUG("offset is 0x%08" PRIx32 "", offset);
255         LOG_DEBUG("count is %" PRId32 "", count);
256
257         if (ERROR_OK != avr_jtagprg_enterprogmode(avr))
258         {
259                 return ERROR_FAIL;
260         }
261
262         cur_size = 0;
263         while (count > 0)
264         {
265                 if (count > page_size)
266                 {
267                         cur_buffer_size = page_size;
268                 }
269                 else
270                 {
271                         cur_buffer_size = count;
272                 }
273                 avr_jtagprg_writeflashpage(avr, buffer + cur_size, cur_buffer_size, offset + cur_size, page_size);
274                 count -= cur_buffer_size;
275                 cur_size += cur_buffer_size;
276
277                 keep_alive();
278         }
279
280         return avr_jtagprg_leaveprogmode(avr);
281 }
282
283 #define EXTRACT_MFG(X)  (((X) & 0xffe) >> 1)
284 #define EXTRACT_PART(X) (((X) & 0xffff000) >> 12)
285 #define EXTRACT_VER(X)  (((X) & 0xf0000000) >> 28)
286 static int avrf_probe(struct flash_bank *bank)
287 {
288         struct target *target = bank->target;
289         struct avrf_flash_bank *avrf_info = bank->driver_priv;
290         struct avr_common *avr = target->arch_info;
291         struct avrf_type *avr_info = NULL;
292         int i;
293         uint32_t device_id;
294
295         if (bank->target->state != TARGET_HALTED)
296         {
297                 LOG_ERROR("Target not halted");
298                 return ERROR_TARGET_NOT_HALTED;
299         }
300
301         avrf_info->probed = 0;
302
303         avr_jtag_read_jtagid(avr, &device_id);
304         if (ERROR_OK != mcu_execute_queue())
305         {
306                 return ERROR_FAIL;
307         }
308
309         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
310         if (EXTRACT_MFG(device_id) != 0x1F)
311         {
312                 LOG_ERROR("0x%" PRIx32 " is invalid Manufacturer for avr, 0x%X is expected", EXTRACT_MFG(device_id), 0x1F);
313         }
314
315         for (i = 0; i < (int)ARRAY_SIZE(avft_chips_info); i++)
316         {
317                 if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id))
318                 {
319                         avr_info = &avft_chips_info[i];
320                         LOG_INFO("target device is %s", avr_info->name);
321                         break;
322                 }
323         }
324
325         if (avr_info != NULL)
326         {
327                 // chip found
328                 bank->base = 0x00000000;
329                 bank->size = (avr_info->flash_page_size * avr_info->flash_page_num);
330                 bank->num_sectors = avr_info->flash_page_num;
331                 bank->sectors = malloc(sizeof(struct flash_sector) * avr_info->flash_page_num);
332
333                 for (i = 0; i < avr_info->flash_page_num; i++)
334                 {
335                         bank->sectors[i].offset = i * avr_info->flash_page_size;
336                         bank->sectors[i].size = avr_info->flash_page_size;
337                         bank->sectors[i].is_erased = -1;
338                         bank->sectors[i].is_protected = 1;
339                 }
340
341                 avrf_info->probed = 1;
342                 return ERROR_OK;
343         }
344         else
345         {
346                 // chip not supported
347                 LOG_ERROR("0x%" PRIx32 " is not support for avr", EXTRACT_PART(device_id));
348
349                 avrf_info->probed = 1;
350                 return ERROR_FAIL;
351         }
352 }
353
354 static int avrf_auto_probe(struct flash_bank *bank)
355 {
356         struct avrf_flash_bank *avrf_info = bank->driver_priv;
357         if (avrf_info->probed)
358                 return ERROR_OK;
359         return avrf_probe(bank);
360 }
361
362 static int avrf_protect_check(struct flash_bank *bank)
363 {
364         LOG_INFO("%s", __FUNCTION__);
365         return ERROR_OK;
366 }
367
368 static int avrf_info(struct flash_bank *bank, char *buf, int buf_size)
369 {
370         struct target *target = bank->target;
371         struct avr_common *avr = target->arch_info;
372         struct avrf_type *avr_info = NULL;
373         int i;
374         uint32_t device_id;
375
376         if (bank->target->state != TARGET_HALTED)
377         {
378                 LOG_ERROR("Target not halted");
379                 return ERROR_TARGET_NOT_HALTED;
380         }
381
382         avr_jtag_read_jtagid(avr, &device_id);
383         if (ERROR_OK != mcu_execute_queue())
384         {
385                 return ERROR_FAIL;
386         }
387
388         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
389         if (EXTRACT_MFG(device_id) != 0x1F)
390         {
391                 LOG_ERROR("0x%" PRIx32 " is invalid Manufacturer for avr, 0x%X is expected", EXTRACT_MFG(device_id), 0x1F);
392         }
393
394         for (i = 0; i < (int)ARRAY_SIZE(avft_chips_info); i++)
395         {
396                 if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id))
397                 {
398                         avr_info = &avft_chips_info[i];
399                         LOG_INFO("target device is %s", avr_info->name);
400
401                         break;
402                 }
403         }
404
405         if (avr_info != NULL)
406         {
407                 // chip found
408                 snprintf(buf, buf_size, "%s - Rev: 0x%" PRIx32 "", avr_info->name, EXTRACT_VER(device_id));
409                 return ERROR_OK;
410         }
411         else
412         {
413                 // chip not supported
414                 snprintf(buf, buf_size, "Cannot identify target as a avr\n");
415                 return ERROR_FLASH_OPERATION_FAILED;
416         }
417 }
418
419 static int avrf_mass_erase(struct flash_bank *bank)
420 {
421         struct target *target = bank->target;
422         struct avr_common *avr = target->arch_info;
423
424         if (target->state != TARGET_HALTED)
425         {
426                 LOG_ERROR("Target not halted");
427                 return ERROR_TARGET_NOT_HALTED;
428         }
429
430         if ((ERROR_OK != avr_jtagprg_enterprogmode(avr))
431                 || (ERROR_OK != avr_jtagprg_chiperase(avr))
432                 || (ERROR_OK != avr_jtagprg_leaveprogmode(avr)))
433         {
434                 return ERROR_FAIL;
435         }
436
437         return ERROR_OK;
438 }
439
440 COMMAND_HANDLER(avrf_handle_mass_erase_command)
441 {
442         int i;
443
444         if (CMD_ARGC < 1)
445         {
446                 command_print(CMD_CTX, "avr mass_erase <bank>");
447                 return ERROR_OK;
448         }
449
450         struct flash_bank *bank;
451         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
452         if (ERROR_OK != retval)
453                 return retval;
454
455         if (avrf_mass_erase(bank) == ERROR_OK)
456         {
457                 /* set all sectors as erased */
458                 for (i = 0; i < bank->num_sectors; i++)
459                 {
460                         bank->sectors[i].is_erased = 1;
461                 }
462
463                 command_print(CMD_CTX, "avr mass erase complete");
464         }
465         else
466         {
467                 command_print(CMD_CTX, "avr mass erase failed");
468         }
469
470         LOG_DEBUG("%s", __FUNCTION__);
471         return ERROR_OK;
472 }
473
474 static const struct command_registration avrf_exec_command_handlers[] = {
475         {
476                 .name = "mass_erase",
477                 .handler = avrf_handle_mass_erase_command,
478                 .mode = COMMAND_EXEC,
479                 .help = "erase entire device",
480         },
481         COMMAND_REGISTRATION_DONE
482 };
483 static const struct command_registration avrf_command_handlers[] = {
484         {
485                 .name = "avrf",
486                 .mode = COMMAND_ANY,
487                 .help = "AVR flash command group",
488                 .chain = avrf_exec_command_handlers,
489         },
490         COMMAND_REGISTRATION_DONE
491 };
492
493 struct flash_driver avr_flash = {
494         .name = "avr",
495         .commands = avrf_command_handlers,
496         .flash_bank_command = avrf_flash_bank_command,
497         .erase = avrf_erase,
498         .protect = avrf_protect,
499         .write = avrf_write,
500         .probe = avrf_probe,
501         .auto_probe = avrf_auto_probe,
502         .erase_check = default_flash_mem_blank_check,
503         .protect_check = avrf_protect_check,
504         .info = avrf_info,
505 };