1 /***************************************************************************
2 * Copyright (C) 2017 by Tomas Vanek *
5 * Based on at91samd.c *
6 * Copyright (C) 2013 by Andrey Yurovsky *
7 * Andrey Yurovsky <yurovsky@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
21 ***************************************************************************/
28 #include "helper/binarybuffer.h"
30 #include <helper/time_support.h>
31 #include <jtag/jtag.h>
32 #include <target/cortex_m.h>
34 /* A note to prefixing.
35 * Definitions and functions inherited from at91samd.c without
36 * any change retained the original prefix samd_ so they eventually
37 * may go to samd_common.h and .c
38 * As currently there are only 3 short functions identical with
39 * the original source, no common file was created. */
41 #define SAME5_PAGES_PER_BLOCK 16
42 #define SAME5_NUM_PROT_BLOCKS 32
43 #define SAMD_PAGE_SIZE_MAX 1024
45 #define SAMD_FLASH 0x00000000 /* physical Flash memory */
46 #define SAMD_USER_ROW 0x00804000 /* User Row of Flash */
48 #define SAME5_PAC 0x40000000 /* Peripheral Access Control */
50 #define SAMD_DSU 0x41002000 /* Device Service Unit */
51 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
53 #define SAMD_DSU_STATUSA 1 /* DSU status register */
54 #define SAMD_DSU_DID 0x18 /* Device ID register */
55 #define SAMD_DSU_CTRL_EXT 0x100 /* CTRL register, external access */
57 #define SAME5_NVMCTRL_CTRLA 0x00 /* NVM control A register */
58 #define SAME5_NVMCTRL_CTRLB 0x04 /* NVM control B register */
59 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
60 #define SAME5_NVMCTRL_INTFLAG 0x10 /* NVM interrupt flag register */
61 #define SAME5_NVMCTRL_STATUS 0x12 /* NVM status register */
62 #define SAME5_NVMCTRL_ADDR 0x14 /* NVM address register */
63 #define SAME5_NVMCTRL_LOCK 0x18 /* NVM Lock section register */
65 #define SAMD_CMDEX_KEY 0xA5UL
66 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
68 /* NVMCTRL commands. */
69 #define SAME5_NVM_CMD_EP 0x00 /* Erase Page (User Page only) */
70 #define SAME5_NVM_CMD_EB 0x01 /* Erase Block */
71 #define SAME5_NVM_CMD_WP 0x03 /* Write Page */
72 #define SAME5_NVM_CMD_WQW 0x04 /* Write Quad Word */
73 #define SAME5_NVM_CMD_LR 0x11 /* Lock Region */
74 #define SAME5_NVM_CMD_UR 0x12 /* Unlock Region */
75 #define SAME5_NVM_CMD_PBC 0x15 /* Page Buffer Clear */
76 #define SAME5_NVM_CMD_SSB 0x16 /* Set Security Bit */
79 #define SAME5_NVMCTRL_CTRLA_WMODE_MASK 0x30
81 #define SAME5_NVMCTRL_INTFLAG_DONE (1 << 0)
82 #define SAME5_NVMCTRL_INTFLAG_ADDRE (1 << 1)
83 #define SAME5_NVMCTRL_INTFLAG_PROGE (1 << 2)
84 #define SAME5_NVMCTRL_INTFLAG_LOCKE (1 << 3)
85 #define SAME5_NVMCTRL_INTFLAG_ECCSE (1 << 4)
86 #define SAME5_NVMCTRL_INTFLAG_ECCDE (1 << 5)
87 #define SAME5_NVMCTRL_INTFLAG_NVME (1 << 6)
90 /* Known identifiers */
91 #define SAMD_PROCESSOR_M0 0x01
92 #define SAMD_PROCESSOR_M4 0x06
93 #define SAMD_FAMILY_D 0x00
94 #define SAMD_FAMILY_E 0x03
95 #define SAMD_SERIES_51 0x06
96 #define SAME_SERIES_51 0x01
97 #define SAME_SERIES_53 0x03
98 #define SAME_SERIES_54 0x04
100 /* Device ID macros */
101 #define SAMD_GET_PROCESSOR(id) (id >> 28)
102 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
103 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
104 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
106 /* Bits to mask user row */
107 #define NVMUSERROW_SAM_E5_D5_MASK ((uint64_t)0x7FFF00FF3C007FFF)
116 /* See SAM D5x/E5x Family Silicon Errata and Data Sheet Clarification
118 /* Known SAMD51 parts. */
119 static const struct samd_part samd51_parts[] = {
120 { 0x00, "SAMD51P20A", 1024, 256 },
121 { 0x01, "SAMD51P19A", 512, 192 },
122 { 0x02, "SAMD51N20A", 1024, 256 },
123 { 0x03, "SAMD51N19A", 512, 192 },
124 { 0x04, "SAMD51J20A", 1024, 256 },
125 { 0x05, "SAMD51J19A", 512, 192 },
126 { 0x06, "SAMD51J18A", 256, 128 },
127 { 0x07, "SAMD51G19A", 512, 192 },
128 { 0x08, "SAMD51G18A", 256, 128 },
131 /* Known SAME51 parts. */
132 static const struct samd_part same51_parts[] = {
133 { 0x00, "SAME51N20A", 1024, 256 },
134 { 0x01, "SAME51N19A", 512, 192 },
135 { 0x02, "SAME51J19A", 512, 192 },
136 { 0x03, "SAME51J18A", 256, 128 },
137 { 0x04, "SAME51J20A", 1024, 256 },
138 { 0x05, "SAME51G19A", 512, 192 }, /* New in rev D */
139 { 0x06, "SAME51G18A", 256, 128 }, /* New in rev D */
142 /* Known SAME53 parts. */
143 static const struct samd_part same53_parts[] = {
144 { 0x02, "SAME53N20A", 1024, 256 },
145 { 0x03, "SAME53N19A", 512, 192 },
146 { 0x04, "SAME53J20A", 1024, 256 },
147 { 0x05, "SAME53J19A", 512, 192 },
148 { 0x06, "SAME53J18A", 256, 128 },
151 /* Known SAME54 parts. */
152 static const struct samd_part same54_parts[] = {
153 { 0x00, "SAME54P20A", 1024, 256 },
154 { 0x01, "SAME54P19A", 512, 192 },
155 { 0x02, "SAME54N20A", 1024, 256 },
156 { 0x03, "SAME54N19A", 512, 192 },
159 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
160 * processor ID, family ID, and series ID are used to determine which exact
161 * family this is and then we can use the corresponding table. */
166 const struct samd_part *parts;
170 /* Known SAMD families */
171 static const struct samd_family samd_families[] = {
172 { SAMD_PROCESSOR_M4, SAMD_FAMILY_D, SAMD_SERIES_51,
173 samd51_parts, ARRAY_SIZE(samd51_parts) },
174 { SAMD_PROCESSOR_M4, SAMD_FAMILY_E, SAME_SERIES_51,
175 same51_parts, ARRAY_SIZE(same51_parts) },
176 { SAMD_PROCESSOR_M4, SAMD_FAMILY_E, SAME_SERIES_53,
177 same53_parts, ARRAY_SIZE(same53_parts) },
178 { SAMD_PROCESSOR_M4, SAMD_FAMILY_E, SAME_SERIES_54,
179 same54_parts, ARRAY_SIZE(same54_parts) },
183 const struct samd_params *par;
190 struct target *target;
195 * Gives the family structure to specific device id.
196 * @param id The id of the device.
197 * @return On failure NULL, otherwise a pointer to the structure.
199 static const struct samd_family *samd_find_family(uint32_t id)
201 uint8_t processor = SAMD_GET_PROCESSOR(id);
202 uint8_t family = SAMD_GET_FAMILY(id);
203 uint8_t series = SAMD_GET_SERIES(id);
205 for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
206 if (samd_families[i].processor == processor &&
207 samd_families[i].series == series &&
208 samd_families[i].family == family)
209 return &samd_families[i];
216 * Gives the part structure to specific device id.
217 * @param id The id of the device.
218 * @return On failure NULL, otherwise a pointer to the structure.
220 static const struct samd_part *samd_find_part(uint32_t id)
222 uint8_t devsel = SAMD_GET_DEVSEL(id);
223 const struct samd_family *family = samd_find_family(id);
227 for (unsigned i = 0; i < family->num_parts; i++) {
228 if (family->parts[i].id == devsel)
229 return &family->parts[i];
235 static int same5_protect_check(struct flash_bank *bank)
240 res = target_read_u32(bank->target,
241 SAMD_NVMCTRL + SAME5_NVMCTRL_LOCK, &lock);
245 /* Lock bits are active-low */
246 for (unsigned int prot_block = 0; prot_block < bank->num_prot_blocks; prot_block++)
247 bank->prot_blocks[prot_block].is_protected = !(lock & (1u<<prot_block));
252 static int samd_get_flash_page_info(struct target *target,
253 uint32_t *sizep, int *nump)
258 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, ¶m);
259 if (res == ERROR_OK) {
260 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
261 * so 0 is 8KB and 7 is 1024KB. */
263 *sizep = (8 << ((param >> 16) & 0x7));
264 /* The NVMP field (bits 15:0) indicates the total number of pages */
266 *nump = param & 0xFFFF;
268 LOG_ERROR("Couldn't read NVM Parameters register");
274 static int same5_probe(struct flash_bank *bank)
278 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
279 const struct samd_part *part;
284 res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
285 if (res != ERROR_OK) {
286 LOG_ERROR("Couldn't read Device ID register");
290 part = samd_find_part(id);
292 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32, id);
296 bank->size = part->flash_kb * 1024;
298 res = samd_get_flash_page_info(bank->target, &chip->page_size,
300 if (res != ERROR_OK) {
301 LOG_ERROR("Couldn't determine Flash page size");
305 /* Sanity check: the total flash size in the DSU should match the page size
306 * multiplied by the number of pages. */
307 if (bank->size != chip->num_pages * chip->page_size) {
308 LOG_WARNING("SAM: bank size doesn't match NVM parameters. "
309 "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
310 part->flash_kb, chip->num_pages, chip->page_size);
313 /* Erase granularity = 1 block = 16 pages */
314 chip->sector_size = chip->page_size * SAME5_PAGES_PER_BLOCK;
316 /* Allocate the sector table */
317 bank->num_sectors = chip->num_pages / SAME5_PAGES_PER_BLOCK;
318 bank->sectors = alloc_block_array(0, chip->sector_size, bank->num_sectors);
322 /* 16 protection blocks per device */
323 chip->prot_block_size = bank->size / SAME5_NUM_PROT_BLOCKS;
325 /* Allocate the table of protection blocks */
326 bank->num_prot_blocks = SAME5_NUM_PROT_BLOCKS;
327 bank->prot_blocks = alloc_block_array(0, chip->prot_block_size, bank->num_prot_blocks);
328 if (!bank->prot_blocks)
331 same5_protect_check(bank);
336 LOG_INFO("SAM MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
337 part->flash_kb, part->ram_kb);
342 static int same5_wait_and_check_error(struct target *target)
345 /* Table 54-40 lists the maximum erase block time as 200 ms.
346 * Include some margin.
348 int timeout_ms = 200 * 5;
349 int64_t ts_start = timeval_ms();
353 ret = target_read_u16(target,
354 SAMD_NVMCTRL + SAME5_NVMCTRL_INTFLAG, &intflag);
355 if (ret != ERROR_OK) {
356 LOG_ERROR("SAM: error reading the NVMCTRL_INTFLAG register");
359 if (intflag & SAME5_NVMCTRL_INTFLAG_DONE)
362 } while (timeval_ms() - ts_start < timeout_ms);
364 if (!(intflag & SAME5_NVMCTRL_INTFLAG_DONE)) {
365 LOG_ERROR("SAM: NVM programming timed out");
366 ret = ERROR_FLASH_OPERATION_FAILED;
369 if (intflag & SAME5_NVMCTRL_INTFLAG_ECCSE)
370 LOG_ERROR("SAM: ECC Single Error");
372 if (intflag & SAME5_NVMCTRL_INTFLAG_ECCDE) {
373 LOG_ERROR("SAM: ECC Double Error");
374 ret = ERROR_FLASH_OPERATION_FAILED;
377 if (intflag & SAME5_NVMCTRL_INTFLAG_ADDRE) {
378 LOG_ERROR("SAM: Addr Error");
379 ret = ERROR_FLASH_OPERATION_FAILED;
382 if (intflag & SAME5_NVMCTRL_INTFLAG_NVME) {
383 LOG_ERROR("SAM: NVM Error");
384 ret = ERROR_FLASH_OPERATION_FAILED;
387 if (intflag & SAME5_NVMCTRL_INTFLAG_LOCKE) {
388 LOG_ERROR("SAM: NVM lock error");
389 ret = ERROR_FLASH_PROTECTED;
392 if (intflag & SAME5_NVMCTRL_INTFLAG_PROGE) {
393 LOG_ERROR("SAM: NVM programming error");
394 ret = ERROR_FLASH_OPER_UNSUPPORTED;
397 /* Clear the error conditions by writing a one to them */
398 ret2 = target_write_u16(target,
399 SAMD_NVMCTRL + SAME5_NVMCTRL_INTFLAG, intflag);
400 if (ret2 != ERROR_OK)
401 LOG_ERROR("Can't clear NVM error conditions");
406 static int same5_issue_nvmctrl_command(struct target *target, uint16_t cmd)
410 if (target->state != TARGET_HALTED) {
411 LOG_ERROR("Target not halted");
412 return ERROR_TARGET_NOT_HALTED;
415 /* Issue the NVM command */
416 /* 32-bit write is used to ensure atomic operation on ST-Link */
417 res = target_write_u32(target,
418 SAMD_NVMCTRL + SAME5_NVMCTRL_CTRLB, SAMD_NVM_CMD(cmd));
422 /* Check to see if the NVM command resulted in an error condition. */
423 return same5_wait_and_check_error(target);
427 * Erases a flash block or page at the given address.
428 * @param target Pointer to the target structure.
429 * @param address The address of the row.
430 * @return On success ERROR_OK, on failure an errorcode.
432 static int same5_erase_block(struct target *target, uint32_t address)
436 /* Set an address contained in the block to be erased */
437 res = target_write_u32(target,
438 SAMD_NVMCTRL + SAME5_NVMCTRL_ADDR, address);
440 /* Issue the Erase Block command. */
442 res = same5_issue_nvmctrl_command(target,
443 address == SAMD_USER_ROW ? SAME5_NVM_CMD_EP : SAME5_NVM_CMD_EB);
445 if (res != ERROR_OK) {
446 LOG_ERROR("Failed to erase block containing %08" PRIx32, address);
454 static int same5_pre_write_check(struct target *target)
459 if (target->state != TARGET_HALTED) {
460 LOG_ERROR("Target not halted");
461 return ERROR_TARGET_NOT_HALTED;
464 /* Check if manual write mode is set */
465 res = target_read_u32(target, SAMD_NVMCTRL + SAME5_NVMCTRL_CTRLA, &nvm_ctrla);
469 if (nvm_ctrla & SAME5_NVMCTRL_CTRLA_WMODE_MASK) {
470 LOG_ERROR("The flash controller must be in manual write mode. Issue 'reset init' and retry.");
479 * Modify the contents of the User Row in Flash. The User Row itself
480 * has a size of one page and contains a combination of "fuses" and
481 * calibration data. Bits which have a value of zero in the mask will
483 * @param target Pointer to the target structure.
484 * @param data Pointer to the value to write.
485 * @param mask Pointer to bitmask, 0 -> value stays untouched.
486 * @param offset Offset in user row where new data will be applied.
487 * @param count Size of buffer and mask in bytes.
488 * @return On success ERROR_OK, on failure an errorcode.
490 static int same5_modify_user_row_masked(struct target *target,
491 const uint8_t *data, const uint8_t *mask,
492 uint32_t offset, uint32_t count)
496 /* Retrieve the MCU's flash page size, in bytes. */
498 res = samd_get_flash_page_info(target, &page_size, NULL);
499 if (res != ERROR_OK) {
500 LOG_ERROR("Couldn't determine Flash page size");
504 /* Make sure the size is sane. */
505 assert(page_size <= SAMD_PAGE_SIZE_MAX &&
506 page_size >= offset + count);
508 uint8_t buf[SAMD_PAGE_SIZE_MAX];
509 /* Read the user row (comprising one page) by words. */
510 res = target_read_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
514 /* Modify buffer and check if really changed */
515 bool changed = false;
517 for (i = 0; i < count; i++) {
518 uint8_t old_b = buf[offset+i];
519 uint8_t new_b = (old_b & ~mask[i]) | (data[i] & mask[i]);
520 buf[offset+i] = new_b;
528 res = same5_pre_write_check(target);
532 res = same5_erase_block(target, SAMD_USER_ROW);
533 if (res != ERROR_OK) {
534 LOG_ERROR("Couldn't erase user row");
538 /* Write the page buffer back out to the target using Write Quad Word */
539 for (i = 0; i < page_size; i += 4 * 4) {
540 res = target_write_memory(target, SAMD_USER_ROW + i, 4, 4, buf + i);
544 /* Trigger flash write */
545 res = same5_issue_nvmctrl_command(target, SAME5_NVM_CMD_WQW);
554 * Modifies the user row register to the given value.
555 * @param target Pointer to the target structure.
556 * @param value The value to write.
557 * @param startb The bit-offset by which the given value is shifted.
558 * @param endb The bit-offset of the last bit in value to write.
559 * @return On success ERROR_OK, on failure an errorcode.
561 static int same5_modify_user_row(struct target *target, uint32_t value,
562 uint8_t startb, uint8_t endb)
564 uint8_t buf_val[8] = { 0 };
565 uint8_t buf_mask[8] = { 0 };
567 assert(startb <= endb && endb < 64);
568 buf_set_u32(buf_val, startb, endb + 1 - startb, value);
569 buf_set_u32(buf_mask, startb, endb + 1 - startb, 0xffffffff);
571 return same5_modify_user_row_masked(target,
572 buf_val, buf_mask, 0, 8);
575 static int same5_protect(struct flash_bank *bank, int set, unsigned int first,
580 /* We can issue lock/unlock region commands with the target running but
581 * the settings won't persist unless we're able to modify the LOCK regions
582 * and that requires the target to be halted. */
583 if (bank->target->state != TARGET_HALTED) {
584 LOG_ERROR("Target not halted");
585 return ERROR_TARGET_NOT_HALTED;
588 for (unsigned int prot_block = first; prot_block <= last; prot_block++) {
589 if (set != bank->prot_blocks[prot_block].is_protected) {
590 /* Load an address that is within this protection block (we use offset 0) */
591 res = target_write_u32(bank->target,
592 SAMD_NVMCTRL + SAME5_NVMCTRL_ADDR,
593 bank->prot_blocks[prot_block].offset);
597 /* Tell the controller to lock that block */
598 res = same5_issue_nvmctrl_command(bank->target,
599 set ? SAME5_NVM_CMD_LR : SAME5_NVM_CMD_UR);
605 /* We've now applied our changes, however they will be undone by the next
606 * reset unless we also apply them to the LOCK bits in the User Page.
607 * A '1' means unlocked and a '0' means locked. */
608 const uint8_t lock[4] = { 0, 0, 0, 0 };
609 const uint8_t unlock[4] = { 0xff, 0xff, 0xff, 0xff };
610 uint8_t mask[4] = { 0, 0, 0, 0 };
612 buf_set_u32(mask, first, last + 1 - first, 0xffffffff);
614 res = same5_modify_user_row_masked(bank->target,
615 set ? lock : unlock, mask, 8, 4);
617 LOG_WARNING("SAM: protect settings were not made persistent!");
622 same5_protect_check(bank);
627 static int same5_erase(struct flash_bank *bank, unsigned int first,
631 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
633 if (bank->target->state != TARGET_HALTED) {
634 LOG_ERROR("Target not halted");
636 return ERROR_TARGET_NOT_HALTED;
640 return ERROR_FLASH_BANK_NOT_PROBED;
642 /* For each sector to be erased */
643 for (unsigned int s = first; s <= last; s++) {
644 res = same5_erase_block(bank->target, bank->sectors[s].offset);
645 if (res != ERROR_OK) {
646 LOG_ERROR("SAM: failed to erase sector %d at 0x%08" PRIx32, s, bank->sectors[s].offset);
655 static int same5_write(struct flash_bank *bank, const uint8_t *buffer,
656 uint32_t offset, uint32_t count)
663 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
666 res = same5_pre_write_check(bank->target);
671 return ERROR_FLASH_BANK_NOT_PROBED;
673 res = same5_issue_nvmctrl_command(bank->target, SAME5_NVM_CMD_PBC);
674 if (res != ERROR_OK) {
675 LOG_ERROR("%s: %d", __func__, __LINE__);
680 nb = chip->page_size - offset % chip->page_size;
684 address = bank->base + offset;
685 pg_offset = offset % chip->page_size;
687 if (offset % 4 || (offset + nb) % 4) {
688 /* Either start or end of write is not word aligned */
690 pb = malloc(chip->page_size);
695 /* Set temporary page buffer to 0xff and overwrite the relevant part */
696 memset(pb, 0xff, chip->page_size);
697 memcpy(pb + pg_offset, buffer, nb);
699 /* Align start address to a word boundary */
700 address -= offset % 4;
701 pg_offset -= offset % 4;
702 assert(pg_offset % 4 == 0);
704 /* Extend length to whole words */
705 nw = (nb + offset % 4 + 3) / 4;
706 assert(pg_offset + 4 * nw <= chip->page_size);
708 /* Now we have original data extended by 0xff bytes
709 * to the nearest word boundary on both start and end */
710 res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
714 assert(pg_offset + 4 * nw <= chip->page_size);
716 /* Word aligned data, use direct write from buffer */
717 res = target_write_memory(bank->target, address, 4, nw, buffer);
719 if (res != ERROR_OK) {
720 LOG_ERROR("%s: %d", __func__, __LINE__);
724 res = same5_issue_nvmctrl_command(bank->target, SAME5_NVM_CMD_WP);
725 if (res != ERROR_OK) {
726 LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
730 /* We're done with the page contents */
742 FLASH_BANK_COMMAND_HANDLER(same5_flash_bank_command)
744 if (bank->base != SAMD_FLASH) {
745 LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try "
746 "0x%08x[same5] )", bank->base, SAMD_FLASH);
750 struct samd_info *chip;
751 chip = calloc(1, sizeof(*chip));
753 LOG_ERROR("No memory for flash bank chip info");
757 chip->target = bank->target;
758 chip->probed = false;
760 bank->driver_priv = chip;
766 COMMAND_HANDLER(same5_handle_chip_erase_command)
768 struct target *target = get_current_target(CMD_CTX);
772 /* Enable access to the DSU by disabling the write protect bit */
773 target_write_u32(target, SAME5_PAC, (1<<16) | (1<<5) | (1<<1));
774 /* intentionally without error checking - not accessible on secured chip */
776 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
777 * perform the erase. */
778 int res = target_write_u8(target, SAMD_DSU + SAMD_DSU_CTRL_EXT, (1<<4));
780 command_print(CMD, "chip erase started");
782 command_print(CMD, "write to DSU CTRL failed");
788 COMMAND_HANDLER(same5_handle_userpage_command)
791 struct target *target = get_current_target(CMD_CTX);
796 command_print(CMD, "Too much Arguments given.");
797 return ERROR_COMMAND_SYNTAX_ERROR;
801 uint64_t value, mask = NVMUSERROW_SAM_E5_D5_MASK;
802 COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], value);
806 COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], mask_temp);
810 uint8_t val_buf[8], mask_buf[8];
811 target_buffer_set_u64(target, val_buf, value);
812 target_buffer_set_u64(target, mask_buf, mask);
814 res = same5_modify_user_row_masked(target,
815 val_buf, mask_buf, 0, sizeof(val_buf));
819 int res2 = target_read_memory(target, SAMD_USER_ROW, 4, 2, buffer);
820 if (res2 == ERROR_OK) {
821 uint64_t value = target_buffer_get_u64(target, buffer);
822 command_print(CMD, "USER PAGE: 0x%016"PRIX64, value);
824 LOG_ERROR("USER PAGE could not be read.");
834 COMMAND_HANDLER(same5_handle_bootloader_command)
837 struct target *target = get_current_target(CMD_CTX);
844 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[0], size);
845 uint32_t code = (size + 8191) / 8192;
847 command_print(CMD, "Invalid bootloader size. Please "
848 "see datasheet for a list valid sizes.");
849 return ERROR_COMMAND_SYNTAX_ERROR;
852 res = same5_modify_user_row(target, 15 - code, 26, 29);
856 int res2 = target_read_u32(target, SAMD_USER_ROW, &val);
857 if (res2 == ERROR_OK) {
858 uint32_t code = (val >> 26) & 0xf; /* grab size code */
859 uint32_t size = (15 - code) * 8192;
860 command_print(CMD, "Bootloader protected in the first %"
861 PRIu32 " bytes", size);
871 COMMAND_HANDLER(samd_handle_reset_deassert)
873 struct target *target = get_current_target(CMD_CTX);
875 enum reset_types jtag_reset_config = jtag_get_reset_config();
879 /* If the target has been unresponsive before, try to re-establish
880 * communication now - CPU is held in reset by DSU, DAP is working */
881 if (!target_was_examined(target))
882 target_examine_one(target);
885 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
886 * so we just release reset held by DSU
888 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
890 * After vectreset DSU release is not needed however makes no harm
892 if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
893 res = target_write_u32(target, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
895 res = target_write_u32(target, DCB_DEMCR,
896 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
897 /* do not return on error here, releasing DSU reset is more important */
900 /* clear CPU Reset Phase Extension bit */
901 int res2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
902 if (res2 != ERROR_OK)
908 static const struct command_registration same5_exec_command_handlers[] = {
910 .name = "dsu_reset_deassert",
912 .handler = samd_handle_reset_deassert,
913 .mode = COMMAND_EXEC,
914 .help = "Deassert internal reset held by DSU."
917 .name = "chip-erase",
919 .handler = same5_handle_chip_erase_command,
920 .mode = COMMAND_EXEC,
921 .help = "Erase the entire Flash by using the Chip-"
922 "Erase feature in the Device Service Unit (DSU).",
925 .name = "bootloader",
926 .usage = "[size_in_bytes]",
927 .handler = same5_handle_bootloader_command,
928 .mode = COMMAND_EXEC,
929 .help = "Show or set the bootloader protection size, stored in the User Row. "
930 "Changes are stored immediately but take affect after the MCU is "
935 .usage = "[value] [mask]",
936 .handler = same5_handle_userpage_command,
937 .mode = COMMAND_EXEC,
938 .help = "Show or set the first 64-bit part of user page "
939 "located at address 0x804000. Use the optional mask argument "
940 "to prevent changes at positions where the bitvalue is zero. "
941 "For security reasons the reserved-bits are masked out "
942 "in background and therefore cannot be changed.",
944 COMMAND_REGISTRATION_DONE
947 static const struct command_registration same5_command_handlers[] = {
951 .help = "atsame5 flash command group",
953 .chain = same5_exec_command_handlers,
955 COMMAND_REGISTRATION_DONE
958 const struct flash_driver atsame5_flash = {
960 .commands = same5_command_handlers,
961 .flash_bank_command = same5_flash_bank_command,
962 .erase = same5_erase,
963 .protect = same5_protect,
964 .write = same5_write,
965 .read = default_flash_read,
966 .probe = same5_probe,
967 .auto_probe = same5_probe,
968 .erase_check = default_flash_blank_check,
969 .protect_check = same5_protect_check,
970 .free_driver_priv = default_flash_free_driver_priv,