1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
26 #include "helper/binarybuffer.h"
28 #include <target/cortex_m.h>
30 #define SAMD_NUM_SECTORS 16
31 #define SAMD_PAGE_SIZE_MAX 1024
33 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
34 #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
35 #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
36 #define SAMD_DSU 0x41002000 /* Device Service Unit */
37 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
39 #define SAMD_DSU_STATUSA 1 /* DSU status register */
40 #define SAMD_DSU_DID 0x18 /* Device ID register */
42 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
43 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
44 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
45 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
46 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
47 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
48 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
50 #define SAMD_CMDEX_KEY 0xA5UL
51 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
53 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
54 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
55 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
56 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
57 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
58 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
59 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
60 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
61 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
62 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
63 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
64 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
67 #define SAMD_NVM_CTRLB_MANW 0x80
69 /* Known identifiers */
70 #define SAMD_PROCESSOR_M0 0x01
71 #define SAMD_FAMILY_D 0x00
72 #define SAMD_FAMILY_L 0x01
73 #define SAMD_FAMILY_C 0x02
74 #define SAMD_SERIES_20 0x00
75 #define SAMD_SERIES_21 0x01
76 #define SAMD_SERIES_22 0x02
77 #define SAMD_SERIES_10 0x02
78 #define SAMD_SERIES_11 0x03
80 /* Device ID macros */
81 #define SAMD_GET_PROCESSOR(id) (id >> 28)
82 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
83 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
84 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
93 /* Known SAMD10 parts */
94 static const struct samd_part samd10_parts[] = {
95 { 0x0, "SAMD10D14AMU", 16, 4 },
96 { 0x1, "SAMD10D13AMU", 8, 4 },
97 { 0x2, "SAMD10D12AMU", 4, 4 },
98 { 0x3, "SAMD10D14ASU", 16, 4 },
99 { 0x4, "SAMD10D13ASU", 8, 4 },
100 { 0x5, "SAMD10D12ASU", 4, 4 },
101 { 0x6, "SAMD10C14A", 16, 4 },
102 { 0x7, "SAMD10C13A", 8, 4 },
103 { 0x8, "SAMD10C12A", 4, 4 },
106 /* Known SAMD11 parts */
107 static const struct samd_part samd11_parts[] = {
108 { 0x0, "SAMD11D14AMU", 16, 4 },
109 { 0x1, "SAMD11D13AMU", 8, 4 },
110 { 0x2, "SAMD11D12AMU", 4, 4 },
111 { 0x3, "SAMD11D14ASU", 16, 4 },
112 { 0x4, "SAMD11D13ASU", 8, 4 },
113 { 0x5, "SAMD11D12ASU", 4, 4 },
114 { 0x6, "SAMD11C14A", 16, 4 },
115 { 0x7, "SAMD11C13A", 8, 4 },
116 { 0x8, "SAMD11C12A", 4, 4 },
119 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
120 static const struct samd_part samd20_parts[] = {
121 { 0x0, "SAMD20J18A", 256, 32 },
122 { 0x1, "SAMD20J17A", 128, 16 },
123 { 0x2, "SAMD20J16A", 64, 8 },
124 { 0x3, "SAMD20J15A", 32, 4 },
125 { 0x4, "SAMD20J14A", 16, 2 },
126 { 0x5, "SAMD20G18A", 256, 32 },
127 { 0x6, "SAMD20G17A", 128, 16 },
128 { 0x7, "SAMD20G16A", 64, 8 },
129 { 0x8, "SAMD20G15A", 32, 4 },
130 { 0x9, "SAMD20G14A", 16, 2 },
131 { 0xA, "SAMD20E18A", 256, 32 },
132 { 0xB, "SAMD20E17A", 128, 16 },
133 { 0xC, "SAMD20E16A", 64, 8 },
134 { 0xD, "SAMD20E15A", 32, 4 },
135 { 0xE, "SAMD20E14A", 16, 2 },
138 /* Known SAMD21 parts. */
139 static const struct samd_part samd21_parts[] = {
140 { 0x0, "SAMD21J18A", 256, 32 },
141 { 0x1, "SAMD21J17A", 128, 16 },
142 { 0x2, "SAMD21J16A", 64, 8 },
143 { 0x3, "SAMD21J15A", 32, 4 },
144 { 0x4, "SAMD21J14A", 16, 2 },
145 { 0x5, "SAMD21G18A", 256, 32 },
146 { 0x6, "SAMD21G17A", 128, 16 },
147 { 0x7, "SAMD21G16A", 64, 8 },
148 { 0x8, "SAMD21G15A", 32, 4 },
149 { 0x9, "SAMD21G14A", 16, 2 },
150 { 0xA, "SAMD21E18A", 256, 32 },
151 { 0xB, "SAMD21E17A", 128, 16 },
152 { 0xC, "SAMD21E16A", 64, 8 },
153 { 0xD, "SAMD21E15A", 32, 4 },
154 { 0xE, "SAMD21E14A", 16, 2 },
155 { 0x26, "SAMD21E16B", 64, 8 },
158 /* Known SAMR21 parts. */
159 static const struct samd_part samr21_parts[] = {
160 { 0x19, "SAMR21G18A", 256, 32 },
161 { 0x1A, "SAMR21G17A", 128, 32 },
162 { 0x1B, "SAMR21G16A", 64, 32 },
163 { 0x1C, "SAMR21E18A", 256, 32 },
164 { 0x1D, "SAMR21E17A", 128, 32 },
165 { 0x1E, "SAMR21E16A", 64, 32 },
168 /* Known SAML21 parts. */
169 static const struct samd_part saml21_parts[] = {
170 { 0x00, "SAML21J18A", 256, 32 },
171 { 0x01, "SAML21J17A", 128, 16 },
172 { 0x02, "SAML21J16A", 64, 8 },
173 { 0x05, "SAML21G18A", 256, 32 },
174 { 0x06, "SAML21G17A", 128, 16 },
175 { 0x07, "SAML21G16A", 64, 8 },
176 { 0x0A, "SAML21E18A", 256, 32 },
177 { 0x0B, "SAML21E17A", 128, 16 },
178 { 0x0C, "SAML21E16A", 64, 8 },
179 { 0x0D, "SAML21E15A", 32, 4 },
180 { 0x0F, "SAML21J18B", 256, 32 },
181 { 0x10, "SAML21J17B", 128, 16 },
182 { 0x11, "SAML21J16B", 64, 8 },
183 { 0x14, "SAML21G18B", 256, 32 },
184 { 0x15, "SAML21G17B", 128, 16 },
185 { 0x16, "SAML21G16B", 64, 8 },
186 { 0x19, "SAML21E18B", 256, 32 },
187 { 0x1A, "SAML21E17B", 128, 16 },
188 { 0x1B, "SAML21E16B", 64, 8 },
189 { 0x1C, "SAML21E15B", 32, 4 },
192 /* Known SAML22 parts. */
193 static const struct samd_part saml22_parts[] = {
194 { 0x00, "SAML22N18A", 256, 32 },
195 { 0x01, "SAML22N17A", 128, 16 },
196 { 0x02, "SAML22N16A", 64, 8 },
197 { 0x05, "SAML22J18A", 256, 32 },
198 { 0x06, "SAML22J17A", 128, 16 },
199 { 0x07, "SAML22J16A", 64, 8 },
200 { 0x0A, "SAML22G18A", 256, 32 },
201 { 0x0B, "SAML22G17A", 128, 16 },
202 { 0x0C, "SAML22G16A", 64, 8 },
205 /* Known SAMC20 parts. */
206 static const struct samd_part samc20_parts[] = {
207 { 0x00, "SAMC20J18A", 256, 32 },
208 { 0x01, "SAMC20J17A", 128, 16 },
209 { 0x02, "SAMC20J16A", 64, 8 },
210 { 0x03, "SAMC20J15A", 32, 4 },
211 { 0x05, "SAMC20G18A", 256, 32 },
212 { 0x06, "SAMC20G17A", 128, 16 },
213 { 0x07, "SAMC20G16A", 64, 8 },
214 { 0x08, "SAMC20G15A", 32, 4 },
215 { 0x0A, "SAMC20E18A", 256, 32 },
216 { 0x0B, "SAMC20E17A", 128, 16 },
217 { 0x0C, "SAMC20E16A", 64, 8 },
218 { 0x0D, "SAMC20E15A", 32, 4 },
221 /* Known SAMC21 parts. */
222 static const struct samd_part samc21_parts[] = {
223 { 0x00, "SAMC21J18A", 256, 32 },
224 { 0x01, "SAMC21J17A", 128, 16 },
225 { 0x02, "SAMC21J16A", 64, 8 },
226 { 0x03, "SAMC21J15A", 32, 4 },
227 { 0x05, "SAMC21G18A", 256, 32 },
228 { 0x06, "SAMC21G17A", 128, 16 },
229 { 0x07, "SAMC21G16A", 64, 8 },
230 { 0x08, "SAMC21G15A", 32, 4 },
231 { 0x0A, "SAMC21E18A", 256, 32 },
232 { 0x0B, "SAMC21E17A", 128, 16 },
233 { 0x0C, "SAMC21E16A", 64, 8 },
234 { 0x0D, "SAMC21E15A", 32, 4 },
237 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
238 * processor ID, family ID, and series ID are used to determine which exact
239 * family this is and then we can use the corresponding table. */
244 const struct samd_part *parts;
248 /* Known SAMD families */
249 static const struct samd_family samd_families[] = {
250 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
251 samd20_parts, ARRAY_SIZE(samd20_parts) },
252 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
253 samd21_parts, ARRAY_SIZE(samd21_parts) },
254 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
255 samr21_parts, ARRAY_SIZE(samr21_parts) },
256 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
257 samd10_parts, ARRAY_SIZE(samd10_parts) },
258 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
259 samd11_parts, ARRAY_SIZE(samd11_parts) },
260 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
261 saml21_parts, ARRAY_SIZE(saml21_parts) },
262 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_22,
263 saml22_parts, ARRAY_SIZE(saml22_parts) },
264 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
265 samc20_parts, ARRAY_SIZE(samc20_parts) },
266 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
267 samc21_parts, ARRAY_SIZE(samc21_parts) },
276 struct target *target;
277 struct samd_info *next;
280 static struct samd_info *samd_chips;
284 static const struct samd_part *samd_find_part(uint32_t id)
286 uint8_t processor = SAMD_GET_PROCESSOR(id);
287 uint8_t family = SAMD_GET_FAMILY(id);
288 uint8_t series = SAMD_GET_SERIES(id);
289 uint8_t devsel = SAMD_GET_DEVSEL(id);
291 for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
292 if (samd_families[i].processor == processor &&
293 samd_families[i].series == series &&
294 samd_families[i].family == family) {
295 for (unsigned j = 0; j < samd_families[i].num_parts; j++) {
296 if (samd_families[i].parts[j].id == devsel)
297 return &samd_families[i].parts[j];
305 static int samd_protect_check(struct flash_bank *bank)
310 res = target_read_u16(bank->target,
311 SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
315 /* Lock bits are active-low */
316 for (int i = 0; i < bank->num_sectors; i++)
317 bank->sectors[i].is_protected = !(lock & (1<<i));
322 static int samd_get_flash_page_info(struct target *target,
323 uint32_t *sizep, int *nump)
328 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, ¶m);
329 if (res == ERROR_OK) {
330 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
331 * so 0 is 8KB and 7 is 1024KB. */
333 *sizep = (8 << ((param >> 16) & 0x7));
334 /* The NVMP field (bits 15:0) indicates the total number of pages */
336 *nump = param & 0xFFFF;
338 LOG_ERROR("Couldn't read NVM Parameters register");
344 static int samd_probe(struct flash_bank *bank)
348 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
349 const struct samd_part *part;
354 res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
355 if (res != ERROR_OK) {
356 LOG_ERROR("Couldn't read Device ID register");
360 part = samd_find_part(id);
362 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32, id);
366 bank->size = part->flash_kb * 1024;
368 chip->sector_size = bank->size / SAMD_NUM_SECTORS;
370 res = samd_get_flash_page_info(bank->target, &chip->page_size,
372 if (res != ERROR_OK) {
373 LOG_ERROR("Couldn't determine Flash page size");
377 /* Sanity check: the total flash size in the DSU should match the page size
378 * multiplied by the number of pages. */
379 if (bank->size != chip->num_pages * chip->page_size) {
380 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
381 "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
382 part->flash_kb, chip->num_pages, chip->page_size);
385 /* Allocate the sector table */
386 bank->num_sectors = SAMD_NUM_SECTORS;
387 bank->sectors = calloc(bank->num_sectors, sizeof((bank->sectors)[0]));
391 /* Fill out the sector information: all SAMD sectors are the same size and
392 * there is always a fixed number of them. */
393 for (int i = 0; i < bank->num_sectors; i++) {
394 bank->sectors[i].size = chip->sector_size;
395 bank->sectors[i].offset = i * chip->sector_size;
396 /* mark as unknown */
397 bank->sectors[i].is_erased = -1;
398 bank->sectors[i].is_protected = -1;
401 samd_protect_check(bank);
406 LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
407 part->flash_kb, part->ram_kb);
412 static bool samd_check_error(struct target *target)
418 ret = target_read_u16(target,
419 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
420 if (ret != ERROR_OK) {
421 LOG_ERROR("Can't read NVM status");
425 if (status & 0x001C) {
426 if (status & (1 << 4)) /* NVME */
427 LOG_ERROR("SAMD: NVM Error");
428 if (status & (1 << 3)) /* LOCKE */
429 LOG_ERROR("SAMD: NVM lock error");
430 if (status & (1 << 2)) /* PROGE */
431 LOG_ERROR("SAMD: NVM programming error");
438 /* Clear the error conditions by writing a one to them */
439 ret = target_write_u16(target,
440 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
442 LOG_ERROR("Can't clear NVM error conditions");
447 static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
451 if (target->state != TARGET_HALTED) {
452 LOG_ERROR("Target not halted");
453 return ERROR_TARGET_NOT_HALTED;
456 /* Issue the NVM command */
457 res = target_write_u16(target,
458 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
462 /* Check to see if the NVM command resulted in an error condition. */
463 if (samd_check_error(target))
469 static int samd_erase_row(struct target *target, uint32_t address)
473 /* Set an address contained in the row to be erased */
474 res = target_write_u32(target,
475 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
477 /* Issue the Erase Row command to erase that row. */
479 res = samd_issue_nvmctrl_command(target,
480 address == SAMD_USER_ROW ? SAMD_NVM_CMD_EAR : SAMD_NVM_CMD_ER);
482 if (res != ERROR_OK) {
483 LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
490 static bool is_user_row_reserved_bit(uint8_t bit)
492 /* See Table 9-3 in the SAMD20 datasheet for more information. */
497 /* Voltage regulator internal configuration with default value of 0x70,
498 * may not be changed. */
500 /* 41 is voltage regulator internal configuration and must not be
501 * changed. 42 through 47 are reserved. */
511 /* Modify the contents of the User Row in Flash. These are described in Table
512 * 9-3 of the SAMD20 datasheet. The User Row itself has a size of one page
513 * and contains a combination of "fuses" and calibration data in bits 24:17.
514 * We therefore try not to erase the row's contents unless we absolutely have
515 * to and we don't permit modifying reserved bits. */
516 static int samd_modify_user_row(struct target *target, uint32_t value,
517 uint8_t startb, uint8_t endb)
521 if (is_user_row_reserved_bit(startb) || is_user_row_reserved_bit(endb)) {
522 LOG_ERROR("Can't modify bits in the requested range");
526 /* Retrieve the MCU's page size, in bytes. This is also the size of the
527 * entire User Row. */
529 res = samd_get_flash_page_info(target, &page_size, NULL);
530 if (res != ERROR_OK) {
531 LOG_ERROR("Couldn't determine Flash page size");
535 /* Make sure the size is sane before we allocate. */
536 assert(page_size > 0 && page_size <= SAMD_PAGE_SIZE_MAX);
538 /* Make sure we're within the single page that comprises the User Row. */
539 if (startb >= (page_size * 8) || endb >= (page_size * 8)) {
540 LOG_ERROR("Can't modify bits outside the User Row page range");
544 uint8_t *buf = malloc(page_size);
548 /* Read the user row (comprising one page) by half-words. */
549 res = target_read_memory(target, SAMD_USER_ROW, 2, page_size / 2, buf);
553 /* We will need to erase before writing if the new value needs a '1' in any
554 * position for which the current value had a '0'. Otherwise we can avoid
556 uint32_t cur = buf_get_u32(buf, startb, endb - startb + 1);
557 if ((~cur) & value) {
558 res = samd_erase_row(target, SAMD_USER_ROW);
559 if (res != ERROR_OK) {
560 LOG_ERROR("Couldn't erase user row");
566 buf_set_u32(buf, startb, endb - startb + 1, value);
568 /* Write the page buffer back out to the target. A Flash write will be
569 * triggered automatically. */
570 res = target_write_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
574 if (samd_check_error(target)) {
588 static int samd_protect(struct flash_bank *bank, int set, int first, int last)
590 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
592 /* We can issue lock/unlock region commands with the target running but
593 * the settings won't persist unless we're able to modify the LOCK regions
594 * and that requires the target to be halted. */
595 if (bank->target->state != TARGET_HALTED) {
596 LOG_ERROR("Target not halted");
597 return ERROR_TARGET_NOT_HALTED;
602 for (int s = first; s <= last; s++) {
603 if (set != bank->sectors[s].is_protected) {
604 /* Load an address that is within this sector (we use offset 0) */
605 res = target_write_u32(bank->target,
606 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
607 ((s * chip->sector_size) >> 1));
611 /* Tell the controller to lock that sector */
612 res = samd_issue_nvmctrl_command(bank->target,
613 set ? SAMD_NVM_CMD_LR : SAMD_NVM_CMD_UR);
619 /* We've now applied our changes, however they will be undone by the next
620 * reset unless we also apply them to the LOCK bits in the User Page. The
621 * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
622 * corresponding to Sector 15. A '1' means unlocked and a '0' means
623 * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
625 res = samd_modify_user_row(bank->target, set ? 0x0000 : 0xFFFF,
626 48 + first, 48 + last);
628 LOG_WARNING("SAMD: protect settings were not made persistent!");
633 samd_protect_check(bank);
638 static int samd_erase(struct flash_bank *bank, int first, int last)
642 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
644 if (bank->target->state != TARGET_HALTED) {
645 LOG_ERROR("Target not halted");
647 return ERROR_TARGET_NOT_HALTED;
651 if (samd_probe(bank) != ERROR_OK)
652 return ERROR_FLASH_BANK_NOT_PROBED;
655 /* The SAMD NVM has row erase granularity. There are four pages in a row
656 * and the number of rows in a sector depends on the sector size, which in
657 * turn depends on the Flash capacity as there is a fixed number of
659 rows_in_sector = chip->sector_size / (chip->page_size * 4);
661 /* For each sector to be erased */
662 for (int s = first; s <= last; s++) {
663 if (bank->sectors[s].is_protected) {
664 LOG_ERROR("SAMD: failed to erase sector %d. That sector is write-protected", s);
665 return ERROR_FLASH_OPERATION_FAILED;
668 /* For each row in that sector */
669 for (int r = s * rows_in_sector; r < (s + 1) * rows_in_sector; r++) {
670 res = samd_erase_row(bank->target, r * chip->page_size * 4);
671 if (res != ERROR_OK) {
672 LOG_ERROR("SAMD: failed to erase sector %d", s);
682 static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
683 uint32_t offset, uint32_t count)
691 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
695 if (bank->target->state != TARGET_HALTED) {
696 LOG_ERROR("Target not halted");
697 return ERROR_TARGET_NOT_HALTED;
701 if (samd_probe(bank) != ERROR_OK)
702 return ERROR_FLASH_BANK_NOT_PROBED;
705 /* Check if we need to do manual page write commands */
706 res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
711 if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
716 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
717 if (res != ERROR_OK) {
718 LOG_ERROR("%s: %d", __func__, __LINE__);
723 nb = chip->page_size - offset % chip->page_size;
727 address = bank->base + offset;
728 pg_offset = offset % chip->page_size;
730 if (offset % 4 || (offset + nb) % 4) {
731 /* Either start or end of write is not word aligned */
733 pb = malloc(chip->page_size);
738 /* Set temporary page buffer to 0xff and overwrite the relevant part */
739 memset(pb, 0xff, chip->page_size);
740 memcpy(pb + pg_offset, buffer, nb);
742 /* Align start address to a word boundary */
743 address -= offset % 4;
744 pg_offset -= offset % 4;
745 assert(pg_offset % 4 == 0);
747 /* Extend length to whole words */
748 nw = (nb + offset % 4 + 3) / 4;
749 assert(pg_offset + 4 * nw <= chip->page_size);
751 /* Now we have original data extended by 0xff bytes
752 * to the nearest word boundary on both start and end */
753 res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
757 assert(pg_offset + 4 * nw <= chip->page_size);
759 /* Word aligned data, use direct write from buffer */
760 res = target_write_memory(bank->target, address, 4, nw, buffer);
762 if (res != ERROR_OK) {
763 LOG_ERROR("%s: %d", __func__, __LINE__);
767 /* Devices with errata 13134 have automatic page write enabled by default
768 * For other devices issue a write page CMD to the NVM
769 * If the page has not been written up to the last word
770 * then issue CMD_WP always */
771 if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
772 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
773 if (res != ERROR_OK) {
774 LOG_ERROR("%s: %d", __func__, __LINE__);
779 /* Access through AHB is stalled while flash is being programmed */
782 if (samd_check_error(bank->target)) {
783 LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
788 /* We're done with the page contents */
801 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
803 struct samd_info *chip = samd_chips;
806 if (chip->target == bank->target)
812 /* Create a new chip */
813 chip = calloc(1, sizeof(*chip));
817 chip->target = bank->target;
818 chip->probed = false;
820 bank->driver_priv = chip;
822 /* Insert it into the chips list (at head) */
823 chip->next = samd_chips;
827 if (bank->base != SAMD_FLASH) {
828 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
829 "[at91samd series] )",
830 bank->base, SAMD_FLASH);
837 COMMAND_HANDLER(samd_handle_info_command)
842 COMMAND_HANDLER(samd_handle_chip_erase_command)
844 struct target *target = get_current_target(CMD_CTX);
847 /* Enable access to the DSU by disabling the write protect bit */
848 target_write_u32(target, SAMD_PAC1, (1<<1));
849 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
850 * perform the erase. */
851 target_write_u8(target, SAMD_DSU, (1<<4));
853 command_print(CMD_CTX, "chip erased");
859 COMMAND_HANDLER(samd_handle_set_security_command)
862 struct target *target = get_current_target(CMD_CTX);
864 if (CMD_ARGC < 1 || (CMD_ARGC >= 1 && (strcmp(CMD_ARGV[0], "enable")))) {
865 command_print(CMD_CTX, "supply the \"enable\" argument to proceed.");
866 return ERROR_COMMAND_SYNTAX_ERROR;
870 if (target->state != TARGET_HALTED) {
871 LOG_ERROR("Target not halted");
872 return ERROR_TARGET_NOT_HALTED;
875 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_SSB);
877 /* Check (and clear) error conditions */
879 command_print(CMD_CTX, "chip secured on next power-cycle");
881 command_print(CMD_CTX, "failed to secure chip");
887 COMMAND_HANDLER(samd_handle_eeprom_command)
890 struct target *target = get_current_target(CMD_CTX);
893 if (target->state != TARGET_HALTED) {
894 LOG_ERROR("Target not halted");
895 return ERROR_TARGET_NOT_HALTED;
899 int val = atoi(CMD_ARGV[0]);
905 /* Try to match size in bytes with corresponding size code */
906 for (code = 0; code <= 6; code++) {
907 if (val == (2 << (13 - code)))
912 command_print(CMD_CTX, "Invalid EEPROM size. Please see "
913 "datasheet for a list valid sizes.");
914 return ERROR_COMMAND_SYNTAX_ERROR;
918 res = samd_modify_user_row(target, code, 4, 6);
921 res = target_read_u16(target, SAMD_USER_ROW, &val);
922 if (res == ERROR_OK) {
923 uint32_t size = ((val >> 4) & 0x7); /* grab size code */
926 command_print(CMD_CTX, "EEPROM is disabled");
928 /* Otherwise, 6 is 256B, 0 is 16KB */
929 command_print(CMD_CTX, "EEPROM size is %u bytes",
939 COMMAND_HANDLER(samd_handle_bootloader_command)
942 struct target *target = get_current_target(CMD_CTX);
945 if (target->state != TARGET_HALTED) {
946 LOG_ERROR("Target not halted");
947 return ERROR_TARGET_NOT_HALTED;
950 /* Retrieve the MCU's page size, in bytes. */
952 res = samd_get_flash_page_info(target, &page_size, NULL);
953 if (res != ERROR_OK) {
954 LOG_ERROR("Couldn't determine Flash page size");
959 int val = atoi(CMD_ARGV[0]);
965 /* Try to match size in bytes with corresponding size code */
966 for (code = 0; code <= 6; code++) {
967 if ((unsigned int)val == (2UL << (8UL - code)) * page_size)
972 command_print(CMD_CTX, "Invalid bootloader size. Please "
973 "see datasheet for a list valid sizes.");
974 return ERROR_COMMAND_SYNTAX_ERROR;
979 res = samd_modify_user_row(target, code, 0, 2);
982 res = target_read_u16(target, SAMD_USER_ROW, &val);
983 if (res == ERROR_OK) {
984 uint32_t size = (val & 0x7); /* grab size code */
990 nb = (2 << (8 - size)) * page_size;
992 /* There are 4 pages per row */
993 command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
994 nb, (uint32_t)(nb / (page_size * 4)));
1004 COMMAND_HANDLER(samd_handle_reset_deassert)
1006 struct target *target = get_current_target(CMD_CTX);
1007 struct armv7m_common *armv7m = target_to_armv7m(target);
1008 int retval = ERROR_OK;
1009 enum reset_types jtag_reset_config = jtag_get_reset_config();
1011 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
1012 * so we just release reset held by DSU
1014 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
1016 * After vectreset DSU release is not needed however makes no harm
1018 if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
1019 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
1020 if (retval == ERROR_OK)
1021 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
1022 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1023 /* do not return on error here, releasing DSU reset is more important */
1026 /* clear CPU Reset Phase Extension bit */
1027 int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
1028 if (retval2 != ERROR_OK)
1034 static const struct command_registration at91samd_exec_command_handlers[] = {
1036 .name = "dsu_reset_deassert",
1037 .handler = samd_handle_reset_deassert,
1038 .mode = COMMAND_EXEC,
1039 .help = "deasert internal reset held by DSU"
1043 .handler = samd_handle_info_command,
1044 .mode = COMMAND_EXEC,
1045 .help = "Print information about the current at91samd chip"
1046 "and its flash configuration.",
1049 .name = "chip-erase",
1050 .handler = samd_handle_chip_erase_command,
1051 .mode = COMMAND_EXEC,
1052 .help = "Erase the entire Flash by using the Chip"
1053 "Erase feature in the Device Service Unit (DSU).",
1056 .name = "set-security",
1057 .handler = samd_handle_set_security_command,
1058 .mode = COMMAND_EXEC,
1059 .help = "Secure the chip's Flash by setting the Security Bit."
1060 "This makes it impossible to read the Flash contents."
1061 "The only way to undo this is to issue the chip-erase"
1066 .usage = "[size_in_bytes]",
1067 .handler = samd_handle_eeprom_command,
1068 .mode = COMMAND_EXEC,
1069 .help = "Show or set the EEPROM size setting, stored in the User Row."
1070 "Please see Table 20-3 of the SAMD20 datasheet for allowed values."
1071 "Changes are stored immediately but take affect after the MCU is"
1075 .name = "bootloader",
1076 .usage = "[size_in_bytes]",
1077 .handler = samd_handle_bootloader_command,
1078 .mode = COMMAND_EXEC,
1079 .help = "Show or set the bootloader size, stored in the User Row."
1080 "Please see Table 20-2 of the SAMD20 datasheet for allowed values."
1081 "Changes are stored immediately but take affect after the MCU is"
1084 COMMAND_REGISTRATION_DONE
1087 static const struct command_registration at91samd_command_handlers[] = {
1090 .mode = COMMAND_ANY,
1091 .help = "at91samd flash command group",
1093 .chain = at91samd_exec_command_handlers,
1095 COMMAND_REGISTRATION_DONE
1098 struct flash_driver at91samd_flash = {
1100 .commands = at91samd_command_handlers,
1101 .flash_bank_command = samd_flash_bank_command,
1102 .erase = samd_erase,
1103 .protect = samd_protect,
1104 .write = samd_write,
1105 .read = default_flash_read,
1106 .probe = samd_probe,
1107 .auto_probe = samd_probe,
1108 .erase_check = default_flash_blank_check,
1109 .protect_check = samd_protect_check,