1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
26 #include "helper/binarybuffer.h"
28 #include <target/cortex_m.h>
30 #define SAMD_NUM_SECTORS 16
31 #define SAMD_PAGE_SIZE_MAX 1024
33 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
34 #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
35 #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
36 #define SAMD_DSU 0x41002000 /* Device Service Unit */
37 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
39 #define SAMD_DSU_STATUSA 1 /* DSU status register */
40 #define SAMD_DSU_DID 0x18 /* Device ID register */
42 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
43 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
44 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
45 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
46 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
47 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
48 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
50 #define SAMD_CMDEX_KEY 0xA5UL
51 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
53 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
54 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
55 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
56 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
57 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
58 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
59 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
60 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
61 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
62 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
63 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
64 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
67 #define SAMD_NVM_CTRLB_MANW 0x80
69 /* Known identifiers */
70 #define SAMD_PROCESSOR_M0 0x01
71 #define SAMD_FAMILY_D 0x00
72 #define SAMD_FAMILY_L 0x01
73 #define SAMD_FAMILY_C 0x02
74 #define SAMD_SERIES_20 0x00
75 #define SAMD_SERIES_21 0x01
76 #define SAMD_SERIES_10 0x02
77 #define SAMD_SERIES_11 0x03
79 /* Device ID macros */
80 #define SAMD_GET_PROCESSOR(id) (id >> 28)
81 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
82 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
83 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
92 /* Known SAMD10 parts */
93 static const struct samd_part samd10_parts[] = {
94 { 0x0, "SAMD10D14AMU", 16, 4 },
95 { 0x1, "SAMD10D13AMU", 8, 4 },
96 { 0x2, "SAMD10D12AMU", 4, 4 },
97 { 0x3, "SAMD10D14ASU", 16, 4 },
98 { 0x4, "SAMD10D13ASU", 8, 4 },
99 { 0x5, "SAMD10D12ASU", 4, 4 },
100 { 0x6, "SAMD10C14A", 16, 4 },
101 { 0x7, "SAMD10C13A", 8, 4 },
102 { 0x8, "SAMD10C12A", 4, 4 },
105 /* Known SAMD11 parts */
106 static const struct samd_part samd11_parts[] = {
107 { 0x0, "SAMD11D14AMU", 16, 4 },
108 { 0x1, "SAMD11D13AMU", 8, 4 },
109 { 0x2, "SAMD11D12AMU", 4, 4 },
110 { 0x3, "SAMD11D14ASU", 16, 4 },
111 { 0x4, "SAMD11D13ASU", 8, 4 },
112 { 0x5, "SAMD11D12ASU", 4, 4 },
113 { 0x6, "SAMD11C14A", 16, 4 },
114 { 0x7, "SAMD11C13A", 8, 4 },
115 { 0x8, "SAMD11C12A", 4, 4 },
118 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
119 static const struct samd_part samd20_parts[] = {
120 { 0x0, "SAMD20J18A", 256, 32 },
121 { 0x1, "SAMD20J17A", 128, 16 },
122 { 0x2, "SAMD20J16A", 64, 8 },
123 { 0x3, "SAMD20J15A", 32, 4 },
124 { 0x4, "SAMD20J14A", 16, 2 },
125 { 0x5, "SAMD20G18A", 256, 32 },
126 { 0x6, "SAMD20G17A", 128, 16 },
127 { 0x7, "SAMD20G16A", 64, 8 },
128 { 0x8, "SAMD20G15A", 32, 4 },
129 { 0x9, "SAMD20G14A", 16, 2 },
130 { 0xA, "SAMD20E18A", 256, 32 },
131 { 0xB, "SAMD20E17A", 128, 16 },
132 { 0xC, "SAMD20E16A", 64, 8 },
133 { 0xD, "SAMD20E15A", 32, 4 },
134 { 0xE, "SAMD20E14A", 16, 2 },
137 /* Known SAMD21 parts. */
138 static const struct samd_part samd21_parts[] = {
139 { 0x0, "SAMD21J18A", 256, 32 },
140 { 0x1, "SAMD21J17A", 128, 16 },
141 { 0x2, "SAMD21J16A", 64, 8 },
142 { 0x3, "SAMD21J15A", 32, 4 },
143 { 0x4, "SAMD21J14A", 16, 2 },
144 { 0x5, "SAMD21G18A", 256, 32 },
145 { 0x6, "SAMD21G17A", 128, 16 },
146 { 0x7, "SAMD21G16A", 64, 8 },
147 { 0x8, "SAMD21G15A", 32, 4 },
148 { 0x9, "SAMD21G14A", 16, 2 },
149 { 0xA, "SAMD21E18A", 256, 32 },
150 { 0xB, "SAMD21E17A", 128, 16 },
151 { 0xC, "SAMD21E16A", 64, 8 },
152 { 0xD, "SAMD21E15A", 32, 4 },
153 { 0xE, "SAMD21E14A", 16, 2 },
156 /* Known SAMR21 parts. */
157 static const struct samd_part samr21_parts[] = {
158 { 0x19, "SAMR21G18A", 256, 32 },
159 { 0x1A, "SAMR21G17A", 128, 32 },
160 { 0x1B, "SAMR21G16A", 64, 32 },
161 { 0x1C, "SAMR21E18A", 256, 32 },
162 { 0x1D, "SAMR21E17A", 128, 32 },
163 { 0x1E, "SAMR21E16A", 64, 32 },
166 /* Known SAML21 parts. */
167 static const struct samd_part saml21_parts[] = {
168 { 0x00, "SAML21J18A", 256, 32 },
169 { 0x01, "SAML21J17A", 128, 16 },
170 { 0x02, "SAML21J16A", 64, 8 },
171 { 0x05, "SAML21G18A", 256, 32 },
172 { 0x06, "SAML21G17A", 128, 16 },
173 { 0x07, "SAML21G16A", 64, 8 },
174 { 0x0A, "SAML21E18A", 256, 32 },
175 { 0x0B, "SAML21E17A", 128, 16 },
176 { 0x0C, "SAML21E16A", 64, 8 },
177 { 0x0D, "SAML21E15A", 32, 4 },
178 { 0x0F, "SAML21J18B", 256, 32 },
179 { 0x10, "SAML21J17B", 128, 16 },
180 { 0x11, "SAML21J16B", 64, 8 },
181 { 0x14, "SAML21G18B", 256, 32 },
182 { 0x15, "SAML21G17B", 128, 16 },
183 { 0x16, "SAML21G16B", 64, 8 },
184 { 0x19, "SAML21E18B", 256, 32 },
185 { 0x1A, "SAML21E17B", 128, 16 },
186 { 0x1B, "SAML21E16B", 64, 8 },
187 { 0x1C, "SAML21E15B", 32, 4 },
190 /* Known SAMC20 parts. */
191 static const struct samd_part samc20_parts[] = {
192 { 0x00, "SAMC20J18A", 256, 32 },
193 { 0x01, "SAMC20J17A", 128, 16 },
194 { 0x02, "SAMC20J16A", 64, 8 },
195 { 0x03, "SAMC20J15A", 32, 4 },
196 { 0x05, "SAMC20G18A", 256, 32 },
197 { 0x06, "SAMC20G17A", 128, 16 },
198 { 0x07, "SAMC20G16A", 64, 8 },
199 { 0x08, "SAMC20G15A", 32, 4 },
200 { 0x0A, "SAMC20E18A", 256, 32 },
201 { 0x0B, "SAMC20E17A", 128, 16 },
202 { 0x0C, "SAMC20E16A", 64, 8 },
203 { 0x0D, "SAMC20E15A", 32, 4 },
206 /* Known SAMC21 parts. */
207 static const struct samd_part samc21_parts[] = {
208 { 0x00, "SAMC21J18A", 256, 32 },
209 { 0x01, "SAMC21J17A", 128, 16 },
210 { 0x02, "SAMC21J16A", 64, 8 },
211 { 0x03, "SAMC21J15A", 32, 4 },
212 { 0x05, "SAMC21G18A", 256, 32 },
213 { 0x06, "SAMC21G17A", 128, 16 },
214 { 0x07, "SAMC21G16A", 64, 8 },
215 { 0x08, "SAMC21G15A", 32, 4 },
216 { 0x0A, "SAMC21E18A", 256, 32 },
217 { 0x0B, "SAMC21E17A", 128, 16 },
218 { 0x0C, "SAMC21E16A", 64, 8 },
219 { 0x0D, "SAMC21E15A", 32, 4 },
222 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
223 * processor ID, family ID, and series ID are used to determine which exact
224 * family this is and then we can use the corresponding table. */
229 const struct samd_part *parts;
233 /* Known SAMD families */
234 static const struct samd_family samd_families[] = {
235 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
236 samd20_parts, ARRAY_SIZE(samd20_parts) },
237 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
238 samd21_parts, ARRAY_SIZE(samd21_parts) },
239 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
240 samr21_parts, ARRAY_SIZE(samr21_parts) },
241 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
242 samd10_parts, ARRAY_SIZE(samd10_parts) },
243 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
244 samd11_parts, ARRAY_SIZE(samd11_parts) },
245 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
246 saml21_parts, ARRAY_SIZE(saml21_parts) },
247 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
248 samc20_parts, ARRAY_SIZE(samc20_parts) },
249 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
250 samc21_parts, ARRAY_SIZE(samc21_parts) },
259 struct target *target;
260 struct samd_info *next;
263 static struct samd_info *samd_chips;
267 static const struct samd_part *samd_find_part(uint32_t id)
269 uint8_t processor = SAMD_GET_PROCESSOR(id);
270 uint8_t family = SAMD_GET_FAMILY(id);
271 uint8_t series = SAMD_GET_SERIES(id);
272 uint8_t devsel = SAMD_GET_DEVSEL(id);
274 for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
275 if (samd_families[i].processor == processor &&
276 samd_families[i].series == series &&
277 samd_families[i].family == family) {
278 for (unsigned j = 0; j < samd_families[i].num_parts; j++) {
279 if (samd_families[i].parts[j].id == devsel)
280 return &samd_families[i].parts[j];
288 static int samd_protect_check(struct flash_bank *bank)
293 res = target_read_u16(bank->target,
294 SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
298 /* Lock bits are active-low */
299 for (int i = 0; i < bank->num_sectors; i++)
300 bank->sectors[i].is_protected = !(lock & (1<<i));
305 static int samd_get_flash_page_info(struct target *target,
306 uint32_t *sizep, int *nump)
311 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, ¶m);
312 if (res == ERROR_OK) {
313 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
314 * so 0 is 8KB and 7 is 1024KB. */
316 *sizep = (8 << ((param >> 16) & 0x7));
317 /* The NVMP field (bits 15:0) indicates the total number of pages */
319 *nump = param & 0xFFFF;
321 LOG_ERROR("Couldn't read NVM Parameters register");
327 static int samd_probe(struct flash_bank *bank)
331 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
332 const struct samd_part *part;
337 res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
338 if (res != ERROR_OK) {
339 LOG_ERROR("Couldn't read Device ID register");
343 part = samd_find_part(id);
345 LOG_ERROR("Couldn't find part correspoding to DID %08" PRIx32, id);
349 bank->size = part->flash_kb * 1024;
351 chip->sector_size = bank->size / SAMD_NUM_SECTORS;
353 res = samd_get_flash_page_info(bank->target, &chip->page_size,
355 if (res != ERROR_OK) {
356 LOG_ERROR("Couldn't determine Flash page size");
360 /* Sanity check: the total flash size in the DSU should match the page size
361 * multiplied by the number of pages. */
362 if (bank->size != chip->num_pages * chip->page_size) {
363 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
364 "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
365 part->flash_kb, chip->num_pages, chip->page_size);
368 /* Allocate the sector table */
369 bank->num_sectors = SAMD_NUM_SECTORS;
370 bank->sectors = calloc(bank->num_sectors, sizeof((bank->sectors)[0]));
374 /* Fill out the sector information: all SAMD sectors are the same size and
375 * there is always a fixed number of them. */
376 for (int i = 0; i < bank->num_sectors; i++) {
377 bank->sectors[i].size = chip->sector_size;
378 bank->sectors[i].offset = i * chip->sector_size;
379 /* mark as unknown */
380 bank->sectors[i].is_erased = -1;
381 bank->sectors[i].is_protected = -1;
384 samd_protect_check(bank);
389 LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
390 part->flash_kb, part->ram_kb);
395 static bool samd_check_error(struct target *target)
401 ret = target_read_u16(target,
402 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
403 if (ret != ERROR_OK) {
404 LOG_ERROR("Can't read NVM status");
408 if (status & 0x001C) {
409 if (status & (1 << 4)) /* NVME */
410 LOG_ERROR("SAMD: NVM Error");
411 if (status & (1 << 3)) /* LOCKE */
412 LOG_ERROR("SAMD: NVM lock error");
413 if (status & (1 << 2)) /* PROGE */
414 LOG_ERROR("SAMD: NVM programming error");
421 /* Clear the error conditions by writing a one to them */
422 ret = target_write_u16(target,
423 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
425 LOG_ERROR("Can't clear NVM error conditions");
430 static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
434 if (target->state != TARGET_HALTED) {
435 LOG_ERROR("Target not halted");
436 return ERROR_TARGET_NOT_HALTED;
439 /* Issue the NVM command */
440 res = target_write_u16(target,
441 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
445 /* Check to see if the NVM command resulted in an error condition. */
446 if (samd_check_error(target))
452 static int samd_erase_row(struct target *target, uint32_t address)
456 /* Set an address contained in the row to be erased */
457 res = target_write_u32(target,
458 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
460 /* Issue the Erase Row command to erase that row. */
462 res = samd_issue_nvmctrl_command(target,
463 address == SAMD_USER_ROW ? SAMD_NVM_CMD_EAR : SAMD_NVM_CMD_ER);
465 if (res != ERROR_OK) {
466 LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
473 static bool is_user_row_reserved_bit(uint8_t bit)
475 /* See Table 9-3 in the SAMD20 datasheet for more information. */
480 /* Voltage regulator internal configuration with default value of 0x70,
481 * may not be changed. */
483 /* 41 is voltage regulator internal configuration and must not be
484 * changed. 42 through 47 are reserved. */
494 /* Modify the contents of the User Row in Flash. These are described in Table
495 * 9-3 of the SAMD20 datasheet. The User Row itself has a size of one page
496 * and contains a combination of "fuses" and calibration data in bits 24:17.
497 * We therefore try not to erase the row's contents unless we absolutely have
498 * to and we don't permit modifying reserved bits. */
499 static int samd_modify_user_row(struct target *target, uint32_t value,
500 uint8_t startb, uint8_t endb)
504 if (is_user_row_reserved_bit(startb) || is_user_row_reserved_bit(endb)) {
505 LOG_ERROR("Can't modify bits in the requested range");
509 /* Retrieve the MCU's page size, in bytes. This is also the size of the
510 * entire User Row. */
512 res = samd_get_flash_page_info(target, &page_size, NULL);
513 if (res != ERROR_OK) {
514 LOG_ERROR("Couldn't determine Flash page size");
518 /* Make sure the size is sane before we allocate. */
519 assert(page_size > 0 && page_size <= SAMD_PAGE_SIZE_MAX);
521 /* Make sure we're within the single page that comprises the User Row. */
522 if (startb >= (page_size * 8) || endb >= (page_size * 8)) {
523 LOG_ERROR("Can't modify bits outside the User Row page range");
527 uint8_t *buf = malloc(page_size);
531 /* Read the user row (comprising one page) by half-words. */
532 res = target_read_memory(target, SAMD_USER_ROW, 2, page_size / 2, buf);
536 /* We will need to erase before writing if the new value needs a '1' in any
537 * position for which the current value had a '0'. Otherwise we can avoid
539 uint32_t cur = buf_get_u32(buf, startb, endb - startb + 1);
540 if ((~cur) & value) {
541 res = samd_erase_row(target, SAMD_USER_ROW);
542 if (res != ERROR_OK) {
543 LOG_ERROR("Couldn't erase user row");
549 buf_set_u32(buf, startb, endb - startb + 1, value);
551 /* Write the page buffer back out to the target. A Flash write will be
552 * triggered automatically. */
553 res = target_write_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
557 if (samd_check_error(target)) {
571 static int samd_protect(struct flash_bank *bank, int set, int first, int last)
573 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
575 /* We can issue lock/unlock region commands with the target running but
576 * the settings won't persist unless we're able to modify the LOCK regions
577 * and that requires the target to be halted. */
578 if (bank->target->state != TARGET_HALTED) {
579 LOG_ERROR("Target not halted");
580 return ERROR_TARGET_NOT_HALTED;
585 for (int s = first; s <= last; s++) {
586 if (set != bank->sectors[s].is_protected) {
587 /* Load an address that is within this sector (we use offset 0) */
588 res = target_write_u32(bank->target,
589 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
590 ((s * chip->sector_size) >> 1));
594 /* Tell the controller to lock that sector */
595 res = samd_issue_nvmctrl_command(bank->target,
596 set ? SAMD_NVM_CMD_LR : SAMD_NVM_CMD_UR);
602 /* We've now applied our changes, however they will be undone by the next
603 * reset unless we also apply them to the LOCK bits in the User Page. The
604 * LOCK bits start at bit 48, correspoding to Sector 0 and end with bit 63,
605 * corresponding to Sector 15. A '1' means unlocked and a '0' means
606 * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
608 res = samd_modify_user_row(bank->target, set ? 0x0000 : 0xFFFF,
609 48 + first, 48 + last);
611 LOG_WARNING("SAMD: protect settings were not made persistent!");
616 samd_protect_check(bank);
621 static int samd_erase(struct flash_bank *bank, int first, int last)
625 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
627 if (bank->target->state != TARGET_HALTED) {
628 LOG_ERROR("Target not halted");
630 return ERROR_TARGET_NOT_HALTED;
634 if (samd_probe(bank) != ERROR_OK)
635 return ERROR_FLASH_BANK_NOT_PROBED;
638 /* The SAMD NVM has row erase granularity. There are four pages in a row
639 * and the number of rows in a sector depends on the sector size, which in
640 * turn depends on the Flash capacity as there is a fixed number of
642 rows_in_sector = chip->sector_size / (chip->page_size * 4);
644 /* For each sector to be erased */
645 for (int s = first; s <= last; s++) {
646 if (bank->sectors[s].is_protected) {
647 LOG_ERROR("SAMD: failed to erase sector %d. That sector is write-protected", s);
648 return ERROR_FLASH_OPERATION_FAILED;
651 /* For each row in that sector */
652 for (int r = s * rows_in_sector; r < (s + 1) * rows_in_sector; r++) {
653 res = samd_erase_row(bank->target, r * chip->page_size * 4);
654 if (res != ERROR_OK) {
655 LOG_ERROR("SAMD: failed to erase sector %d", s);
665 static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
666 uint32_t offset, uint32_t count)
674 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
678 if (bank->target->state != TARGET_HALTED) {
679 LOG_ERROR("Target not halted");
680 return ERROR_TARGET_NOT_HALTED;
684 if (samd_probe(bank) != ERROR_OK)
685 return ERROR_FLASH_BANK_NOT_PROBED;
688 /* Check if we need to do manual page write commands */
689 res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
694 if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
699 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
700 if (res != ERROR_OK) {
701 LOG_ERROR("%s: %d", __func__, __LINE__);
706 nb = chip->page_size - offset % chip->page_size;
710 address = bank->base + offset;
711 pg_offset = offset % chip->page_size;
713 if (offset % 4 || (offset + nb) % 4) {
714 /* Either start or end of write is not word aligned */
716 pb = malloc(chip->page_size);
721 /* Set temporary page buffer to 0xff and overwrite the relevant part */
722 memset(pb, 0xff, chip->page_size);
723 memcpy(pb + pg_offset, buffer, nb);
725 /* Align start address to a word boundary */
726 address -= offset % 4;
727 pg_offset -= offset % 4;
728 assert(pg_offset % 4 == 0);
730 /* Extend length to whole words */
731 nw = (nb + offset % 4 + 3) / 4;
732 assert(pg_offset + 4 * nw <= chip->page_size);
734 /* Now we have original data extended by 0xff bytes
735 * to the nearest word boundary on both start and end */
736 res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
740 assert(pg_offset + 4 * nw <= chip->page_size);
742 /* Word aligned data, use direct write from buffer */
743 res = target_write_memory(bank->target, address, 4, nw, buffer);
745 if (res != ERROR_OK) {
746 LOG_ERROR("%s: %d", __func__, __LINE__);
750 /* Devices with errata 13134 have automatic page write enabled by default
751 * For other devices issue a write page CMD to the NVM
752 * If the page has not been written up to the last word
753 * then issue CMD_WP always */
754 if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
755 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
756 if (res != ERROR_OK) {
757 LOG_ERROR("%s: %d", __func__, __LINE__);
762 /* Access through AHB is stalled while flash is being programmed */
765 if (samd_check_error(bank->target)) {
766 LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
771 /* We're done with the page contents */
784 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
786 struct samd_info *chip = samd_chips;
789 if (chip->target == bank->target)
795 /* Create a new chip */
796 chip = calloc(1, sizeof(*chip));
800 chip->target = bank->target;
801 chip->probed = false;
803 bank->driver_priv = chip;
805 /* Insert it into the chips list (at head) */
806 chip->next = samd_chips;
810 if (bank->base != SAMD_FLASH) {
811 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
812 "[at91samd series] )",
813 bank->base, SAMD_FLASH);
820 COMMAND_HANDLER(samd_handle_info_command)
825 COMMAND_HANDLER(samd_handle_chip_erase_command)
827 struct target *target = get_current_target(CMD_CTX);
830 /* Enable access to the DSU by disabling the write protect bit */
831 target_write_u32(target, SAMD_PAC1, (1<<1));
832 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
833 * perform the erase. */
834 target_write_u8(target, SAMD_DSU, (1<<4));
836 command_print(CMD_CTX, "chip erased");
842 COMMAND_HANDLER(samd_handle_set_security_command)
845 struct target *target = get_current_target(CMD_CTX);
847 if (CMD_ARGC < 1 || (CMD_ARGC >= 1 && (strcmp(CMD_ARGV[0], "enable")))) {
848 command_print(CMD_CTX, "supply the \"enable\" argument to proceed.");
849 return ERROR_COMMAND_SYNTAX_ERROR;
853 if (target->state != TARGET_HALTED) {
854 LOG_ERROR("Target not halted");
855 return ERROR_TARGET_NOT_HALTED;
858 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_SSB);
860 /* Check (and clear) error conditions */
862 command_print(CMD_CTX, "chip secured on next power-cycle");
864 command_print(CMD_CTX, "failed to secure chip");
870 COMMAND_HANDLER(samd_handle_eeprom_command)
873 struct target *target = get_current_target(CMD_CTX);
876 if (target->state != TARGET_HALTED) {
877 LOG_ERROR("Target not halted");
878 return ERROR_TARGET_NOT_HALTED;
882 int val = atoi(CMD_ARGV[0]);
888 /* Try to match size in bytes with corresponding size code */
889 for (code = 0; code <= 6; code++) {
890 if (val == (2 << (13 - code)))
895 command_print(CMD_CTX, "Invalid EEPROM size. Please see "
896 "datasheet for a list valid sizes.");
897 return ERROR_COMMAND_SYNTAX_ERROR;
901 res = samd_modify_user_row(target, code, 4, 6);
904 res = target_read_u16(target, SAMD_USER_ROW, &val);
905 if (res == ERROR_OK) {
906 uint32_t size = ((val >> 4) & 0x7); /* grab size code */
909 command_print(CMD_CTX, "EEPROM is disabled");
911 /* Otherwise, 6 is 256B, 0 is 16KB */
912 command_print(CMD_CTX, "EEPROM size is %u bytes",
922 COMMAND_HANDLER(samd_handle_bootloader_command)
925 struct target *target = get_current_target(CMD_CTX);
928 if (target->state != TARGET_HALTED) {
929 LOG_ERROR("Target not halted");
930 return ERROR_TARGET_NOT_HALTED;
933 /* Retrieve the MCU's page size, in bytes. */
935 res = samd_get_flash_page_info(target, &page_size, NULL);
936 if (res != ERROR_OK) {
937 LOG_ERROR("Couldn't determine Flash page size");
942 int val = atoi(CMD_ARGV[0]);
948 /* Try to match size in bytes with corresponding size code */
949 for (code = 0; code <= 6; code++) {
950 if ((unsigned int)val == (2UL << (8UL - code)) * page_size)
955 command_print(CMD_CTX, "Invalid bootloader size. Please "
956 "see datasheet for a list valid sizes.");
957 return ERROR_COMMAND_SYNTAX_ERROR;
962 res = samd_modify_user_row(target, code, 0, 2);
965 res = target_read_u16(target, SAMD_USER_ROW, &val);
966 if (res == ERROR_OK) {
967 uint32_t size = (val & 0x7); /* grab size code */
973 nb = (2 << (8 - size)) * page_size;
975 /* There are 4 pages per row */
976 command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
977 nb, (uint32_t)(nb / (page_size * 4)));
987 COMMAND_HANDLER(samd_handle_reset_deassert)
989 struct target *target = get_current_target(CMD_CTX);
990 struct armv7m_common *armv7m = target_to_armv7m(target);
991 int retval = ERROR_OK;
992 enum reset_types jtag_reset_config = jtag_get_reset_config();
994 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
995 * so we just release reset held by DSU
997 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
999 * After vectreset DSU release is not needed however makes no harm
1001 if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
1002 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
1003 if (retval == ERROR_OK)
1004 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
1005 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1006 /* do not return on error here, releasing DSU reset is more important */
1009 /* clear CPU Reset Phase Extension bit */
1010 int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
1011 if (retval2 != ERROR_OK)
1017 static const struct command_registration at91samd_exec_command_handlers[] = {
1019 .name = "dsu_reset_deassert",
1020 .handler = samd_handle_reset_deassert,
1021 .mode = COMMAND_EXEC,
1022 .help = "deasert internal reset held by DSU"
1026 .handler = samd_handle_info_command,
1027 .mode = COMMAND_EXEC,
1028 .help = "Print information about the current at91samd chip"
1029 "and its flash configuration.",
1032 .name = "chip-erase",
1033 .handler = samd_handle_chip_erase_command,
1034 .mode = COMMAND_EXEC,
1035 .help = "Erase the entire Flash by using the Chip"
1036 "Erase feature in the Device Service Unit (DSU).",
1039 .name = "set-security",
1040 .handler = samd_handle_set_security_command,
1041 .mode = COMMAND_EXEC,
1042 .help = "Secure the chip's Flash by setting the Security Bit."
1043 "This makes it impossible to read the Flash contents."
1044 "The only way to undo this is to issue the chip-erase"
1049 .usage = "[size_in_bytes]",
1050 .handler = samd_handle_eeprom_command,
1051 .mode = COMMAND_EXEC,
1052 .help = "Show or set the EEPROM size setting, stored in the User Row."
1053 "Please see Table 20-3 of the SAMD20 datasheet for allowed values."
1054 "Changes are stored immediately but take affect after the MCU is"
1058 .name = "bootloader",
1059 .usage = "[size_in_bytes]",
1060 .handler = samd_handle_bootloader_command,
1061 .mode = COMMAND_EXEC,
1062 .help = "Show or set the bootloader size, stored in the User Row."
1063 "Please see Table 20-2 of the SAMD20 datasheet for allowed values."
1064 "Changes are stored immediately but take affect after the MCU is"
1067 COMMAND_REGISTRATION_DONE
1070 static const struct command_registration at91samd_command_handlers[] = {
1073 .mode = COMMAND_ANY,
1074 .help = "at91samd flash command group",
1076 .chain = at91samd_exec_command_handlers,
1078 COMMAND_REGISTRATION_DONE
1081 struct flash_driver at91samd_flash = {
1083 .commands = at91samd_command_handlers,
1084 .flash_bank_command = samd_flash_bank_command,
1085 .erase = samd_erase,
1086 .protect = samd_protect,
1087 .write = samd_write,
1088 .read = default_flash_read,
1089 .probe = samd_probe,
1090 .auto_probe = samd_probe,
1091 .erase_check = default_flash_blank_check,
1092 .protect_check = samd_protect_check,