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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Gheorghe Guran (atlas)                          *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21 ****************************************************************************/
  22
  23 /***************************************************************************
  24 *
  25 * New flash setup command:
  26 *
  27 * flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_id>
  28 *       [<chip_type> <banks>
  29 *        <sectors_per_bank> <pages_per_sector>
  30 *        <page_size> <num_nvmbits>
  31 *        <ext_freq_khz>]
  32 *
  33 *   <ext_freq_khz> - MUST be used if clock is from external source,
  34 *                    CAN be used if main oscillator frequency is known (recommended)
  35 * Examples:
  36 * ==== RECOMMENDED (covers clock speed) ============
  37 *  flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 25000
  38 *                       (if auto-detect fails; provides clock spec)
  39 *  flash bank at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 25000
  40 *                       (auto-detect everything except the clock)
  41 * ==== NOT RECOMMENDED !!! (clock speed is not configured) ====
  42 *  flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 0
  43 *                       (if auto-detect fails)
  44 *  flash bank at91sam7 0 0 0 0 $_TARGETNAME
  45 *                       (old style, auto-detect everything)
  46 ****************************************************************************/
  47
  48 #ifdef HAVE_CONFIG_H
  49 #include "config.h"
  50 #endif
  51
  52 #include "imp.h"
  53 #include <helper/binarybuffer.h>
  54
  55
  56 /* AT91SAM7 control registers */
  57 #define DBGU_CIDR                       0xFFFFF240
  58 #define CKGR_MCFR                       0xFFFFFC24
  59 #define CKGR_MOR                        0xFFFFFC20
  60 #define CKGR_MCFR_MAINRDY       0x10000
  61 #define CKGR_PLLR                       0xFFFFFC2c
  62 #define CKGR_PLLR_DIV           0xff
  63 #define CKGR_PLLR_MUL           0x07ff0000
  64 #define PMC_MCKR                        0xFFFFFC30
  65 #define PMC_MCKR_CSS            0x03
  66 #define PMC_MCKR_PRES           0x1c
  67
  68 /* Flash Controller Commands */
  69 #define WP              0x01
  70 #define SLB             0x02
  71 #define WPL             0x03
  72 #define CLB             0x04
  73 #define EA              0x08
  74 #define SGPB    0x0B
  75 #define CGPB    0x0D
  76 #define SSB             0x0F
  77
  78 /* MC_FSR bit definitions */
  79 #define MC_FSR_FRDY                     1
  80 #define MC_FSR_EOL                      2
  81
  82 /* AT91SAM7 constants */
  83 #define RC_FREQ                         32000
  84
  85 /* Flash timing modes */
  86 #define FMR_TIMING_NONE         0
  87 #define FMR_TIMING_NVBITS       1
  88 #define FMR_TIMING_FLASH        2
  89
  90 /* Flash size constants */
  91 #define FLASH_SIZE_8KB          1
  92 #define FLASH_SIZE_16KB         2
  93 #define FLASH_SIZE_32KB         3
  94 #define FLASH_SIZE_64KB         5
  95 #define FLASH_SIZE_128KB        7
  96 #define FLASH_SIZE_256KB        9
  97 #define FLASH_SIZE_512KB        10
  98 #define FLASH_SIZE_1024KB       12
  99 #define FLASH_SIZE_2048KB       14
 100
 101
 102 static int at91sam7_protect_check(struct flash_bank *bank);
 103 static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
 104
 105 static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number);
 106 static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode);
 107 static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout);
 108 static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t pagen);
 109
 110 static uint32_t MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
 111 static uint32_t MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
 112 static uint32_t MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
 113
 114 static char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
 115
 116 struct at91sam7_flash_bank
 117 {
 118         /* chip id register */
 119         uint32_t cidr;
 120         uint16_t cidr_ext;
 121         uint16_t cidr_nvptyp;
 122         uint16_t cidr_arch;
 123         uint16_t cidr_sramsiz;
 124         uint16_t cidr_nvpsiz;
 125         uint16_t cidr_nvpsiz2;
 126         uint16_t cidr_eproc;
 127         uint16_t cidr_version;
 128         const char *target_name;
 129
 130         /* flash auto-detection */
 131         uint8_t  flash_autodetection;
 132
 133         /* flash geometry */
 134         uint16_t pages_per_sector;
 135         uint16_t pagesize;
 136         uint16_t pages_in_lockregion;
 137
 138         /* nv memory bits */
 139         uint16_t num_lockbits_on;
 140         uint16_t lockbits;
 141         uint16_t num_nvmbits;
 142         uint16_t num_nvmbits_on;
 143         uint16_t nvmbits;
 144         uint8_t  securitybit;
 145
 146         /* 0: not init
 147          * 1: fmcn for nvbits (1uS)
 148          * 2: fmcn for flash (1.5uS) */
 149         uint8_t  flashmode;
 150
 151         /* main clock status */
 152         uint8_t  mck_valid;
 153         uint32_t mck_freq;
 154
 155         /* external clock frequency */
 156         uint32_t ext_freq;
 157
 158 };
 159
 160 #if 0
 161 static long SRAMSIZ[16] = {
 162         -1,
 163         0x0400,         /*  1K */
 164         0x0800,         /*  2K */
 165         -1,
 166         0x1c000,        /* 112K */
 167         0x1000,         /*   4K */
 168         0x14000,        /*  80K */
 169         0x28000,        /* 160K */
 170         0x2000,         /*   8K */
 171         0x4000,         /*  16K */
 172         0x8000,         /*  32K */
 173         0x10000,        /*  64K */
 174         0x20000,        /* 128K */
 175         0x40000,        /* 256K */
 176         0x18000,        /*  96K */
 177         0x80000,        /* 512K */
 178 };
 179 #endif
 180
 181
 182 static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number)
 183 {
 184         uint32_t fsr;
 185         target_read_u32(target, MC_FSR[bank_number], &fsr);
 186
 187         return fsr;
 188 }
 189
 190 /* Read clock configuration and set at91sam7_info->mck_freq */
 191 static void at91sam7_read_clock_info(struct flash_bank *bank)
 192 {
 193         struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
 194         struct target *target = bank->target;
 195         uint32_t mckr, mcfr, pllr, mor;
 196         unsigned long tmp = 0, mainfreq;
 197
 198         /* Read Clock Generator Main Oscillator Register */
 199         target_read_u32(target, CKGR_MOR, &mor);
 200         /* Read Clock Generator Main Clock Frequency Register */
 201         target_read_u32(target, CKGR_MCFR, &mcfr);
 202         /* Read Master Clock Register*/
 203         target_read_u32(target, PMC_MCKR, &mckr);
 204         /* Read Clock Generator PLL Register  */
 205         target_read_u32(target, CKGR_PLLR, &pllr);
 206
 207         at91sam7_info->mck_valid = 0;
 208         at91sam7_info->mck_freq = 0;
 209         switch (mckr & PMC_MCKR_CSS)
 210         {
 211                 case 0:                 /* Slow Clock */
 212                         at91sam7_info->mck_valid = 1;
 213                         tmp = RC_FREQ;
 214                         break;
 215
 216                 case 1:                 /* Main Clock */
 217                         if ((mcfr & CKGR_MCFR_MAINRDY) &&
 218                                 (at91sam7_info->ext_freq == 0))
 219                         {
 220                                 at91sam7_info->mck_valid = 1;
 221                                 tmp = RC_FREQ / 16ul * (mcfr & 0xffff);
 222                         }
 223                         else if (at91sam7_info->ext_freq != 0)
 224                         {
 225                                 at91sam7_info->mck_valid = 1;
 226                                 tmp = at91sam7_info->ext_freq;
 227                         }
 228                         break;
 229
 230                 case 2:                 /* Reserved */
 231                         break;
 232
 233                 case 3:                 /* PLL Clock */
 234                         if ((mcfr & CKGR_MCFR_MAINRDY) &&
 235                                 (at91sam7_info->ext_freq == 0))
 236                         {
 237                                 target_read_u32(target, CKGR_PLLR, &pllr);
 238                                 if (!(pllr & CKGR_PLLR_DIV))
 239                                         break; /* 0 Hz */
 240                                 at91sam7_info->mck_valid = 1;
 241                                 mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
 242                                 /* Integer arithmetic should have sufficient precision
 243                                  * as long as PLL is properly configured. */
 244                                 tmp = mainfreq / (pllr & CKGR_PLLR_DIV)*
 245                                         (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
 246                         }
 247                         else if ((at91sam7_info->ext_freq != 0) &&
 248                                 ((pllr&CKGR_PLLR_DIV) != 0))
 249                         {
 250                                 at91sam7_info->mck_valid = 1;
 251                                 tmp = at91sam7_info->ext_freq / (pllr&CKGR_PLLR_DIV)*
 252                                         (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
 253                         }
 254                         break;
 255         }
 256
 257         /* Prescaler adjust */
 258         if ((((mckr & PMC_MCKR_PRES) >> 2) == 7) || (tmp == 0))
 259         {
 260                 at91sam7_info->mck_valid = 0;
 261                 at91sam7_info->mck_freq = 0;
 262         }
 263         else if (((mckr & PMC_MCKR_PRES) >> 2) != 0)
 264                 at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);
 265         else
 266                 at91sam7_info->mck_freq = tmp;
 267 }
 268
 269 /* Setup the timimg registers for nvbits or normal flash */
 270 static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode)
 271 {
 272         uint32_t fmr, fmcn = 0, fws = 0;
 273         struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
 274         struct target *target = bank->target;
 275
 276         if (mode && (mode != at91sam7_info->flashmode))
 277         {
 278                 /* Always round up (ceil) */
 279                 if (mode == FMR_TIMING_NVBITS)
 280                 {
 281                         if (at91sam7_info->cidr_arch == 0x60)
 282                         {
 283                                 /* AT91SAM7A3 uses master clocks in 100 ns */
 284                                 fmcn = (at91sam7_info->mck_freq/10000000ul) + 1;
 285                         }
 286                         else
 287                         {
 288                                 /* master clocks in 1uS for ARCH 0x7 types */
 289                                 fmcn = (at91sam7_info->mck_freq/1000000ul) + 1;
 290                         }
 291                 }
 292                 else if (mode == FMR_TIMING_FLASH)
 293                 {
 294                         /* main clocks in 1.5uS */
 295                         fmcn = (at91sam7_info->mck_freq/1000000ul)+
 296                                 (at91sam7_info->mck_freq/2000000ul) + 1;
 297                 }
 298
 299                 /* hard overclocking */
 300                 if (fmcn > 0xFF)
 301                         fmcn = 0xFF;
 302
 303                 /* Only allow fmcn = 0 if clock period is > 30 us = 33kHz. */
 304                 if (at91sam7_info->mck_freq <= 33333ul)
 305                         fmcn = 0;
 306                 /* Only allow fws = 0 if clock frequency is < 30 MHz. */
 307                 if (at91sam7_info->mck_freq > 30000000ul)
 308                         fws = 1;
 309
 310                 LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, (int)(fmcn));
 311                 fmr = fmcn << 16 | fws << 8;
 312                 target_write_u32(target, MC_FMR[bank->bank_number], fmr);
 313         }
 314
 315         at91sam7_info->flashmode = mode;
 316 }
 317
 318 static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout)
 319 {
 320         uint32_t status;
 321
 322         while ((!((status = at91sam7_get_flash_status(bank->target, bank->bank_number)) & waitbits)) && (timeout-- > 0))
 323         {
 324                 LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
 325                 alive_sleep(1);
 326         }
 327
 328         LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
 329
 330         if (status & 0x0C)
 331         {
 332                 LOG_ERROR("status register: 0x%" PRIx32 "", status);
 333                 if (status & 0x4)
 334                         LOG_ERROR("Lock Error Bit Detected, Operation Abort");
 335                 if (status & 0x8)
 336                         LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
 337                 if (status & 0x10)
 338                         LOG_ERROR("Security Bit Set, Operation Abort");
 339         }
 340
 341         return status;
 342 }
 343
 344 /* Send one command to the AT91SAM flash controller */
 345 static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t pagen)
 346 {
 347         uint32_t fcr;
 348         struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
 349         struct target *target = bank->target;
 350
 351         fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
 352         target_write_u32(target, MC_FCR[bank->bank_number], fcr);
 353         LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number + 1, pagen);
 354
 355         if ((at91sam7_info->cidr_arch == 0x60) && ((cmd == SLB) | (cmd == CLB)))
 356         {
 357                 /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
 358                 if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
 359                 {
 360                         return ERROR_FLASH_OPERATION_FAILED;
 361                 }
 362                 return ERROR_OK;
 363         }
 364
 365         if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
 366         {
 367                 return ERROR_FLASH_OPERATION_FAILED;
 368         }
 369
 370         return ERROR_OK;
 371 }
 372
 373 /* Read device id register, main clock frequency register and fill in driver info structure */
 374 static int at91sam7_read_part_info(struct flash_bank *bank)
 375 {
 376         struct flash_bank *t_bank = bank;
 377         struct at91sam7_flash_bank *at91sam7_info;
 378         struct target *target = t_bank->target;
 379
 380         uint16_t bnk, sec;
 381         uint16_t arch;
 382         uint32_t cidr;
 383         uint8_t banks_num = 0;
 384         uint16_t num_nvmbits = 0;
 385         uint16_t sectors_num = 0;
 386         uint16_t pages_per_sector = 0;
 387         uint16_t page_size = 0;
 388         uint32_t ext_freq;
 389         uint32_t bank_size;
 390         uint32_t base_address = 0;
 391         char *target_name_t = "Unknown";
 392
 393         at91sam7_info = t_bank->driver_priv;
 394
 395         if (at91sam7_info->cidr != 0)
 396         {
 397                 /* flash already configured, update clock and check for protected sectors */
 398                 struct flash_bank *fb = bank;
 399                 t_bank = fb;
 400
 401                 while (t_bank)
 402                 {
 403                         /* re-calculate master clock frequency */
 404                         at91sam7_read_clock_info(t_bank);
 405
 406                         /* no timming */
 407                         at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
 408
 409                         /* check protect state */
 410                         at91sam7_protect_check(t_bank);
 411
 412                         t_bank = fb->next;
 413                         fb = t_bank;
 414                 }
 415
 416                 return ERROR_OK;
 417         }
 418
 419         /* Read and parse chip identification register */
 420         target_read_u32(target, DBGU_CIDR, &cidr);
 421         if (cidr == 0)
 422         {
 423                 LOG_WARNING("Cannot identify target as an AT91SAM");
 424                 return ERROR_FLASH_OPERATION_FAILED;
 425         }
 426
 427         if (at91sam7_info->flash_autodetection == 0)
 428         {
 429                 /* banks and sectors are already created, based on data from input file */
 430                 struct flash_bank *fb = bank;
 431                 t_bank = fb;
 432                 while (t_bank)
 433                 {
 434                         at91sam7_info = t_bank->driver_priv;
 435
 436                         at91sam7_info->cidr = cidr;
 437                         at91sam7_info->cidr_ext = (cidr >> 31)&0x0001;
 438                         at91sam7_info->cidr_nvptyp = (cidr >> 28)&0x0007;
 439                         at91sam7_info->cidr_arch = (cidr >> 20)&0x00FF;
 440                         at91sam7_info->cidr_sramsiz = (cidr >> 16)&0x000F;
 441                         at91sam7_info->cidr_nvpsiz2 = (cidr >> 12)&0x000F;
 442                         at91sam7_info->cidr_nvpsiz = (cidr >> 8)&0x000F;
 443                         at91sam7_info->cidr_eproc = (cidr >> 5)&0x0007;
 444                         at91sam7_info->cidr_version = cidr&0x001F;
 445
 446                         /* calculate master clock frequency */
 447                         at91sam7_read_clock_info(t_bank);
 448
 449                         /* no timming */
 450                         at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
 451
 452                         /* check protect state */
 453                         at91sam7_protect_check(t_bank);
 454
 455                         t_bank = fb->next;
 456                         fb = t_bank;
 457                 }
 458
 459                 return ERROR_OK;
 460         }
 461
 462         arch = (cidr >> 20)&0x00FF;
 463
 464         /* check flash size */
 465         switch ((cidr >> 8)&0x000F)
 466         {
 467                 case FLASH_SIZE_8KB:
 468                         break;
 469
 470                 case FLASH_SIZE_16KB:
 471                         banks_num = 1;
 472                         sectors_num = 8;
 473                         pages_per_sector = 32;
 474                         page_size  = 64;
 475                         base_address = 0x00100000;
 476                         if (arch == 0x70)
 477                         {
 478                                 num_nvmbits = 2;
 479                                 target_name_t = "AT91SAM7S161/16";
 480                         }
 481                         break;
 482
 483                 case FLASH_SIZE_32KB:
 484                         banks_num = 1;
 485                         sectors_num = 8;
 486                         pages_per_sector = 32;
 487                         page_size  = 128;
 488                         base_address = 0x00100000;
 489                         if (arch == 0x70)
 490                         {
 491                                 num_nvmbits = 2;
 492                                 target_name_t = "AT91SAM7S321/32";
 493                         }
 494                         if (arch == 0x72)
 495                         {
 496                                 num_nvmbits = 3;
 497                                 target_name_t = "AT91SAM7SE32";
 498                         }
 499                         break;
 500
 501                 case FLASH_SIZE_64KB:
 502                         banks_num = 1;
 503                         sectors_num = 16;
 504                         pages_per_sector = 32;
 505                         page_size  = 128;
 506                         base_address = 0x00100000;
 507                         if (arch == 0x70)
 508                         {
 509                                 num_nvmbits = 2;
 510                                 target_name_t = "AT91SAM7S64";
 511                         }
 512                         break;
 513
 514                 case FLASH_SIZE_128KB:
 515                         banks_num = 1;
 516                         sectors_num = 8;
 517                         pages_per_sector = 64;
 518                         page_size  = 256;
 519                         base_address = 0x00100000;
 520                         if (arch == 0x70)
 521                         {
 522                                 num_nvmbits = 2;
 523                                 target_name_t = "AT91SAM7S128";
 524                         }
 525                         if (arch == 0x71)
 526                         {
 527                                 num_nvmbits = 3;
 528                                 target_name_t = "AT91SAM7XC128";
 529                         }
 530                         if (arch == 0x72)
 531                         {
 532                                 num_nvmbits = 3;
 533                                 target_name_t = "AT91SAM7SE128";
 534                         }
 535                         if (arch == 0x75)
 536                         {
 537                                 num_nvmbits = 3;
 538                                 target_name_t = "AT91SAM7X128";
 539                         }
 540                         break;
 541
 542                 case FLASH_SIZE_256KB:
 543                         banks_num = 1;
 544                         sectors_num = 16;
 545                         pages_per_sector = 64;
 546                         page_size  = 256;
 547                         base_address = 0x00100000;
 548                         if (arch == 0x60)
 549                         {
 550                                 num_nvmbits = 3;
 551                                 target_name_t = "AT91SAM7A3";
 552                         }
 553                         if (arch == 0x70)
 554                         {
 555                                 num_nvmbits = 2;
 556                                 target_name_t = "AT91SAM7S256";
 557                         }
 558                         if (arch == 0x71)
 559                         {
 560                                 num_nvmbits = 3;
 561                                 target_name_t = "AT91SAM7XC256";
 562                         }
 563                         if (arch == 0x72)
 564                         {
 565                                 num_nvmbits = 3;
 566                                 target_name_t = "AT91SAM7SE256";
 567                         }
 568                         if (arch == 0x75)
 569                         {
 570                                 num_nvmbits = 3;
 571                                 target_name_t = "AT91SAM7X256";
 572                         }
 573                         break;
 574
 575                 case FLASH_SIZE_512KB:
 576                         banks_num = 2;
 577                         sectors_num = 16;
 578                         pages_per_sector = 64;
 579                         page_size  = 256;
 580                         base_address = 0x00100000;
 581                         if (arch == 0x70)
 582                         {
 583                                 num_nvmbits = 2;
 584                                 target_name_t = "AT91SAM7S512";
 585                         }
 586                         if (arch == 0x71)
 587                         {
 588                                 num_nvmbits = 3;
 589                                 target_name_t = "AT91SAM7XC512";
 590                         }
 591                         if (arch == 0x72)
 592                         {
 593                                 num_nvmbits = 3;
 594                                 target_name_t = "AT91SAM7SE512";
 595                         }
 596                         if (arch == 0x75)
 597                         {
 598                                 num_nvmbits = 3;
 599                                 target_name_t = "AT91SAM7X512";
 600                         }
 601                         break;
 602
 603                 case FLASH_SIZE_1024KB:
 604                         break;
 605
 606                 case FLASH_SIZE_2048KB:
 607                         break;
 608         }
 609
 610         if (strcmp(target_name_t, "Unknown") == 0)
 611         {
 612                 LOG_ERROR("Target autodetection failed! Please specify target parameters in configuration file");
 613                 return ERROR_FLASH_OPERATION_FAILED;
 614         }
 615
 616         ext_freq = at91sam7_info->ext_freq;
 617
 618         /* calculate bank size  */
 619         bank_size = sectors_num * pages_per_sector * page_size;
 620
 621         for (bnk = 0; bnk < banks_num; bnk++)
 622         {
 623                 if (bnk > 0)
 624                 {
 625                         if (!t_bank->next) {
 626                                 /* create a new flash bank element */
 627                                 struct flash_bank *fb = malloc(sizeof(struct flash_bank));
 628                                 fb->target = target;
 629                                 fb->driver = bank->driver;
 630                                 fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
 631                                 fb->name = "sam7_probed";
 632                                 fb->next = NULL;
 633
 634                                 /* link created bank in 'flash_banks' list */
 635                                 t_bank->next = fb;
 636                         }
 637                         t_bank = t_bank->next;
 638                 }
 639
 640                 t_bank->bank_number = bnk;
 641                 t_bank->base = base_address + bnk * bank_size;
 642                 t_bank->size = bank_size;
 643                 t_bank->chip_width = 0;
 644                 t_bank->bus_width = 4;
 645                 t_bank->num_sectors = sectors_num;
 646
 647                 /* allocate sectors */
 648                 t_bank->sectors = malloc(sectors_num * sizeof(struct flash_sector));
 649                 for (sec = 0; sec < sectors_num; sec++)
 650                 {
 651                         t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
 652                         t_bank->sectors[sec].size = pages_per_sector * page_size;
 653                         t_bank->sectors[sec].is_erased = -1;
 654                         t_bank->sectors[sec].is_protected = -1;
 655                 }
 656
 657                 at91sam7_info = t_bank->driver_priv;
 658
 659                 at91sam7_info->cidr = cidr;
 660                 at91sam7_info->cidr_ext = (cidr >> 31)&0x0001;
 661                 at91sam7_info->cidr_nvptyp = (cidr >> 28)&0x0007;
 662                 at91sam7_info->cidr_arch = (cidr >> 20)&0x00FF;
 663                 at91sam7_info->cidr_sramsiz = (cidr >> 16)&0x000F;
 664                 at91sam7_info->cidr_nvpsiz2 = (cidr >> 12)&0x000F;
 665                 at91sam7_info->cidr_nvpsiz = (cidr >> 8)&0x000F;
 666                 at91sam7_info->cidr_eproc = (cidr >> 5)&0x0007;
 667                 at91sam7_info->cidr_version = cidr&0x001F;
 668
 669                 at91sam7_info->target_name  = target_name_t;
 670                 at91sam7_info->flashmode = 0;
 671                 at91sam7_info->ext_freq = ext_freq;
 672                 at91sam7_info->num_nvmbits = num_nvmbits;
 673                 at91sam7_info->num_nvmbits_on = 0;
 674                 at91sam7_info->pagesize = page_size;
 675                 at91sam7_info->pages_per_sector = pages_per_sector;
 676
 677                 /* calculate master clock frequency */
 678                 at91sam7_read_clock_info(t_bank);
 679
 680                 /* no timming */
 681                 at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
 682
 683                 /* check protect state */
 684                 at91sam7_protect_check(t_bank);
 685         }
 686
 687         LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch);
 688
 689         return ERROR_OK;
 690 }
 691
 692 static int at91sam7_erase_check(struct flash_bank *bank)
 693 {
 694         struct target *target = bank->target;
 695         uint16_t retval;
 696         uint32_t blank;
 697         uint16_t fast_check;
 698         uint8_t *buffer;
 699         uint16_t nSector;
 700         uint16_t nByte;
 701
 702         if (bank->target->state != TARGET_HALTED)
 703         {
 704                 LOG_ERROR("Target not halted");
 705                 return ERROR_TARGET_NOT_HALTED;
 706         }
 707
 708         /* Configure the flash controller timing */
 709         at91sam7_read_clock_info(bank);
 710         at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
 711
 712         fast_check = 1;
 713         for (nSector = 0; nSector < bank->num_sectors; nSector++)
 714         {
 715                 retval = target_blank_check_memory(target, bank->base + bank->sectors[nSector].offset,
 716                         bank->sectors[nSector].size, &blank);
 717                 if (retval != ERROR_OK)
 718                 {
 719                         fast_check = 0;
 720                         break;
 721                 }
 722                 if (blank == 0xFF)
 723                         bank->sectors[nSector].is_erased = 1;
 724                 else
 725                         bank->sectors[nSector].is_erased = 0;
 726         }
 727
 728         if (fast_check)
 729         {
 730                 return ERROR_OK;
 731         }
 732
 733         LOG_USER("Running slow fallback erase check - add working memory");
 734
 735         buffer = malloc(bank->sectors[0].size);
 736         for (nSector = 0; nSector < bank->num_sectors; nSector++)
 737         {
 738                 bank->sectors[nSector].is_erased = 1;
 739                 retval = target_read_memory(target, bank->base + bank->sectors[nSector].offset, 4,
 740                         bank->sectors[nSector].size/4, buffer);
 741                 if (retval != ERROR_OK)
 742                         return retval;
 743
 744                 for (nByte = 0; nByte < bank->sectors[nSector].size; nByte++)
 745                 {
 746                         if (buffer[nByte] != 0xFF)
 747                         {
 748                                 bank->sectors[nSector].is_erased = 0;
 749                                 break;
 750                         }
 751                 }
 752         }
 753         free(buffer);
 754
 755         return ERROR_OK;
 756 }
 757
 758 static int at91sam7_protect_check(struct flash_bank *bank)
 759 {
 760         uint8_t lock_pos, gpnvm_pos;
 761         uint32_t status;
 762
 763         struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
 764
 765         if (at91sam7_info->cidr == 0)
 766         {
 767                 return ERROR_FLASH_BANK_NOT_PROBED;
 768         }
 769         if (bank->target->state != TARGET_HALTED)
 770         {
 771                 LOG_ERROR("Target not halted");
 772                 return ERROR_TARGET_NOT_HALTED;
 773         }
 774
 775         status = at91sam7_get_flash_status(bank->target, bank->bank_number);
 776         at91sam7_info->lockbits = (status >> 16);
 777
 778         at91sam7_info->num_lockbits_on = 0;
 779         for (lock_pos = 0; lock_pos < bank->num_sectors; lock_pos++)
 780         {
 781                 if (((status >> (16 + lock_pos))&(0x0001)) == 1)
 782                 {
 783                         at91sam7_info->num_lockbits_on++;
 784                         bank->sectors[lock_pos].is_protected = 1;
 785                 }
 786                 else
 787                         bank->sectors[lock_pos].is_protected = 0;
 788         }
 789
 790         /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
 791         status = at91sam7_get_flash_status(bank->target, 0);
 792
 793         at91sam7_info->securitybit = (status >> 4)&0x01;
 794         at91sam7_info->nvmbits = (status >> 8)&0xFF;
 795
 796         at91sam7_info->num_nvmbits_on = 0;
 797         for (gpnvm_pos = 0; gpnvm_pos < at91sam7_info->num_nvmbits; gpnvm_pos++)
 798         {
 799                 if (((status >> (8 + gpnvm_pos))&(0x01)) == 1)
 800                 {
 801                         at91sam7_info->num_nvmbits_on++;
 802                 }
 803         }
 804
 805         return ERROR_OK;
 806 }
 807
 808 FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
 809 {
 810         struct flash_bank *t_bank = bank;
 811         struct at91sam7_flash_bank *at91sam7_info;
 812         struct target *target = t_bank->target;
 813
 814         uint32_t base_address;
 815         uint32_t bank_size;
 816         uint32_t ext_freq = 0;
 817
 818         int chip_width;
 819         int bus_width;
 820         int banks_num;
 821         int num_sectors;
 822
 823         uint16_t pages_per_sector;
 824         uint16_t page_size;
 825         uint16_t num_nvmbits;
 826
 827         char *target_name_t;
 828
 829         int bnk, sec;
 830
 831         at91sam7_info = malloc(sizeof(struct at91sam7_flash_bank));
 832         t_bank->driver_priv = at91sam7_info;
 833
 834         /* part wasn't probed for info yet */
 835         at91sam7_info->cidr = 0;
 836         at91sam7_info->flashmode = 0;
 837         at91sam7_info->ext_freq = 0;
 838         at91sam7_info->flash_autodetection = 0;
 839
 840         if (CMD_ARGC < 13)
 841         {
 842                 at91sam7_info->flash_autodetection = 1;
 843                 return ERROR_OK;
 844         }
 845
 846         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], base_address);
 847
 848         COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], chip_width);
 849         COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], bus_width);
 850
 851         COMMAND_PARSE_NUMBER(int, CMD_ARGV[8], banks_num);
 852         COMMAND_PARSE_NUMBER(int, CMD_ARGV[9], num_sectors);
 853         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[10], pages_per_sector);
 854         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[11], page_size);
 855         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[12], num_nvmbits);
 856
 857         if (CMD_ARGC == 14) {
 858                 unsigned long freq;
 859                 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[13], freq);
 860                 ext_freq = freq * 1000;
 861                 at91sam7_info->ext_freq = ext_freq;
 862         }
 863
 864         if ((bus_width == 0) || (banks_num == 0) || (num_sectors == 0) ||
 865                 (pages_per_sector == 0) || (page_size == 0) || (num_nvmbits == 0))
 866         {
 867                 at91sam7_info->flash_autodetection = 1;
 868                 return ERROR_OK;
 869         }
 870
 871         target_name_t = calloc(strlen(CMD_ARGV[7]) + 1, sizeof(char));
 872         strcpy(target_name_t, CMD_ARGV[7]);
 873
 874         /* calculate bank size  */
 875         bank_size = num_sectors * pages_per_sector * page_size;
 876
 877         for (bnk = 0; bnk < banks_num; bnk++)
 878         {
 879                 if (bnk > 0)
 880                 {
 881                         if (!t_bank->next) {
 882                                 /* create a new bank element */
 883                                 struct flash_bank *fb = malloc(sizeof(struct flash_bank));
 884                                 fb->target = target;
 885                                 fb->driver = bank->driver;
 886                                 fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
 887                                 fb->name = "sam7_probed";
 888                                 fb->next = NULL;
 889
 890                                 /* link created bank in 'flash_banks' list */
 891                                 t_bank->next = fb;
 892                         }
 893                         t_bank = t_bank->next;
 894                 }
 895
 896                 t_bank->bank_number = bnk;
 897                 t_bank->base = base_address + bnk * bank_size;
 898                 t_bank->size = bank_size;
 899                 t_bank->chip_width = chip_width;
 900                 t_bank->bus_width = bus_width;
 901                 t_bank->num_sectors = num_sectors;
 902
 903                 /* allocate sectors */
 904                 t_bank->sectors = malloc(num_sectors * sizeof(struct flash_sector));
 905                 for (sec = 0; sec < num_sectors; sec++)
 906                 {
 907                         t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
 908                         t_bank->sectors[sec].size = pages_per_sector * page_size;
 909                         t_bank->sectors[sec].is_erased = -1;
 910                         t_bank->sectors[sec].is_protected = -1;
 911                 }
 912
 913                 at91sam7_info = t_bank->driver_priv;
 914
 915                 at91sam7_info->target_name  = target_name_t;
 916                 at91sam7_info->flashmode = 0;
 917                 at91sam7_info->ext_freq  = ext_freq;
 918                 at91sam7_info->num_nvmbits = num_nvmbits;
 919                 at91sam7_info->num_nvmbits_on = 0;
 920                 at91sam7_info->pagesize = page_size;
 921                 at91sam7_info->pages_per_sector = pages_per_sector;
 922         }
 923
 924         return ERROR_OK;
 925 }
 926
 927 static int at91sam7_erase(struct flash_bank *bank, int first, int last)
 928 {
 929         struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
 930         int sec;
 931         uint32_t nbytes, pos;
 932         uint8_t *buffer;
 933         uint8_t erase_all;
 934
 935         if (at91sam7_info->cidr == 0)
 936         {
 937                 return ERROR_FLASH_BANK_NOT_PROBED;
 938         }
 939
 940         if (bank->target->state != TARGET_HALTED)
 941         {
 942                 LOG_ERROR("Target not halted");
 943                 return ERROR_TARGET_NOT_HALTED;
 944         }
 945
 946         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 947         {
 948                 return ERROR_FLASH_SECTOR_INVALID;
 949         }
 950
 951         erase_all = 0;
 952         if ((first == 0) && (last == (bank->num_sectors-1)))
 953         {
 954                 erase_all = 1;
 955         }
 956
 957         /* Configure the flash controller timing */
 958         at91sam7_read_clock_info(bank);
 959         at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
 960
 961         if (erase_all)
 962         {
 963                 if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
 964                 {
 965                         return ERROR_FLASH_OPERATION_FAILED;
 966                 }
 967         }
 968         else
 969         {
 970                 /* allocate and clean buffer  */
 971                 nbytes = (last - first + 1) * bank->sectors[first].size;
 972                 buffer = malloc(nbytes * sizeof(uint8_t));
 973                 for (pos = 0; pos < nbytes; pos++)
 974                 {
 975                         buffer[pos] = 0xFF;
 976                 }
 977
 978                 if (at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK)
 979                 {
 980                         return ERROR_FLASH_OPERATION_FAILED;
 981                 }
 982
 983                 free(buffer);
 984         }
 985
 986         /* mark erased sectors */
 987         for (sec = first; sec <= last; sec++)
 988         {
 989                 bank->sectors[sec].is_erased = 1;
 990         }
 991
 992         return ERROR_OK;
 993 }
 994
 995 static int at91sam7_protect(struct flash_bank *bank, int set, int first, int last)
 996 {
 997         uint32_t cmd;
 998         int sector;
 999         uint32_t pagen;
1000
1001         struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
1002
1003         if (at91sam7_info->cidr == 0)
1004         {
1005                 return ERROR_FLASH_BANK_NOT_PROBED;
1006         }
1007
1008         if (bank->target->state != TARGET_HALTED)
1009         {
1010                 LOG_ERROR("Target not halted");
1011                 return ERROR_TARGET_NOT_HALTED;
1012         }
1013
1014         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
1015         {
1016                 return ERROR_FLASH_SECTOR_INVALID;
1017         }
1018
1019         /* Configure the flash controller timing */
1020         at91sam7_read_clock_info(bank);
1021         at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
1022
1023         for (sector = first; sector <= last; sector++)
1024         {
1025                 if (set)
1026                         cmd = SLB;
1027                 else
1028                         cmd = CLB;
1029
1030                 /* if we lock a page from one sector then entire sector will be locked, also,
1031                  * if we unlock a page from a locked sector, entire sector will be unlocked   */
1032                 pagen = sector * at91sam7_info->pages_per_sector;
1033
1034                 if (at91sam7_flash_command(bank, cmd, pagen) != ERROR_OK)
1035                 {
1036                         return ERROR_FLASH_OPERATION_FAILED;
1037                 }
1038         }
1039
1040         at91sam7_protect_check(bank);
1041
1042         return ERROR_OK;
1043 }
1044
1045 static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1046 {
1047         int retval;
1048         struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
1049         struct target *target = bank->target;
1050         uint32_t dst_min_alignment, wcount, bytes_remaining = count;
1051         uint32_t first_page, last_page, pagen, buffer_pos;
1052
1053         if (at91sam7_info->cidr == 0)
1054         {
1055                 return ERROR_FLASH_BANK_NOT_PROBED;
1056         }
1057
1058         if (bank->target->state != TARGET_HALTED)
1059         {
1060                 LOG_ERROR("Target not halted");
1061                 return ERROR_TARGET_NOT_HALTED;
1062         }
1063
1064         if (offset + count > bank->size)
1065                 return ERROR_FLASH_DST_OUT_OF_BANK;
1066
1067         dst_min_alignment = at91sam7_info->pagesize;
1068
1069         if (offset % dst_min_alignment)
1070         {
1071                 LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "", offset, dst_min_alignment);
1072                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1073         }
1074
1075         if (at91sam7_info->cidr_arch == 0)
1076                 return ERROR_FLASH_BANK_NOT_PROBED;
1077
1078         first_page = offset/dst_min_alignment;
1079         last_page = DIV_ROUND_UP(offset + count, dst_min_alignment);
1080
1081         LOG_DEBUG("first_page: %i, last_page: %i, count %i", (int)first_page, (int)last_page, (int)count);
1082
1083         /* Configure the flash controller timing */
1084         at91sam7_read_clock_info(bank);
1085         at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
1086
1087         for (pagen = first_page; pagen < last_page; pagen++)
1088         {
1089                 if (bytes_remaining < dst_min_alignment)
1090                         count = bytes_remaining;
1091                 else
1092                         count = dst_min_alignment;
1093                 bytes_remaining -= count;
1094
1095                 /* Write one block to the PageWriteBuffer */
1096                 buffer_pos = (pagen-first_page)*dst_min_alignment;
1097                 wcount = DIV_ROUND_UP(count,4);
1098                 if ((retval = target_write_memory(target, bank->base + pagen*dst_min_alignment, 4, wcount, buffer + buffer_pos)) != ERROR_OK)
1099                 {
1100                         return retval;
1101                 }
1102
1103                 /* Send Write Page command to Flash Controller */
1104                 if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
1105                 {
1106                         return ERROR_FLASH_OPERATION_FAILED;
1107                 }
1108                 LOG_DEBUG("Write flash bank:%i page number:%" PRIi32 "", bank->bank_number, pagen);
1109         }
1110
1111         return ERROR_OK;
1112 }
1113
1114 static int at91sam7_probe(struct flash_bank *bank)
1115 {
1116         /* we can't probe on an at91sam7
1117          * if this is an at91sam7, it has the configured flash */
1118         int retval;
1119
1120         if (bank->target->state != TARGET_HALTED)
1121         {
1122                 LOG_ERROR("Target not halted");
1123                 return ERROR_TARGET_NOT_HALTED;
1124         }
1125
1126         retval = at91sam7_read_part_info(bank);
1127         if (retval != ERROR_OK)
1128                 return retval;
1129
1130         return ERROR_OK;
1131 }
1132
1133 static int get_at91sam7_info(struct flash_bank *bank, char *buf, int buf_size)
1134 {
1135         int printed;
1136         struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
1137
1138         if (at91sam7_info->cidr == 0)
1139         {
1140                 return ERROR_FLASH_BANK_NOT_PROBED;
1141         }
1142
1143         printed = snprintf(buf, buf_size,
1144                 "\n at91sam7 driver information: Chip is %s\n",
1145                 at91sam7_info->target_name);
1146
1147         buf += printed;
1148         buf_size -= printed;
1149
1150         printed = snprintf(buf,
1151                            buf_size,
1152                            " Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8" PRIx32 "\n",
1153                            at91sam7_info->cidr,
1154                            at91sam7_info->cidr_arch,
1155                            EPROC[at91sam7_info->cidr_eproc],
1156                            at91sam7_info->cidr_version,
1157                            bank->size);
1158
1159         buf += printed;
1160         buf_size -= printed;
1161
1162         printed = snprintf(buf, buf_size,
1163                 " Master clock (estimated): %u KHz | External clock: %u KHz\n",
1164                 (unsigned)(at91sam7_info->mck_freq / 1000), (unsigned)(at91sam7_info->ext_freq / 1000));
1165
1166         buf += printed;
1167         buf_size -= printed;
1168
1169         printed = snprintf(buf, buf_size,
1170                 " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i \n",
1171                 at91sam7_info->pagesize, bank->num_sectors, at91sam7_info->num_lockbits_on,
1172                 at91sam7_info->lockbits, at91sam7_info->pages_per_sector*at91sam7_info->num_lockbits_on);
1173
1174         buf += printed;
1175         buf_size -= printed;
1176
1177         snprintf(buf, buf_size,
1178                 " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
1179                 at91sam7_info->securitybit, at91sam7_info->num_nvmbits,
1180                 at91sam7_info->num_nvmbits_on, at91sam7_info->nvmbits);
1181
1182         return ERROR_OK;
1183 }
1184
1185 /*
1186 * On AT91SAM7S: When the gpnvm bits are set with
1187 * > at91sam7 gpnvm bitnr set
1188 * the changes are not visible in the flash controller status register MC_FSR
1189 * until the processor has been reset.
1190 * On the Olimex board this requires a power cycle.
1191 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
1192 *   The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
1193 *   Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
1194 */
1195 COMMAND_HANDLER(at91sam7_handle_gpnvm_command)
1196 {
1197         struct flash_bank *bank;
1198         int bit;
1199         uint8_t  flashcmd;
1200         uint32_t status;
1201         struct at91sam7_flash_bank *at91sam7_info;
1202         int retval;
1203
1204         if (CMD_ARGC != 2)
1205         {
1206                 command_print(CMD_CTX, "at91sam7 gpnvm <bit> <set | clear>");
1207                 return ERROR_OK;
1208         }
1209
1210         bank = get_flash_bank_by_num_noprobe(0);
1211         if (bank ==  NULL)
1212         {
1213                 return ERROR_FLASH_BANK_INVALID;
1214         }
1215         if (strcmp(bank->driver->name, "at91sam7"))
1216         {
1217                 command_print(CMD_CTX, "not an at91sam7 flash bank '%s'", CMD_ARGV[0]);
1218                 return ERROR_FLASH_BANK_INVALID;
1219         }
1220         if (bank->target->state != TARGET_HALTED)
1221         {
1222                 LOG_ERROR("target has to be halted to perform flash operation");
1223                 return ERROR_TARGET_NOT_HALTED;
1224         }
1225
1226         if (strcmp(CMD_ARGV[1], "set") == 0)
1227         {
1228                 flashcmd = SGPB;
1229         }
1230         else if (strcmp(CMD_ARGV[1], "clear") == 0)
1231         {
1232                 flashcmd = CGPB;
1233         }
1234         else
1235         {
1236                 return ERROR_COMMAND_SYNTAX_ERROR;
1237         }
1238
1239         at91sam7_info = bank->driver_priv;
1240         if (at91sam7_info->cidr == 0)
1241         {
1242                 retval = at91sam7_read_part_info(bank);
1243                 if (retval != ERROR_OK)
1244                 {
1245                         return retval;
1246                 }
1247         }
1248
1249         COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], bit);
1250         if ((bit < 0) || (bit >= at91sam7_info->num_nvmbits))
1251         {
1252                 command_print(CMD_CTX, "gpnvm bit '#%s' is out of bounds for target %s", CMD_ARGV[0], at91sam7_info->target_name);
1253                 return ERROR_OK;
1254         }
1255
1256         /* Configure the flash controller timing */
1257         at91sam7_read_clock_info(bank);
1258         at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
1259
1260         if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
1261         {
1262                 return ERROR_FLASH_OPERATION_FAILED;
1263         }
1264
1265         /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
1266         status = at91sam7_get_flash_status(bank->target, 0);
1267         LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32, flashcmd, bit, status);
1268
1269         /* check protect state */
1270         at91sam7_protect_check(bank);
1271
1272         return ERROR_OK;
1273 }
1274
1275 static const struct command_registration at91sam7_exec_command_handlers[] = {
1276         {
1277                 .name = "gpnvm",
1278                 .handler = at91sam7_handle_gpnvm_command,
1279                 .mode = COMMAND_EXEC,
1280                 .help = "set or clear one General Purpose Non-Volatile Memory "
1281                         "(gpnvm) bit",
1282                 .usage = "bitnum ('set'|'clear')",
1283         },
1284         COMMAND_REGISTRATION_DONE
1285 };
1286 static const struct command_registration at91sam7_command_handlers[] = {
1287         {
1288                 .name = "at91sam7",
1289                 .mode = COMMAND_ANY,
1290                 .help = "at91sam7 flash command group",
1291                 .chain = at91sam7_exec_command_handlers,
1292         },
1293         COMMAND_REGISTRATION_DONE
1294 };
1295
1296 struct flash_driver at91sam7_flash = {
1297         .name = "at91sam7",
1298         .commands = at91sam7_command_handlers,
1299         .flash_bank_command = at91sam7_flash_bank_command,
1300         .erase = at91sam7_erase,
1301         .protect = at91sam7_protect,
1302         .write = at91sam7_write,
1303         .read = default_flash_read,
1304         .probe = at91sam7_probe,
1305         .auto_probe = at91sam7_probe,
1306         .erase_check = at91sam7_erase_check,
1307         .protect_check = at91sam7_protect_check,
1308         .info = get_at91sam7_info,
1309 };