1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
19 * GNU General public License for more details. *
21 * You should have received a copy of the GNU General public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ****************************************************************************/
27 /* Some of the the lower level code was based on code supplied by
28 * ATMEL under this copyright. */
30 /* BEGIN ATMEL COPYRIGHT */
31 /* ----------------------------------------------------------------------------
32 * ATMEL Microcontroller Software Support
33 * ----------------------------------------------------------------------------
34 * Copyright (c) 2009, Atmel Corporation
36 * All rights reserved.
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions are met:
41 * - Redistributions of source code must retain the above copyright notice,
42 * this list of conditions and the disclaimer below.
44 * Atmel's name may not be used to endorse or promote products derived from
45 * this software without specific prior written permission.
47 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
49 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
50 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
53 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
54 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
55 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
56 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * ----------------------------------------------------------------------------
59 /* END ATMEL COPYRIGHT */
66 #include <helper/time_support.h>
68 #define REG_NAME_WIDTH (12)
70 /* at91sam4s series (has always one flash bank)*/
71 #define FLASH_BANK_BASE_S 0x00400000
73 /* at91sam4sd series (two one flash banks), first bank address */
74 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
75 /* at91sam4sd16x, second bank address */
76 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
77 /* at91sam4sd32x, second bank address */
78 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
80 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
81 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
82 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
83 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
84 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
85 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
86 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
87 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
88 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
89 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
90 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
91 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
92 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
93 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
94 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
95 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
96 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
98 #define offset_EFC_FMR 0
99 #define offset_EFC_FCR 4
100 #define offset_EFC_FSR 8
101 #define offset_EFC_FRR 12
103 extern struct flash_driver at91sam4_flash;
105 static float _tomhz(uint32_t freq_hz)
109 f = ((float)(freq_hz)) / 1000000.0;
113 /* How the chip is configured. */
115 uint32_t unique_id[4];
119 uint32_t mainosc_freq;
129 #define SAM4_CHIPID_CIDR (0x400E0740)
130 uint32_t CHIPID_CIDR;
131 #define SAM4_CHIPID_EXID (0x400E0744)
132 uint32_t CHIPID_EXID;
134 #define SAM4_PMC_BASE (0x400E0400)
135 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
137 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
139 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
141 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
143 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
145 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
147 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
149 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
151 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
153 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
155 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
157 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
159 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
161 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
165 struct sam4_bank_private {
167 /* DANGER: THERE ARE DRAGONS HERE.. */
168 /* NOTE: If you add more 'ghost' pointers */
169 /* be aware that you must *manually* update */
170 /* these pointers in the function sam4_GetDetails() */
171 /* See the comment "Here there be dragons" */
173 /* so we can find the chip we belong to */
174 struct sam4_chip *pChip;
175 /* so we can find the original bank pointer */
176 struct flash_bank *pBank;
177 unsigned bank_number;
178 uint32_t controller_address;
179 uint32_t base_address;
180 uint32_t flash_wait_states;
184 unsigned sector_size;
188 struct sam4_chip_details {
189 /* THERE ARE DRAGONS HERE.. */
190 /* note: If you add pointers here */
191 /* be careful about them as they */
192 /* may need to be updated inside */
193 /* the function: "sam4_GetDetails() */
194 /* which copy/overwrites the */
195 /* 'runtime' copy of this structure */
196 uint32_t chipid_cidr;
200 #define SAM4_N_NVM_BITS 3
201 unsigned gpnvm[SAM4_N_NVM_BITS];
202 unsigned total_flash_size;
203 unsigned total_sram_size;
205 #define SAM4_MAX_FLASH_BANKS 2
206 /* these are "initialized" from the global const data */
207 struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
211 struct sam4_chip *next;
214 /* this is "initialized" from the global const structure */
215 struct sam4_chip_details details;
216 struct target *target;
221 struct sam4_reg_list {
222 uint32_t address; size_t struct_offset; const char *name;
223 void (*explain_func)(struct sam4_chip *pInfo);
226 static struct sam4_chip *all_sam4_chips;
228 static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
231 static struct sam4_chip *p;
233 t = get_current_target(cmd_ctx);
235 command_print(cmd_ctx, "No current target?");
241 /* this should not happen */
242 /* the command is not registered until the chip is created? */
243 command_print(cmd_ctx, "No SAM4 chips exist?");
252 command_print(cmd_ctx, "Cannot find SAM4 chip?");
256 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
257 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
258 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
259 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
261 /* these are used to *initialize* the "pChip->details" structure. */
262 static const struct sam4_chip_details all_sam4_details[] = {
263 /* Start at91sam4s* series */
264 /*atsam4s16c - LQFP100/BGA100*/
266 .chipid_cidr = 0x28AC0CE0,
267 .name = "at91sam4s16c",
268 .total_flash_size = 1024 * 1024,
269 .total_sram_size = 128 * 1024,
279 .base_address = FLASH_BANK_BASE_S,
280 .controller_address = 0x400e0a00,
281 .flash_wait_states = 6, /* workaround silicon bug */
283 .size_bytes = 1024 * 1024,
297 /*atsam4s16b - LQFP64/QFN64*/
299 .chipid_cidr = 0x289C0CE0,
300 .name = "at91sam4s16b",
301 .total_flash_size = 1024 * 1024,
302 .total_sram_size = 128 * 1024,
312 .base_address = FLASH_BANK_BASE_S,
313 .controller_address = 0x400e0a00,
314 .flash_wait_states = 6, /* workaround silicon bug */
316 .size_bytes = 1024 * 1024,
330 /*atsam4s16a - LQFP48/QFN48*/
332 .chipid_cidr = 0x288C0CE0,
333 .name = "at91sam4s16a",
334 .total_flash_size = 1024 * 1024,
335 .total_sram_size = 128 * 1024,
345 .base_address = FLASH_BANK_BASE_S,
346 .controller_address = 0x400e0a00,
347 .flash_wait_states = 6, /* workaround silicon bug */
349 .size_bytes = 1024 * 1024,
363 /*atsam4s8c - LQFP100/BGA100*/
365 .chipid_cidr = 0x28AC0AE0,
366 .name = "at91sam4s8c",
367 .total_flash_size = 512 * 1024,
368 .total_sram_size = 128 * 1024,
378 .base_address = FLASH_BANK_BASE_S,
379 .controller_address = 0x400e0a00,
380 .flash_wait_states = 6, /* workaround silicon bug */
382 .size_bytes = 512 * 1024,
396 /*atsam4s8b - LQFP64/BGA64*/
398 .chipid_cidr = 0x289C0AE0,
399 .name = "at91sam4s8b",
400 .total_flash_size = 512 * 1024,
401 .total_sram_size = 128 * 1024,
411 .base_address = FLASH_BANK_BASE_S,
412 .controller_address = 0x400e0a00,
413 .flash_wait_states = 6, /* workaround silicon bug */
415 .size_bytes = 512 * 1024,
429 /*atsam4s8a - LQFP48/BGA48*/
431 .chipid_cidr = 0x288C0AE0,
432 .name = "at91sam4s8a",
433 .total_flash_size = 512 * 1024,
434 .total_sram_size = 128 * 1024,
444 .base_address = FLASH_BANK_BASE_S,
445 .controller_address = 0x400e0a00,
446 .flash_wait_states = 6, /* workaround silicon bug */
448 .size_bytes = 512 * 1024,
465 .chipid_cidr = 0x29a70ee0,
466 .name = "at91sam4sd32c",
467 .total_flash_size = 2048 * 1024,
468 .total_sram_size = 160 * 1024,
479 .base_address = FLASH_BANK0_BASE_SD,
480 .controller_address = 0x400e0a00,
481 .flash_wait_states = 6, /* workaround silicon bug */
483 .size_bytes = 1024 * 1024,
495 .base_address = FLASH_BANK1_BASE_2048K_SD,
496 .controller_address = 0x400e0c00,
497 .flash_wait_states = 6, /* workaround silicon bug */
499 .size_bytes = 1024 * 1024,
515 /***********************************************************************
516 **********************************************************************
517 **********************************************************************
518 **********************************************************************
519 **********************************************************************
520 **********************************************************************/
521 /* *ATMEL* style code - from the SAM4 driver code */
524 * Get the current status of the EEFC and
525 * the value of some status bits (LOCKE, PROGE).
526 * @param pPrivate - info about the bank
527 * @param v - result goes here
529 static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
532 r = target_read_u32(pPrivate->pChip->target,
533 pPrivate->controller_address + offset_EFC_FSR,
535 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
537 ((unsigned int)((*v >> 2) & 1)),
538 ((unsigned int)((*v >> 1) & 1)),
539 ((unsigned int)((*v >> 0) & 1)));
545 * Get the result of the last executed command.
546 * @param pPrivate - info about the bank
547 * @param v - result goes here
549 static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
553 r = target_read_u32(pPrivate->pChip->target,
554 pPrivate->controller_address + offset_EFC_FRR,
558 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
562 static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
563 unsigned command, unsigned argument)
572 /* Check command & argument */
575 case AT91C_EFC_FCMD_WP:
576 case AT91C_EFC_FCMD_WPL:
577 case AT91C_EFC_FCMD_EWP:
578 case AT91C_EFC_FCMD_EWPL:
579 /* case AT91C_EFC_FCMD_EPL: */
580 case AT91C_EFC_FCMD_EPA:
581 case AT91C_EFC_FCMD_SLB:
582 case AT91C_EFC_FCMD_CLB:
583 n = (pPrivate->size_bytes / pPrivate->page_size);
585 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
588 case AT91C_EFC_FCMD_SFB:
589 case AT91C_EFC_FCMD_CFB:
590 if (argument >= pPrivate->pChip->details.n_gpnvms) {
591 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
592 pPrivate->pChip->details.n_gpnvms);
596 case AT91C_EFC_FCMD_GETD:
597 case AT91C_EFC_FCMD_EA:
598 case AT91C_EFC_FCMD_GLB:
599 case AT91C_EFC_FCMD_GFB:
600 case AT91C_EFC_FCMD_STUI:
601 case AT91C_EFC_FCMD_SPUI:
603 LOG_ERROR("Argument is meaningless for cmd: %d", command);
606 LOG_ERROR("Unknown command %d", command);
610 if (command == AT91C_EFC_FCMD_SPUI) {
611 /* this is a very special situation. */
612 /* Situation (1) - error/retry - see below */
613 /* And we are being called recursively */
614 /* Situation (2) - normal, finished reading unique id */
616 /* it should be "ready" */
617 EFC_GetStatus(pPrivate, &v);
619 /* then it is ready */
623 /* we have done this before */
624 /* the controller is not responding. */
625 LOG_ERROR("flash controller(%d) is not ready! Error",
626 pPrivate->bank_number);
630 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
631 pPrivate->bank_number);
632 /* we do that by issuing the *STOP* command */
633 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
634 /* above is recursive, and further recursion is blocked by */
635 /* if (command == AT91C_EFC_FCMD_SPUI) above */
641 v = (0x5A << 24) | (argument << 8) | command;
642 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
643 r = target_write_u32(pPrivate->pBank->target,
644 pPrivate->controller_address + offset_EFC_FCR, v);
646 LOG_DEBUG("Error Write failed");
651 * Performs the given command and wait until its completion (or an error).
652 * @param pPrivate - info about the bank
653 * @param command - Command to perform.
654 * @param argument - Optional command argument.
655 * @param status - put command status bits here
657 static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
665 long long ms_now, ms_end;
671 r = EFC_StartCommand(pPrivate, command, argument);
675 ms_end = 10000 + timeval_ms();
678 r = EFC_GetStatus(pPrivate, &v);
681 ms_now = timeval_ms();
682 if (ms_now > ms_end) {
684 LOG_ERROR("Command timeout");
687 } while ((v & 1) == 0);
697 * Read the unique ID.
698 * @param pPrivate - info about the bank
699 * The unique ID is stored in the 'pPrivate' structure.
701 static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
707 pPrivate->pChip->cfg.unique_id[0] = 0;
708 pPrivate->pChip->cfg.unique_id[1] = 0;
709 pPrivate->pChip->cfg.unique_id[2] = 0;
710 pPrivate->pChip->cfg.unique_id[3] = 0;
713 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
717 for (x = 0; x < 4; x++) {
718 r = target_read_u32(pPrivate->pChip->target,
719 pPrivate->pBank->base + (x * 4),
723 pPrivate->pChip->cfg.unique_id[x] = v;
726 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
727 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
729 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
730 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
731 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
732 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
738 * Erases the entire flash.
739 * @param pPrivate - the info about the bank.
741 static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
744 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
748 * Erases the entire flash.
749 * @param pPrivate - the info about the bank.
751 static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
776 /* AT91C_EFC_FCMD_EPA
777 * According to the datasheet FARG[15:2] defines the page from which
778 * the erase will start.This page must be modulo 4, 8, 16 or 32
779 * according to the number of pages to erase. FARG[1:0] defines the
780 * number of pages to be erased. Previously (firstpage << 2) was used
781 * to conform to this, seems it should not be shifted...
783 return EFC_PerformCommand(pPrivate,
784 /* send Erase Page */
786 (firstPage) | erasePages,
791 * Gets current GPNVM state.
792 * @param pPrivate - info about the bank.
793 * @param gpnvm - GPNVM bit index.
794 * @param puthere - result stored here.
796 /* ------------------------------------------------------------------------------ */
797 static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
803 if (pPrivate->bank_number != 0) {
804 LOG_ERROR("GPNVM only works with Bank0");
808 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
809 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
810 gpnvm, pPrivate->pChip->details.n_gpnvms);
814 /* Get GPNVMs status */
815 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
821 r = EFC_GetResult(pPrivate, &v);
824 /* Check if GPNVM is set */
825 /* get the bit and make it a 0/1 */
826 *puthere = (v >> gpnvm) & 1;
833 * Clears the selected GPNVM bit.
834 * @param pPrivate info about the bank
835 * @param gpnvm GPNVM index.
836 * @returns 0 if successful; otherwise returns an error code.
838 static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
844 if (pPrivate->bank_number != 0) {
845 LOG_ERROR("GPNVM only works with Bank0");
849 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
850 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
851 gpnvm, pPrivate->pChip->details.n_gpnvms);
855 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
857 LOG_DEBUG("Failed: %d", r);
860 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
861 LOG_DEBUG("End: %d", r);
866 * Sets the selected GPNVM bit.
867 * @param pPrivate info about the bank
868 * @param gpnvm GPNVM index.
870 static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
875 if (pPrivate->bank_number != 0) {
876 LOG_ERROR("GPNVM only works with Bank0");
880 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
881 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
882 gpnvm, pPrivate->pChip->details.n_gpnvms);
886 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
894 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
900 * Returns a bit field (at most 64) of locked regions within a page.
901 * @param pPrivate info about the bank
902 * @param v where to store locked bits
904 static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
908 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
910 EFC_GetResult(pPrivate, v);
911 EFC_GetResult(pPrivate, v);
912 EFC_GetResult(pPrivate, v);
913 r = EFC_GetResult(pPrivate, v);
915 LOG_DEBUG("End: %d", r);
920 * Unlocks all the regions in the given address range.
921 * @param pPrivate info about the bank
922 * @param start_sector first sector to unlock
923 * @param end_sector last (inclusive) to unlock
926 static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
927 unsigned start_sector,
933 uint32_t pages_per_sector;
935 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
937 /* Unlock all pages */
938 while (start_sector <= end_sector) {
939 pg = start_sector * pages_per_sector;
941 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
952 * @param pPrivate - info about the bank
953 * @param start_sector - first sector to lock
954 * @param end_sector - last sector (inclusive) to lock
956 static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
957 unsigned start_sector,
962 uint32_t pages_per_sector;
965 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
968 while (start_sector <= end_sector) {
969 pg = start_sector * pages_per_sector;
971 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
979 /****** END SAM4 CODE ********/
981 /* begin helpful debug code */
982 /* print the fieldname, the field value, in dec & hex, and return field value */
983 static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
993 /* extract the field */
995 v = v & ((1 << width)-1);
1004 /* show the basics */
1005 LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
1006 REG_NAME_WIDTH, regname,
1012 static const char _unknown[] = "unknown";
1013 static const char *const eproc_names[] = {
1017 "cortex-m3", /* 3 */
1019 "arm926ejs", /* 5 */
1020 "cortex-a5", /* 6 */
1021 "cortex-m4", /* 7 */
1032 #define nvpsize2 nvpsize /* these two tables are identical */
1033 static const char *const nvpsize[] = {
1036 "16K bytes", /* 2 */
1037 "32K bytes", /* 3 */
1039 "64K bytes", /* 5 */
1041 "128K bytes", /* 7 */
1043 "256K bytes", /* 9 */
1044 "512K bytes", /* 10 */
1046 "1024K bytes", /* 12 */
1048 "2048K bytes", /* 14 */
1052 static const char *const sramsize[] = {
1053 "48K Bytes", /* 0 */
1057 "112K Bytes", /* 4 */
1059 "80K Bytes", /* 6 */
1060 "160K Bytes", /* 7 */
1062 "16K Bytes", /* 9 */
1063 "32K Bytes", /* 10 */
1064 "64K Bytes", /* 11 */
1065 "128K Bytes", /* 12 */
1066 "256K Bytes", /* 13 */
1067 "96K Bytes", /* 14 */
1068 "512K Bytes", /* 15 */
1072 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1073 { 0x19, "AT91SAM9xx Series" },
1074 { 0x29, "AT91SAM9XExx Series" },
1075 { 0x34, "AT91x34 Series" },
1076 { 0x37, "CAP7 Series" },
1077 { 0x39, "CAP9 Series" },
1078 { 0x3B, "CAP11 Series" },
1079 { 0x40, "AT91x40 Series" },
1080 { 0x42, "AT91x42 Series" },
1081 { 0x55, "AT91x55 Series" },
1082 { 0x60, "AT91SAM7Axx Series" },
1083 { 0x61, "AT91SAM7AQxx Series" },
1084 { 0x63, "AT91x63 Series" },
1085 { 0x70, "AT91SAM7Sxx Series" },
1086 { 0x71, "AT91SAM7XCxx Series" },
1087 { 0x72, "AT91SAM7SExx Series" },
1088 { 0x73, "AT91SAM7Lxx Series" },
1089 { 0x75, "AT91SAM7Xxx Series" },
1090 { 0x76, "AT91SAM7SLxx Series" },
1091 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1092 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1093 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
1094 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
1095 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
1096 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
1097 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
1098 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
1099 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
1100 { 0x92, "AT91x92 Series" },
1101 { 0x93, "ATSAM3NxA Series (48-pin version)" },
1102 { 0x94, "ATSAM3NxB Series (64-pin version)" },
1103 { 0x95, "ATSAM3NxC Series (100-pin version)" },
1104 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
1105 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
1106 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
1107 { 0xA5, "ATSAM5A" },
1108 { 0xF0, "AT75Cxx Series" },
1112 static const char *const nvptype[] = {
1114 "romless or onchip flash", /* 1 */
1115 "embedded flash memory",/* 2 */
1116 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
1117 "sram emulating flash", /* 4 */
1123 static const char *_yes_or_no(uint32_t v)
1131 static const char *const _rc_freq[] = {
1132 "4 MHz", "8 MHz", "12 MHz", "reserved"
1135 static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
1140 v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1141 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
1142 v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1143 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
1144 rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
1145 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
1146 v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1147 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
1149 pChip->cfg.rc_freq = 0;
1153 pChip->cfg.rc_freq = 0;
1156 pChip->cfg.rc_freq = 4 * 1000 * 1000;
1159 pChip->cfg.rc_freq = 8 * 1000 * 1000;
1162 pChip->cfg.rc_freq = 12 * 1000 * 1000;
1167 v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1168 LOG_USER("(startup clks, time= %f uSecs)",
1169 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1170 v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1171 LOG_USER("(mainosc source: %s)",
1172 v ? "external xtal" : "internal RC");
1174 v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1175 LOG_USER("(clock failure enabled: %s)",
1179 static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
1185 sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1188 v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1189 LOG_USER("%s", eproc_names[v]);
1191 v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1192 LOG_USER("%s", nvpsize[v]);
1194 v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1195 LOG_USER("%s", nvpsize2[v]);
1197 v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
1198 LOG_USER("%s", sramsize[v]);
1200 v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1202 for (x = 0; archnames[x].name; x++) {
1203 if (v == archnames[x].value) {
1204 cp = archnames[x].name;
1211 v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1212 LOG_USER("%s", nvptype[v]);
1214 v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1215 LOG_USER("(exists: %s)", _yes_or_no(v));
1218 static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
1222 v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1223 LOG_USER("(main ready: %s)", _yes_or_no(v));
1225 v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1227 v = (v * pChip->cfg.slow_freq) / 16;
1228 pChip->cfg.mainosc_freq = v;
1230 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
1232 (uint32_t)(pChip->cfg.slow_freq / 1000),
1233 (uint32_t)(pChip->cfg.slow_freq % 1000));
1236 static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
1238 uint32_t mula, diva;
1240 diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1242 mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1244 pChip->cfg.plla_freq = 0;
1246 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
1248 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
1249 else if (diva >= 1) {
1250 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
1251 LOG_USER("\tPLLA Freq: %3.03f MHz",
1252 _tomhz(pChip->cfg.plla_freq));
1256 static void sam4_explain_mckr(struct sam4_chip *pChip)
1258 uint32_t css, pres, fin = 0;
1260 const char *cp = NULL;
1262 css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1265 fin = pChip->cfg.slow_freq;
1269 fin = pChip->cfg.mainosc_freq;
1273 fin = pChip->cfg.plla_freq;
1277 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
1278 fin = 480 * 1000 * 1000;
1282 cp = "upll (*ERROR* UPLL is disabled)";
1290 LOG_USER("%s (%3.03f Mhz)",
1293 pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
1294 switch (pres & 0x07) {
1297 cp = "selected clock";
1331 LOG_USER("(%s)", cp);
1333 /* sam4 has a *SINGLE* clock - */
1334 /* other at91 series parts have divisors for these. */
1335 pChip->cfg.cpu_freq = fin;
1336 pChip->cfg.mclk_freq = fin;
1337 pChip->cfg.fclk_freq = fin;
1338 LOG_USER("\t\tResult CPU Freq: %3.03f",
1343 static struct sam4_chip *target2sam4(struct target *pTarget)
1345 struct sam4_chip *pChip;
1347 if (pTarget == NULL)
1350 pChip = all_sam4_chips;
1352 if (pChip->target == pTarget)
1353 break; /* return below */
1355 pChip = pChip->next;
1361 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
1363 /* this function exists to help */
1364 /* keep funky offsetof() errors */
1365 /* and casting from causing bugs */
1367 /* By using prototypes - we can detect what would */
1368 /* be casting errors. */
1370 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
1374 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
1376 NAME), # NAME, FUNC }
1377 static const struct sam4_reg_list sam4_all_regs[] = {
1378 SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
1379 SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
1380 SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
1381 SAM4_ENTRY(CKGR_UCKR, NULL),
1382 SAM4_ENTRY(PMC_FSMR, NULL),
1383 SAM4_ENTRY(PMC_FSPR, NULL),
1384 SAM4_ENTRY(PMC_IMR, NULL),
1385 SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
1386 SAM4_ENTRY(PMC_PCK0, NULL),
1387 SAM4_ENTRY(PMC_PCK1, NULL),
1388 SAM4_ENTRY(PMC_PCK2, NULL),
1389 SAM4_ENTRY(PMC_PCSR, NULL),
1390 SAM4_ENTRY(PMC_SCSR, NULL),
1391 SAM4_ENTRY(PMC_SR, NULL),
1392 SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
1393 SAM4_ENTRY(CHIPID_EXID, NULL),
1394 /* TERMINATE THE LIST */
1399 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
1401 return bank->driver_priv;
1405 * Given a pointer to where it goes in the structure,
1406 * determine the register name, address from the all registers table.
1408 static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
1410 const struct sam4_reg_list *pReg;
1412 pReg = &(sam4_all_regs[0]);
1413 while (pReg->name) {
1414 uint32_t *pPossible;
1416 /* calculate where this one go.. */
1417 /* it is "possibly" this register. */
1419 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
1421 /* well? Is it this register */
1422 if (pPossible == goes_here) {
1430 /* This is *TOTAL*PANIC* - we are totally screwed. */
1431 LOG_ERROR("INVALID SAM4 REGISTER");
1435 static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
1437 const struct sam4_reg_list *pReg;
1440 pReg = sam4_GetReg(pChip, goes_here);
1444 r = target_read_u32(pChip->target, pReg->address, goes_here);
1445 if (r != ERROR_OK) {
1446 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
1447 pReg->name, (unsigned)(pReg->address), r);
1452 static int sam4_ReadAllRegs(struct sam4_chip *pChip)
1455 const struct sam4_reg_list *pReg;
1457 pReg = &(sam4_all_regs[0]);
1458 while (pReg->name) {
1459 r = sam4_ReadThisReg(pChip,
1460 sam4_get_reg_ptr(&(pChip->cfg), pReg));
1461 if (r != ERROR_OK) {
1462 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
1463 pReg->name, ((unsigned)(pReg->address)), r);
1472 static int sam4_GetInfo(struct sam4_chip *pChip)
1474 const struct sam4_reg_list *pReg;
1477 pReg = &(sam4_all_regs[0]);
1478 while (pReg->name) {
1479 /* display all regs */
1480 LOG_DEBUG("Start: %s", pReg->name);
1481 regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
1482 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
1487 if (pReg->explain_func)
1488 (*(pReg->explain_func))(pChip);
1489 LOG_DEBUG("End: %s", pReg->name);
1492 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
1493 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
1494 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
1495 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
1496 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
1498 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
1499 pChip->cfg.unique_id[0],
1500 pChip->cfg.unique_id[1],
1501 pChip->cfg.unique_id[2],
1502 pChip->cfg.unique_id[3]);
1507 static int sam4_protect_check(struct flash_bank *bank)
1510 uint32_t v[4] = {0};
1512 struct sam4_bank_private *pPrivate;
1515 if (bank->target->state != TARGET_HALTED) {
1516 LOG_ERROR("Target not halted");
1517 return ERROR_TARGET_NOT_HALTED;
1520 pPrivate = get_sam4_bank_private(bank);
1522 LOG_ERROR("no private for this bank?");
1525 if (!(pPrivate->probed))
1526 return ERROR_FLASH_BANK_NOT_PROBED;
1528 r = FLASHD_GetLockBits(pPrivate, v);
1529 if (r != ERROR_OK) {
1530 LOG_DEBUG("Failed: %d", r);
1534 for (x = 0; x < pPrivate->nsectors; x++)
1535 bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
1540 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
1542 struct sam4_chip *pChip;
1544 pChip = all_sam4_chips;
1546 /* is this an existing chip? */
1548 if (pChip->target == bank->target)
1550 pChip = pChip->next;
1554 /* this is a *NEW* chip */
1555 pChip = calloc(1, sizeof(struct sam4_chip));
1557 LOG_ERROR("NO RAM!");
1560 pChip->target = bank->target;
1561 /* insert at head */
1562 pChip->next = all_sam4_chips;
1563 all_sam4_chips = pChip;
1564 pChip->target = bank->target;
1565 /* assumption is this runs at 32khz */
1566 pChip->cfg.slow_freq = 32768;
1570 switch (bank->base) {
1572 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
1573 "[at91sam4s series] )",
1574 ((unsigned int)(bank->base)),
1575 ((unsigned int)(FLASH_BANK_BASE_S)));
1579 /* at91sam4s series only has bank 0*/
1580 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
1581 case FLASH_BANK_BASE_S:
1582 bank->driver_priv = &(pChip->details.bank[0]);
1583 bank->bank_number = 0;
1584 pChip->details.bank[0].pChip = pChip;
1585 pChip->details.bank[0].pBank = bank;
1588 /* Bank 1 of at91sam4sd series */
1589 case FLASH_BANK1_BASE_1024K_SD:
1590 case FLASH_BANK1_BASE_2048K_SD:
1591 bank->driver_priv = &(pChip->details.bank[1]);
1592 bank->bank_number = 1;
1593 pChip->details.bank[1].pChip = pChip;
1594 pChip->details.bank[1].pBank = bank;
1598 /* we initialize after probing. */
1602 static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
1604 const struct sam4_chip_details *pDetails;
1605 struct sam4_chip *pChip;
1606 struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
1610 pDetails = all_sam4_details;
1611 while (pDetails->name) {
1612 /* Compare cidr without version bits */
1613 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
1618 if (pDetails->name == NULL) {
1619 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
1620 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
1621 /* Help the victim, print details about the chip */
1622 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
1623 pPrivate->pChip->cfg.CHIPID_CIDR);
1624 sam4_explain_chipid_cidr(pPrivate->pChip);
1628 /* DANGER: THERE ARE DRAGONS HERE */
1630 /* get our pChip - it is going */
1631 /* to be over-written shortly */
1632 pChip = pPrivate->pChip;
1634 /* Note that, in reality: */
1636 /* pPrivate = &(pChip->details.bank[0]) */
1637 /* or pPrivate = &(pChip->details.bank[1]) */
1640 /* save the "bank" pointers */
1641 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
1642 saved_banks[x] = pChip->details.bank[x].pBank;
1644 /* Overwrite the "details" structure. */
1645 memcpy(&(pPrivate->pChip->details),
1647 sizeof(pPrivate->pChip->details));
1649 /* now fix the ghosted pointers */
1650 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
1651 pChip->details.bank[x].pChip = pChip;
1652 pChip->details.bank[x].pBank = saved_banks[x];
1655 /* update the *BANK*SIZE* */
1661 static int _sam4_probe(struct flash_bank *bank, int noise)
1665 struct sam4_bank_private *pPrivate;
1668 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
1669 if (bank->target->state != TARGET_HALTED) {
1670 LOG_ERROR("Target not halted");
1671 return ERROR_TARGET_NOT_HALTED;
1674 pPrivate = get_sam4_bank_private(bank);
1676 LOG_ERROR("Invalid/unknown bank number");
1680 r = sam4_ReadAllRegs(pPrivate->pChip);
1685 if (pPrivate->pChip->probed)
1686 r = sam4_GetInfo(pPrivate->pChip);
1688 r = sam4_GetDetails(pPrivate);
1692 /* update the flash bank size */
1693 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
1694 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
1695 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
1700 if (bank->sectors == NULL) {
1701 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
1702 if (bank->sectors == NULL) {
1703 LOG_ERROR("No memory!");
1706 bank->num_sectors = pPrivate->nsectors;
1708 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
1709 bank->sectors[x].size = pPrivate->sector_size;
1710 bank->sectors[x].offset = x * (pPrivate->sector_size);
1711 /* mark as unknown */
1712 bank->sectors[x].is_erased = -1;
1713 bank->sectors[x].is_protected = -1;
1717 pPrivate->probed = 1;
1719 r = sam4_protect_check(bank);
1723 LOG_DEBUG("Bank = %d, nbanks = %d",
1724 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
1725 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
1726 /* read unique id, */
1727 /* it appears to be associated with the *last* flash bank. */
1728 FLASHD_ReadUniqueID(pPrivate);
1734 static int sam4_probe(struct flash_bank *bank)
1736 return _sam4_probe(bank, 1);
1739 static int sam4_auto_probe(struct flash_bank *bank)
1741 return _sam4_probe(bank, 0);
1744 static int sam4_erase(struct flash_bank *bank, int first, int last)
1746 struct sam4_bank_private *pPrivate;
1750 /*16 pages equals 8KB - Same size as a lock region*/
1755 if (bank->target->state != TARGET_HALTED) {
1756 LOG_ERROR("Target not halted");
1757 return ERROR_TARGET_NOT_HALTED;
1760 r = sam4_auto_probe(bank);
1761 if (r != ERROR_OK) {
1762 LOG_DEBUG("Here,r=%d", r);
1766 pPrivate = get_sam4_bank_private(bank);
1767 if (!(pPrivate->probed))
1768 return ERROR_FLASH_BANK_NOT_PROBED;
1770 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
1773 return FLASHD_EraseEntireBank(pPrivate);
1775 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
1776 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
1777 for (i = first; i <= last; i++) {
1778 /*16 pages equals 8KB - Same size as a lock region*/
1779 r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
1780 LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
1782 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
1784 if (status & (1 << 2)) {
1785 LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i));
1788 if (status & (1 << 1)) {
1789 LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
1797 static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
1799 struct sam4_bank_private *pPrivate;
1803 if (bank->target->state != TARGET_HALTED) {
1804 LOG_ERROR("Target not halted");
1805 return ERROR_TARGET_NOT_HALTED;
1808 pPrivate = get_sam4_bank_private(bank);
1809 if (!(pPrivate->probed))
1810 return ERROR_FLASH_BANK_NOT_PROBED;
1813 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
1815 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
1816 LOG_DEBUG("End: r=%d", r);
1822 static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
1827 adr = pagenum * pPrivate->page_size;
1828 adr = adr + pPrivate->base_address;
1830 r = target_read_memory(pPrivate->pChip->target,
1832 4, /* THIS*MUST*BE* in 32bit values */
1833 pPrivate->page_size / 4,
1836 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
1837 (unsigned int)(adr));
1841 static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
1845 uint32_t fmr; /* EEFC Flash Mode Register */
1848 adr = pagenum * pPrivate->page_size;
1849 adr = (adr + pPrivate->base_address);
1851 /* Get flash mode register value */
1852 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
1854 LOG_DEBUG("Error Read failed: read flash mode register");
1856 /* Clear flash wait state field */
1859 /* set FWS (flash wait states) field in the FMR (flash mode register) */
1860 fmr |= (pPrivate->flash_wait_states << 8);
1862 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
1863 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
1865 LOG_DEBUG("Error Write failed: set flash mode register");
1867 /* 1st sector 8kBytes - page 0 - 15*/
1868 /* 2nd sector 8kBytes - page 16 - 30*/
1869 /* 3rd sector 48kBytes - page 31 - 127*/
1870 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
1871 r = target_write_memory(pPrivate->pChip->target,
1873 4, /* THIS*MUST*BE* in 32bit values */
1874 pPrivate->page_size / 4,
1876 if (r != ERROR_OK) {
1877 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
1878 (unsigned int)(adr));
1882 r = EFC_PerformCommand(pPrivate,
1883 /* send Erase & Write Page */
1884 AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
1889 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
1890 (unsigned int)(adr));
1891 if (status & (1 << 2)) {
1892 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
1895 if (status & (1 << 1)) {
1896 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
1902 static int sam4_write(struct flash_bank *bank,
1911 unsigned page_offset;
1912 struct sam4_bank_private *pPrivate;
1913 uint8_t *pagebuffer;
1915 /* incase we bail further below, set this to null */
1918 /* ignore dumb requests */
1924 if (bank->target->state != TARGET_HALTED) {
1925 LOG_ERROR("Target not halted");
1926 r = ERROR_TARGET_NOT_HALTED;
1930 pPrivate = get_sam4_bank_private(bank);
1931 if (!(pPrivate->probed)) {
1932 r = ERROR_FLASH_BANK_NOT_PROBED;
1936 if ((offset + count) > pPrivate->size_bytes) {
1937 LOG_ERROR("Flash write error - past end of bank");
1938 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
1939 (unsigned int)(offset),
1940 (unsigned int)(count),
1941 (unsigned int)(pPrivate->size_bytes));
1946 pagebuffer = malloc(pPrivate->page_size);
1948 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
1953 /* what page do we start & end in? */
1954 page_cur = offset / pPrivate->page_size;
1955 page_end = (offset + count - 1) / pPrivate->page_size;
1957 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
1958 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
1960 /* Special case: all one page */
1963 /* (1) non-aligned start */
1964 /* (2) body pages */
1965 /* (3) non-aligned end. */
1967 /* Handle special case - all one page. */
1968 if (page_cur == page_end) {
1969 LOG_DEBUG("Special case, all in one page");
1970 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
1974 page_offset = (offset & (pPrivate->page_size-1));
1975 memcpy(pagebuffer + page_offset,
1979 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
1986 /* non-aligned start */
1987 page_offset = offset & (pPrivate->page_size - 1);
1989 LOG_DEBUG("Not-Aligned start");
1990 /* read the partial */
1991 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
1995 /* over-write with new data */
1996 n = (pPrivate->page_size - page_offset);
1997 memcpy(pagebuffer + page_offset,
2001 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2011 /* By checking that offset is correct here, we also
2012 fix a clang warning */
2013 assert(offset % pPrivate->page_size == 0);
2015 /* intermediate large pages */
2016 /* also - the final *terminal* */
2017 /* if that terminal page is a full page */
2018 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2019 (int)page_cur, (int)page_end, (unsigned int)(count));
2021 while ((page_cur < page_end) &&
2022 (count >= pPrivate->page_size)) {
2023 r = sam4_page_write(pPrivate, page_cur, buffer);
2026 count -= pPrivate->page_size;
2027 buffer += pPrivate->page_size;
2031 /* terminal partial page? */
2033 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2034 /* we have a partial page */
2035 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2038 /* data goes at start */
2039 memcpy(pagebuffer, buffer, count);
2040 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2052 COMMAND_HANDLER(sam4_handle_info_command)
2054 struct sam4_chip *pChip;
2055 pChip = get_current_sam4(CMD_CTX);
2062 /* bank0 must exist before we can do anything */
2063 if (pChip->details.bank[0].pBank == NULL) {
2066 command_print(CMD_CTX,
2067 "Please define bank %d via command: flash bank %s ... ",
2069 at91sam4_flash.name);
2073 /* if bank 0 is not probed, then probe it */
2074 if (!(pChip->details.bank[0].probed)) {
2075 r = sam4_auto_probe(pChip->details.bank[0].pBank);
2079 /* above guarantees the "chip details" structure is valid */
2080 /* and thus, bank private areas are valid */
2081 /* and we have a SAM4 chip, what a concept! */
2083 /* auto-probe other banks, 0 done above */
2084 for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
2085 /* skip banks not present */
2086 if (!(pChip->details.bank[x].present))
2089 if (pChip->details.bank[x].pBank == NULL)
2092 if (pChip->details.bank[x].probed)
2095 r = sam4_auto_probe(pChip->details.bank[x].pBank);
2100 r = sam4_GetInfo(pChip);
2101 if (r != ERROR_OK) {
2102 LOG_DEBUG("Sam4Info, Failed %d", r);
2109 COMMAND_HANDLER(sam4_handle_gpnvm_command)
2113 struct sam4_chip *pChip;
2115 pChip = get_current_sam4(CMD_CTX);
2119 if (pChip->target->state != TARGET_HALTED) {
2120 LOG_ERROR("sam4 - target not halted");
2121 return ERROR_TARGET_NOT_HALTED;
2124 if (pChip->details.bank[0].pBank == NULL) {
2125 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
2126 at91sam4_flash.name);
2129 if (!pChip->details.bank[0].probed) {
2130 r = sam4_auto_probe(pChip->details.bank[0].pBank);
2137 return ERROR_COMMAND_SYNTAX_ERROR;
2146 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
2150 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
2156 if (0 == strcmp("show", CMD_ARGV[0])) {
2160 for (x = 0; x < pChip->details.n_gpnvms; x++) {
2161 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
2164 command_print(CMD_CTX, "sam4-gpnvm%u: %u", x, v);
2168 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
2169 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
2170 command_print(CMD_CTX, "sam4-gpnvm%u: %u", who, v);
2173 command_print(CMD_CTX, "sam4-gpnvm invalid GPNVM: %u", who);
2174 return ERROR_COMMAND_SYNTAX_ERROR;
2179 command_print(CMD_CTX, "Missing GPNVM number");
2180 return ERROR_COMMAND_SYNTAX_ERROR;
2183 if (0 == strcmp("set", CMD_ARGV[0]))
2184 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
2185 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
2186 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
2187 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
2189 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
2190 r = ERROR_COMMAND_SYNTAX_ERROR;
2195 COMMAND_HANDLER(sam4_handle_slowclk_command)
2197 struct sam4_chip *pChip;
2199 pChip = get_current_sam4(CMD_CTX);
2211 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
2213 /* absurd slow clock of 200Khz? */
2214 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
2215 return ERROR_COMMAND_SYNTAX_ERROR;
2217 pChip->cfg.slow_freq = v;
2222 command_print(CMD_CTX, "Too many parameters");
2223 return ERROR_COMMAND_SYNTAX_ERROR;
2226 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
2227 (int)(pChip->cfg.slow_freq / 1000),
2228 (int)(pChip->cfg.slow_freq % 1000));
2232 static const struct command_registration at91sam4_exec_command_handlers[] = {
2235 .handler = sam4_handle_gpnvm_command,
2236 .mode = COMMAND_EXEC,
2237 .usage = "[('clr'|'set'|'show') bitnum]",
2238 .help = "Without arguments, shows all bits in the gpnvm "
2239 "register. Otherwise, clears, sets, or shows one "
2240 "General Purpose Non-Volatile Memory (gpnvm) bit.",
2244 .handler = sam4_handle_info_command,
2245 .mode = COMMAND_EXEC,
2246 .help = "Print information about the current at91sam4 chip"
2247 "and its flash configuration.",
2251 .handler = sam4_handle_slowclk_command,
2252 .mode = COMMAND_EXEC,
2253 .usage = "[clock_hz]",
2254 .help = "Display or set the slowclock frequency "
2255 "(default 32768 Hz).",
2257 COMMAND_REGISTRATION_DONE
2259 static const struct command_registration at91sam4_command_handlers[] = {
2262 .mode = COMMAND_ANY,
2263 .help = "at91sam4 flash command group",
2265 .chain = at91sam4_exec_command_handlers,
2267 COMMAND_REGISTRATION_DONE
2270 struct flash_driver at91sam4_flash = {
2272 .commands = at91sam4_command_handlers,
2273 .flash_bank_command = sam4_flash_bank_command,
2274 .erase = sam4_erase,
2275 .protect = sam4_protect,
2276 .write = sam4_write,
2277 .read = default_flash_read,
2278 .probe = sam4_probe,
2279 .auto_probe = sam4_auto_probe,
2280 .erase_check = default_flash_blank_check,
2281 .protect_check = sam4_protect_check,