1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken (at91sam3x* support) * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
18 * GNU General public License for more details. *
20 * You should have received a copy of the GNU General public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ****************************************************************************/
26 /* Some of the the lower level code was based on code supplied by
27 * ATMEL under this copyright. */
29 /* BEGIN ATMEL COPYRIGHT */
30 /* ----------------------------------------------------------------------------
31 * ATMEL Microcontroller Software Support
32 * ----------------------------------------------------------------------------
33 * Copyright (c) 2009, Atmel Corporation
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions are met:
40 * - Redistributions of source code must retain the above copyright notice,
41 * this list of conditions and the disclaimer below.
43 * Atmel's name may not be used to endorse or promote products derived from
44 * this software without specific prior written permission.
46 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
48 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
49 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
52 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
53 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
54 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
55 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 * ----------------------------------------------------------------------------
58 /* END ATMEL COPYRIGHT */
65 #include <helper/time_support.h>
67 #define REG_NAME_WIDTH (12)
69 /* at91sam3u series (has one or two flash banks) */
70 #define FLASH_BANK0_BASE_U 0x00080000
71 #define FLASH_BANK1_BASE_U 0x00100000
73 /* at91sam3s series (has always one flash bank) */
74 #define FLASH_BANK_BASE_S 0x00400000
76 /* at91sam3n series (has always one flash bank) */
77 #define FLASH_BANK_BASE_N 0x00400000
79 /* at91sam3a/x series has two flash banks*/
80 #define FLASH_BANK0_BASE_AX 0x00080000
81 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
82 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
83 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
85 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
86 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
88 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
89 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
90 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
91 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
92 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page
94 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
95 /* cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
96 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
97 /* cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
98 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
99 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
100 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
101 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
102 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
103 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
104 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
105 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
106 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
108 #define offset_EFC_FMR 0
109 #define offset_EFC_FCR 4
110 #define offset_EFC_FSR 8
111 #define offset_EFC_FRR 12
113 extern struct flash_driver at91sam3_flash;
115 static float _tomhz(uint32_t freq_hz)
119 f = ((float)(freq_hz)) / 1000000.0;
123 /* How the chip is configured. */
125 uint32_t unique_id[4];
129 uint32_t mainosc_freq;
139 #define SAM3_CHIPID_CIDR (0x400E0740)
140 uint32_t CHIPID_CIDR;
141 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
142 uint32_t CHIPID_CIDR2;
143 #define SAM3_CHIPID_EXID (0x400E0744)
144 uint32_t CHIPID_EXID;
145 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
146 uint32_t CHIPID_EXID2;
149 #define SAM3_PMC_BASE (0x400E0400)
150 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
152 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
154 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
156 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
158 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
160 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
162 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
164 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
166 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
168 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
170 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
172 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
174 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
176 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
181 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
182 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
183 * the flash wait state (FWS) should be set to 6. It seems like that the
184 * cause of the problem is not the flash itself, but the flash write
185 * buffer. Ie the wait states have to be set before writing into the
187 * Tested and confirmed with SAM3N and SAM3U
190 struct sam3_bank_private {
192 /* DANGER: THERE ARE DRAGONS HERE.. */
193 /* NOTE: If you add more 'ghost' pointers */
194 /* be aware that you must *manually* update */
195 /* these pointers in the function sam3_GetDetails() */
196 /* See the comment "Here there be dragons" */
198 /* so we can find the chip we belong to */
199 struct sam3_chip *pChip;
200 /* so we can find the orginal bank pointer */
201 struct flash_bank *pBank;
202 unsigned bank_number;
203 uint32_t controller_address;
204 uint32_t base_address;
205 uint32_t flash_wait_states;
209 unsigned sector_size;
213 struct sam3_chip_details {
214 /* THERE ARE DRAGONS HERE.. */
215 /* note: If you add pointers here */
216 /* becareful about them as they */
217 /* may need to be updated inside */
218 /* the function: "sam3_GetDetails() */
219 /* which copy/overwrites the */
220 /* 'runtime' copy of this structure */
221 uint32_t chipid_cidr;
225 #define SAM3_N_NVM_BITS 3
226 unsigned gpnvm[SAM3_N_NVM_BITS];
227 unsigned total_flash_size;
228 unsigned total_sram_size;
230 #define SAM3_MAX_FLASH_BANKS 2
231 /* these are "initialized" from the global const data */
232 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
236 struct sam3_chip *next;
239 /* this is "initialized" from the global const structure */
240 struct sam3_chip_details details;
241 struct target *target;
246 struct sam3_reg_list {
247 uint32_t address; size_t struct_offset; const char *name;
248 void (*explain_func)(struct sam3_chip *pInfo);
251 static struct sam3_chip *all_sam3_chips;
253 static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
256 static struct sam3_chip *p;
258 t = get_current_target(cmd_ctx);
260 command_print(cmd_ctx, "No current target?");
266 /* this should not happen */
267 /* the command is not registered until the chip is created? */
268 command_print(cmd_ctx, "No SAM3 chips exist?");
277 command_print(cmd_ctx, "Cannot find SAM3 chip?");
281 /* these are used to *initialize* the "pChip->details" structure. */
282 static const struct sam3_chip_details all_sam3_details[] = {
283 /* Start at91sam3u* series */
285 .chipid_cidr = 0x28100960,
286 .name = "at91sam3u4e",
287 .total_flash_size = 256 * 1024,
288 .total_sram_size = 52 * 1024,
292 /* System boots at address 0x0 */
293 /* gpnvm[1] = selects boot code */
294 /* if gpnvm[1] == 0 */
295 /* boot is via "SAMBA" (rom) */
297 /* boot is via FLASH */
298 /* Selection is via gpnvm[2] */
301 /* NOTE: banks 0 & 1 switch places */
302 /* if gpnvm[2] == 0 */
303 /* Bank0 is the boot rom */
305 /* Bank1 is the boot rom */
314 .base_address = FLASH_BANK0_BASE_U,
315 .controller_address = 0x400e0800,
316 .flash_wait_states = 6, /* workaround silicon bug */
318 .size_bytes = 128 * 1024,
330 .base_address = FLASH_BANK1_BASE_U,
331 .controller_address = 0x400e0a00,
332 .flash_wait_states = 6, /* workaround silicon bug */
334 .size_bytes = 128 * 1024,
343 .chipid_cidr = 0x281a0760,
344 .name = "at91sam3u2e",
345 .total_flash_size = 128 * 1024,
346 .total_sram_size = 36 * 1024,
350 /* System boots at address 0x0 */
351 /* gpnvm[1] = selects boot code */
352 /* if gpnvm[1] == 0 */
353 /* boot is via "SAMBA" (rom) */
355 /* boot is via FLASH */
356 /* Selection is via gpnvm[2] */
365 .base_address = FLASH_BANK0_BASE_U,
366 .controller_address = 0x400e0800,
367 .flash_wait_states = 6, /* workaround silicon bug */
369 .size_bytes = 128 * 1024,
383 .chipid_cidr = 0x28190560,
384 .name = "at91sam3u1e",
385 .total_flash_size = 64 * 1024,
386 .total_sram_size = 20 * 1024,
390 /* System boots at address 0x0 */
391 /* gpnvm[1] = selects boot code */
392 /* if gpnvm[1] == 0 */
393 /* boot is via "SAMBA" (rom) */
395 /* boot is via FLASH */
396 /* Selection is via gpnvm[2] */
407 .base_address = FLASH_BANK0_BASE_U,
408 .controller_address = 0x400e0800,
409 .flash_wait_states = 6, /* workaround silicon bug */
411 .size_bytes = 64 * 1024,
427 .chipid_cidr = 0x28000960,
428 .name = "at91sam3u4c",
429 .total_flash_size = 256 * 1024,
430 .total_sram_size = 52 * 1024,
434 /* System boots at address 0x0 */
435 /* gpnvm[1] = selects boot code */
436 /* if gpnvm[1] == 0 */
437 /* boot is via "SAMBA" (rom) */
439 /* boot is via FLASH */
440 /* Selection is via gpnvm[2] */
443 /* NOTE: banks 0 & 1 switch places */
444 /* if gpnvm[2] == 0 */
445 /* Bank0 is the boot rom */
447 /* Bank1 is the boot rom */
456 .base_address = FLASH_BANK0_BASE_U,
457 .controller_address = 0x400e0800,
458 .flash_wait_states = 6, /* workaround silicon bug */
460 .size_bytes = 128 * 1024,
471 .base_address = FLASH_BANK1_BASE_U,
472 .controller_address = 0x400e0a00,
473 .flash_wait_states = 6, /* workaround silicon bug */
475 .size_bytes = 128 * 1024,
484 .chipid_cidr = 0x280a0760,
485 .name = "at91sam3u2c",
486 .total_flash_size = 128 * 1024,
487 .total_sram_size = 36 * 1024,
491 /* System boots at address 0x0 */
492 /* gpnvm[1] = selects boot code */
493 /* if gpnvm[1] == 0 */
494 /* boot is via "SAMBA" (rom) */
496 /* boot is via FLASH */
497 /* Selection is via gpnvm[2] */
506 .base_address = FLASH_BANK0_BASE_U,
507 .controller_address = 0x400e0800,
508 .flash_wait_states = 6, /* workaround silicon bug */
510 .size_bytes = 128 * 1024,
524 .chipid_cidr = 0x28090560,
525 .name = "at91sam3u1c",
526 .total_flash_size = 64 * 1024,
527 .total_sram_size = 20 * 1024,
531 /* System boots at address 0x0 */
532 /* gpnvm[1] = selects boot code */
533 /* if gpnvm[1] == 0 */
534 /* boot is via "SAMBA" (rom) */
536 /* boot is via FLASH */
537 /* Selection is via gpnvm[2] */
548 .base_address = FLASH_BANK0_BASE_U,
549 .controller_address = 0x400e0800,
550 .flash_wait_states = 6, /* workaround silicon bug */
552 .size_bytes = 64 * 1024,
567 /* Start at91sam3s* series */
569 /* Note: The preliminary at91sam3s datasheet says on page 302 */
570 /* that the flash controller is at address 0x400E0800. */
571 /* This is _not_ the case, the controller resides at address 0x400e0a0. */
573 .chipid_cidr = 0x28A00960,
574 .name = "at91sam3s4c",
575 .total_flash_size = 256 * 1024,
576 .total_sram_size = 48 * 1024,
586 .base_address = FLASH_BANK_BASE_S,
587 .controller_address = 0x400e0a00,
588 .flash_wait_states = 6, /* workaround silicon bug */
590 .size_bytes = 256 * 1024,
592 .sector_size = 16384,
606 .chipid_cidr = 0x28900960,
607 .name = "at91sam3s4b",
608 .total_flash_size = 256 * 1024,
609 .total_sram_size = 48 * 1024,
619 .base_address = FLASH_BANK_BASE_S,
620 .controller_address = 0x400e0a00,
621 .flash_wait_states = 6, /* workaround silicon bug */
623 .size_bytes = 256 * 1024,
625 .sector_size = 16384,
638 .chipid_cidr = 0x28800960,
639 .name = "at91sam3s4a",
640 .total_flash_size = 256 * 1024,
641 .total_sram_size = 48 * 1024,
651 .base_address = FLASH_BANK_BASE_S,
652 .controller_address = 0x400e0a00,
653 .flash_wait_states = 6, /* workaround silicon bug */
655 .size_bytes = 256 * 1024,
657 .sector_size = 16384,
670 .chipid_cidr = 0x28AA0760,
671 .name = "at91sam3s2c",
672 .total_flash_size = 128 * 1024,
673 .total_sram_size = 32 * 1024,
683 .base_address = FLASH_BANK_BASE_S,
684 .controller_address = 0x400e0a00,
685 .flash_wait_states = 6, /* workaround silicon bug */
687 .size_bytes = 128 * 1024,
689 .sector_size = 16384,
702 .chipid_cidr = 0x289A0760,
703 .name = "at91sam3s2b",
704 .total_flash_size = 128 * 1024,
705 .total_sram_size = 32 * 1024,
715 .base_address = FLASH_BANK_BASE_S,
716 .controller_address = 0x400e0a00,
717 .flash_wait_states = 6, /* workaround silicon bug */
719 .size_bytes = 128 * 1024,
721 .sector_size = 16384,
734 .chipid_cidr = 0x29ab0a60,
735 .name = "at91sam3sd8c",
736 .total_flash_size = 512 * 1024,
737 .total_sram_size = 64 * 1024,
747 .base_address = FLASH_BANK0_BASE_SD,
748 .controller_address = 0x400e0a00,
749 .flash_wait_states = 6, /* workaround silicon bug */
751 .size_bytes = 256 * 1024,
753 .sector_size = 16384,
762 .base_address = FLASH_BANK1_BASE_512K_SD,
763 .controller_address = 0x400e0a00,
764 .flash_wait_states = 6, /* workaround silicon bug */
766 .size_bytes = 256 * 1024,
768 .sector_size = 16384,
774 .chipid_cidr = 0x288A0760,
775 .name = "at91sam3s2a",
776 .total_flash_size = 128 * 1024,
777 .total_sram_size = 32 * 1024,
787 .base_address = FLASH_BANK_BASE_S,
788 .controller_address = 0x400e0a00,
789 .flash_wait_states = 6, /* workaround silicon bug */
791 .size_bytes = 128 * 1024,
793 .sector_size = 16384,
806 .chipid_cidr = 0x28A90560,
807 .name = "at91sam3s1c",
808 .total_flash_size = 64 * 1024,
809 .total_sram_size = 16 * 1024,
819 .base_address = FLASH_BANK_BASE_S,
820 .controller_address = 0x400e0a00,
821 .flash_wait_states = 6, /* workaround silicon bug */
823 .size_bytes = 64 * 1024,
825 .sector_size = 16384,
838 .chipid_cidr = 0x28990560,
839 .name = "at91sam3s1b",
840 .total_flash_size = 64 * 1024,
841 .total_sram_size = 16 * 1024,
851 .base_address = FLASH_BANK_BASE_S,
852 .controller_address = 0x400e0a00,
853 .flash_wait_states = 6, /* workaround silicon bug */
855 .size_bytes = 64 * 1024,
857 .sector_size = 16384,
870 .chipid_cidr = 0x28890560,
871 .name = "at91sam3s1a",
872 .total_flash_size = 64 * 1024,
873 .total_sram_size = 16 * 1024,
883 .base_address = FLASH_BANK_BASE_S,
884 .controller_address = 0x400e0a00,
885 .flash_wait_states = 6, /* workaround silicon bug */
887 .size_bytes = 64 * 1024,
889 .sector_size = 16384,
902 /* Start at91sam3n* series */
904 .chipid_cidr = 0x29540960,
905 .name = "at91sam3n4c",
906 .total_flash_size = 256 * 1024,
907 .total_sram_size = 24 * 1024,
911 /* System boots at address 0x0 */
912 /* gpnvm[1] = selects boot code */
913 /* if gpnvm[1] == 0 */
914 /* boot is via "SAMBA" (rom) */
916 /* boot is via FLASH */
917 /* Selection is via gpnvm[2] */
920 /* NOTE: banks 0 & 1 switch places */
921 /* if gpnvm[2] == 0 */
922 /* Bank0 is the boot rom */
924 /* Bank1 is the boot rom */
933 .base_address = FLASH_BANK_BASE_N,
934 .controller_address = 0x400e0A00,
935 .flash_wait_states = 6, /* workaround silicon bug */
937 .size_bytes = 256 * 1024,
939 .sector_size = 16384,
953 .chipid_cidr = 0x29440960,
954 .name = "at91sam3n4b",
955 .total_flash_size = 256 * 1024,
956 .total_sram_size = 24 * 1024,
960 /* System boots at address 0x0 */
961 /* gpnvm[1] = selects boot code */
962 /* if gpnvm[1] == 0 */
963 /* boot is via "SAMBA" (rom) */
965 /* boot is via FLASH */
966 /* Selection is via gpnvm[2] */
969 /* NOTE: banks 0 & 1 switch places */
970 /* if gpnvm[2] == 0 */
971 /* Bank0 is the boot rom */
973 /* Bank1 is the boot rom */
982 .base_address = FLASH_BANK_BASE_N,
983 .controller_address = 0x400e0A00,
984 .flash_wait_states = 6, /* workaround silicon bug */
986 .size_bytes = 256 * 1024,
988 .sector_size = 16384,
1002 .chipid_cidr = 0x29340960,
1003 .name = "at91sam3n4a",
1004 .total_flash_size = 256 * 1024,
1005 .total_sram_size = 24 * 1024,
1009 /* System boots at address 0x0 */
1010 /* gpnvm[1] = selects boot code */
1011 /* if gpnvm[1] == 0 */
1012 /* boot is via "SAMBA" (rom) */
1014 /* boot is via FLASH */
1015 /* Selection is via gpnvm[2] */
1018 /* NOTE: banks 0 & 1 switch places */
1019 /* if gpnvm[2] == 0 */
1020 /* Bank0 is the boot rom */
1022 /* Bank1 is the boot rom */
1031 .base_address = FLASH_BANK_BASE_N,
1032 .controller_address = 0x400e0A00,
1033 .flash_wait_states = 6, /* workaround silicon bug */
1035 .size_bytes = 256 * 1024,
1037 .sector_size = 16384,
1051 .chipid_cidr = 0x29590760,
1052 .name = "at91sam3n2c",
1053 .total_flash_size = 128 * 1024,
1054 .total_sram_size = 16 * 1024,
1058 /* System boots at address 0x0 */
1059 /* gpnvm[1] = selects boot code */
1060 /* if gpnvm[1] == 0 */
1061 /* boot is via "SAMBA" (rom) */
1063 /* boot is via FLASH */
1064 /* Selection is via gpnvm[2] */
1067 /* NOTE: banks 0 & 1 switch places */
1068 /* if gpnvm[2] == 0 */
1069 /* Bank0 is the boot rom */
1071 /* Bank1 is the boot rom */
1080 .base_address = FLASH_BANK_BASE_N,
1081 .controller_address = 0x400e0A00,
1082 .flash_wait_states = 6, /* workaround silicon bug */
1084 .size_bytes = 128 * 1024,
1086 .sector_size = 16384,
1100 .chipid_cidr = 0x29490760,
1101 .name = "at91sam3n2b",
1102 .total_flash_size = 128 * 1024,
1103 .total_sram_size = 16 * 1024,
1107 /* System boots at address 0x0 */
1108 /* gpnvm[1] = selects boot code */
1109 /* if gpnvm[1] == 0 */
1110 /* boot is via "SAMBA" (rom) */
1112 /* boot is via FLASH */
1113 /* Selection is via gpnvm[2] */
1116 /* NOTE: banks 0 & 1 switch places */
1117 /* if gpnvm[2] == 0 */
1118 /* Bank0 is the boot rom */
1120 /* Bank1 is the boot rom */
1129 .base_address = FLASH_BANK_BASE_N,
1130 .controller_address = 0x400e0A00,
1131 .flash_wait_states = 6, /* workaround silicon bug */
1133 .size_bytes = 128 * 1024,
1135 .sector_size = 16384,
1149 .chipid_cidr = 0x29390760,
1150 .name = "at91sam3n2a",
1151 .total_flash_size = 128 * 1024,
1152 .total_sram_size = 16 * 1024,
1156 /* System boots at address 0x0 */
1157 /* gpnvm[1] = selects boot code */
1158 /* if gpnvm[1] == 0 */
1159 /* boot is via "SAMBA" (rom) */
1161 /* boot is via FLASH */
1162 /* Selection is via gpnvm[2] */
1165 /* NOTE: banks 0 & 1 switch places */
1166 /* if gpnvm[2] == 0 */
1167 /* Bank0 is the boot rom */
1169 /* Bank1 is the boot rom */
1178 .base_address = FLASH_BANK_BASE_N,
1179 .controller_address = 0x400e0A00,
1180 .flash_wait_states = 6, /* workaround silicon bug */
1182 .size_bytes = 128 * 1024,
1184 .sector_size = 16384,
1198 .chipid_cidr = 0x29580560,
1199 .name = "at91sam3n1c",
1200 .total_flash_size = 64 * 1024,
1201 .total_sram_size = 8 * 1024,
1205 /* System boots at address 0x0 */
1206 /* gpnvm[1] = selects boot code */
1207 /* if gpnvm[1] == 0 */
1208 /* boot is via "SAMBA" (rom) */
1210 /* boot is via FLASH */
1211 /* Selection is via gpnvm[2] */
1214 /* NOTE: banks 0 & 1 switch places */
1215 /* if gpnvm[2] == 0 */
1216 /* Bank0 is the boot rom */
1218 /* Bank1 is the boot rom */
1227 .base_address = FLASH_BANK_BASE_N,
1228 .controller_address = 0x400e0A00,
1229 .flash_wait_states = 6, /* workaround silicon bug */
1231 .size_bytes = 64 * 1024,
1233 .sector_size = 16384,
1247 .chipid_cidr = 0x29480560,
1248 .name = "at91sam3n1b",
1249 .total_flash_size = 64 * 1024,
1250 .total_sram_size = 8 * 1024,
1254 /* System boots at address 0x0 */
1255 /* gpnvm[1] = selects boot code */
1256 /* if gpnvm[1] == 0 */
1257 /* boot is via "SAMBA" (rom) */
1259 /* boot is via FLASH */
1260 /* Selection is via gpnvm[2] */
1263 /* NOTE: banks 0 & 1 switch places */
1264 /* if gpnvm[2] == 0 */
1265 /* Bank0 is the boot rom */
1267 /* Bank1 is the boot rom */
1276 .base_address = FLASH_BANK_BASE_N,
1277 .controller_address = 0x400e0A00,
1278 .flash_wait_states = 6, /* workaround silicon bug */
1280 .size_bytes = 64 * 1024,
1282 .sector_size = 16384,
1296 .chipid_cidr = 0x29380560,
1297 .name = "at91sam3n1a",
1298 .total_flash_size = 64 * 1024,
1299 .total_sram_size = 8 * 1024,
1303 /* System boots at address 0x0 */
1304 /* gpnvm[1] = selects boot code */
1305 /* if gpnvm[1] == 0 */
1306 /* boot is via "SAMBA" (rom) */
1308 /* boot is via FLASH */
1309 /* Selection is via gpnvm[2] */
1312 /* NOTE: banks 0 & 1 switch places */
1313 /* if gpnvm[2] == 0 */
1314 /* Bank0 is the boot rom */
1316 /* Bank1 is the boot rom */
1325 .base_address = FLASH_BANK_BASE_N,
1326 .controller_address = 0x400e0A00,
1327 .flash_wait_states = 6, /* workaround silicon bug */
1329 .size_bytes = 64 * 1024,
1331 .sector_size = 16384,
1344 /* Start at91sam3a series*/
1345 /* System boots at address 0x0 */
1346 /* gpnvm[1] = selects boot code */
1347 /* if gpnvm[1] == 0 */
1348 /* boot is via "SAMBA" (rom) */
1350 /* boot is via FLASH */
1351 /* Selection is via gpnvm[2] */
1354 /* NOTE: banks 0 & 1 switch places */
1355 /* if gpnvm[2] == 0 */
1356 /* Bank0 is the boot rom */
1358 /* Bank1 is the boot rom */
1362 .chipid_cidr = 0x283E0A60,
1363 .name = "at91sam3a8c",
1364 .total_flash_size = 512 * 1024,
1365 .total_sram_size = 96 * 1024,
1375 .base_address = FLASH_BANK0_BASE_AX,
1376 .controller_address = 0x400e0a00,
1377 .flash_wait_states = 6, /* workaround silicon bug */
1379 .size_bytes = 256 * 1024,
1381 .sector_size = 16384,
1390 .base_address = FLASH_BANK1_BASE_512K_AX,
1391 .controller_address = 0x400e0c00,
1392 .flash_wait_states = 6, /* workaround silicon bug */
1394 .size_bytes = 256 * 1024,
1396 .sector_size = 16384,
1403 .chipid_cidr = 0x283B0960,
1404 .name = "at91sam3a4c",
1405 .total_flash_size = 256 * 1024,
1406 .total_sram_size = 64 * 1024,
1416 .base_address = FLASH_BANK0_BASE_AX,
1417 .controller_address = 0x400e0a00,
1418 .flash_wait_states = 6, /* workaround silicon bug */
1420 .size_bytes = 128 * 1024,
1422 .sector_size = 16384,
1431 .base_address = FLASH_BANK1_BASE_256K_AX,
1432 .controller_address = 0x400e0c00,
1433 .flash_wait_states = 6, /* workaround silicon bug */
1435 .size_bytes = 128 * 1024,
1437 .sector_size = 16384,
1444 /* Start at91sam3x* series */
1445 /* System boots at address 0x0 */
1446 /* gpnvm[1] = selects boot code */
1447 /* if gpnvm[1] == 0 */
1448 /* boot is via "SAMBA" (rom) */
1450 /* boot is via FLASH */
1451 /* Selection is via gpnvm[2] */
1454 /* NOTE: banks 0 & 1 switch places */
1455 /* if gpnvm[2] == 0 */
1456 /* Bank0 is the boot rom */
1458 /* Bank1 is the boot rom */
1460 /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1462 .chipid_cidr = 0x286E0A20,
1463 .name = "at91sam3x8h - ES",
1464 .total_flash_size = 512 * 1024,
1465 .total_sram_size = 96 * 1024,
1475 .base_address = FLASH_BANK0_BASE_AX,
1476 .controller_address = 0x400e0a00,
1477 .flash_wait_states = 6, /* workaround silicon bug */
1479 .size_bytes = 256 * 1024,
1481 .sector_size = 16384,
1490 .base_address = FLASH_BANK1_BASE_512K_AX,
1491 .controller_address = 0x400e0c00,
1492 .flash_wait_states = 6, /* workaround silicon bug */
1494 .size_bytes = 256 * 1024,
1496 .sector_size = 16384,
1502 /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1504 .chipid_cidr = 0x286E0A60,
1505 .name = "at91sam3x8h",
1506 .total_flash_size = 512 * 1024,
1507 .total_sram_size = 96 * 1024,
1517 .base_address = FLASH_BANK0_BASE_AX,
1518 .controller_address = 0x400e0a00,
1519 .flash_wait_states = 6, /* workaround silicon bug */
1521 .size_bytes = 256 * 1024,
1523 .sector_size = 16384,
1532 .base_address = FLASH_BANK1_BASE_512K_AX,
1533 .controller_address = 0x400e0c00,
1534 .flash_wait_states = 6, /* workaround silicon bug */
1536 .size_bytes = 256 * 1024,
1538 .sector_size = 16384,
1545 .chipid_cidr = 0x285E0A60,
1546 .name = "at91sam3x8e",
1547 .total_flash_size = 512 * 1024,
1548 .total_sram_size = 96 * 1024,
1558 .base_address = FLASH_BANK0_BASE_AX,
1559 .controller_address = 0x400e0a00,
1560 .flash_wait_states = 6, /* workaround silicon bug */
1562 .size_bytes = 256 * 1024,
1564 .sector_size = 16384,
1573 .base_address = FLASH_BANK1_BASE_512K_AX,
1574 .controller_address = 0x400e0c00,
1575 .flash_wait_states = 6, /* workaround silicon bug */
1577 .size_bytes = 256 * 1024,
1579 .sector_size = 16384,
1586 .chipid_cidr = 0x284E0A60,
1587 .name = "at91sam3x8c",
1588 .total_flash_size = 512 * 1024,
1589 .total_sram_size = 96 * 1024,
1599 .base_address = FLASH_BANK0_BASE_AX,
1600 .controller_address = 0x400e0a00,
1601 .flash_wait_states = 6, /* workaround silicon bug */
1603 .size_bytes = 256 * 1024,
1605 .sector_size = 16384,
1614 .base_address = FLASH_BANK1_BASE_512K_AX ,
1615 .controller_address = 0x400e0c00,
1616 .flash_wait_states = 6, /* workaround silicon bug */
1618 .size_bytes = 256 * 1024,
1620 .sector_size = 16384,
1627 .chipid_cidr = 0x285B0960,
1628 .name = "at91sam3x4e",
1629 .total_flash_size = 256 * 1024,
1630 .total_sram_size = 64 * 1024,
1640 .base_address = FLASH_BANK0_BASE_AX,
1641 .controller_address = 0x400e0a00,
1642 .flash_wait_states = 6, /* workaround silicon bug */
1644 .size_bytes = 128 * 1024,
1646 .sector_size = 16384,
1655 .base_address = FLASH_BANK1_BASE_256K_AX,
1656 .controller_address = 0x400e0c00,
1657 .flash_wait_states = 6, /* workaround silicon bug */
1659 .size_bytes = 128 * 1024,
1661 .sector_size = 16384,
1668 .chipid_cidr = 0x284B0960,
1669 .name = "at91sam3x4c",
1670 .total_flash_size = 256 * 1024,
1671 .total_sram_size = 64 * 1024,
1681 .base_address = FLASH_BANK0_BASE_AX,
1682 .controller_address = 0x400e0a00,
1683 .flash_wait_states = 6, /* workaround silicon bug */
1685 .size_bytes = 128 * 1024,
1687 .sector_size = 16384,
1696 .base_address = FLASH_BANK1_BASE_256K_AX,
1697 .controller_address = 0x400e0c00,
1698 .flash_wait_states = 6, /* workaround silicon bug */
1700 .size_bytes = 128 * 1024,
1702 .sector_size = 16384,
1716 /***********************************************************************
1717 **********************************************************************
1718 **********************************************************************
1719 **********************************************************************
1720 **********************************************************************
1721 **********************************************************************/
1722 /* *ATMEL* style code - from the SAM3 driver code */
1725 * Get the current status of the EEFC and
1726 * the value of some status bits (LOCKE, PROGE).
1727 * @param pPrivate - info about the bank
1728 * @param v - result goes here
1730 static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
1733 r = target_read_u32(pPrivate->pChip->target,
1734 pPrivate->controller_address + offset_EFC_FSR,
1736 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1738 ((unsigned int)((*v >> 2) & 1)),
1739 ((unsigned int)((*v >> 1) & 1)),
1740 ((unsigned int)((*v >> 0) & 1)));
1746 * Get the result of the last executed command.
1747 * @param pPrivate - info about the bank
1748 * @param v - result goes here
1750 static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
1754 r = target_read_u32(pPrivate->pChip->target,
1755 pPrivate->controller_address + offset_EFC_FRR,
1759 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1763 static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
1764 unsigned command, unsigned argument)
1773 /* Check command & argument */
1776 case AT91C_EFC_FCMD_WP:
1777 case AT91C_EFC_FCMD_WPL:
1778 case AT91C_EFC_FCMD_EWP:
1779 case AT91C_EFC_FCMD_EWPL:
1780 /* case AT91C_EFC_FCMD_EPL: */
1781 /* case AT91C_EFC_FCMD_EPA: */
1782 case AT91C_EFC_FCMD_SLB:
1783 case AT91C_EFC_FCMD_CLB:
1784 n = (pPrivate->size_bytes / pPrivate->page_size);
1786 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1789 case AT91C_EFC_FCMD_SFB:
1790 case AT91C_EFC_FCMD_CFB:
1791 if (argument >= pPrivate->pChip->details.n_gpnvms) {
1792 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1793 pPrivate->pChip->details.n_gpnvms);
1797 case AT91C_EFC_FCMD_GETD:
1798 case AT91C_EFC_FCMD_EA:
1799 case AT91C_EFC_FCMD_GLB:
1800 case AT91C_EFC_FCMD_GFB:
1801 case AT91C_EFC_FCMD_STUI:
1802 case AT91C_EFC_FCMD_SPUI:
1804 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1807 LOG_ERROR("Unknown command %d", command);
1811 if (command == AT91C_EFC_FCMD_SPUI) {
1812 /* this is a very special situation. */
1813 /* Situation (1) - error/retry - see below */
1814 /* And we are being called recursively */
1815 /* Situation (2) - normal, finished reading unique id */
1817 /* it should be "ready" */
1818 EFC_GetStatus(pPrivate, &v);
1820 /* then it is ready */
1824 /* we have done this before */
1825 /* the controller is not responding. */
1826 LOG_ERROR("flash controller(%d) is not ready! Error",
1827 pPrivate->bank_number);
1831 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1832 pPrivate->bank_number);
1833 /* we do that by issuing the *STOP* command */
1834 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1835 /* above is recursive, and further recursion is blocked by */
1836 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1842 v = (0x5A << 24) | (argument << 8) | command;
1843 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1844 r = target_write_u32(pPrivate->pBank->target,
1845 pPrivate->controller_address + offset_EFC_FCR, v);
1847 LOG_DEBUG("Error Write failed");
1852 * Performs the given command and wait until its completion (or an error).
1853 * @param pPrivate - info about the bank
1854 * @param command - Command to perform.
1855 * @param argument - Optional command argument.
1856 * @param status - put command status bits here
1858 static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
1866 long long ms_now, ms_end;
1872 r = EFC_StartCommand(pPrivate, command, argument);
1876 ms_end = 500 + timeval_ms();
1879 r = EFC_GetStatus(pPrivate, &v);
1882 ms_now = timeval_ms();
1883 if (ms_now > ms_end) {
1885 LOG_ERROR("Command timeout");
1888 } while ((v & 1) == 0);
1892 *status = (v & 0x6);
1898 * Read the unique ID.
1899 * @param pPrivate - info about the bank
1900 * The unique ID is stored in the 'pPrivate' structure.
1902 static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
1908 pPrivate->pChip->cfg.unique_id[0] = 0;
1909 pPrivate->pChip->cfg.unique_id[1] = 0;
1910 pPrivate->pChip->cfg.unique_id[2] = 0;
1911 pPrivate->pChip->cfg.unique_id[3] = 0;
1914 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1918 for (x = 0; x < 4; x++) {
1919 r = target_read_u32(pPrivate->pChip->target,
1920 pPrivate->pBank->base + (x * 4),
1924 pPrivate->pChip->cfg.unique_id[x] = v;
1927 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1928 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1930 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1931 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1932 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1933 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1939 * Erases the entire flash.
1940 * @param pPrivate - the info about the bank.
1942 static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
1945 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1949 * Gets current GPNVM state.
1950 * @param pPrivate - info about the bank.
1951 * @param gpnvm - GPNVM bit index.
1952 * @param puthere - result stored here.
1954 /* ------------------------------------------------------------------------------ */
1955 static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1961 if (pPrivate->bank_number != 0) {
1962 LOG_ERROR("GPNVM only works with Bank0");
1966 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1967 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1968 gpnvm, pPrivate->pChip->details.n_gpnvms);
1972 /* Get GPNVMs status */
1973 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1974 if (r != ERROR_OK) {
1975 LOG_ERROR("Failed");
1979 r = EFC_GetResult(pPrivate, &v);
1982 /* Check if GPNVM is set */
1983 /* get the bit and make it a 0/1 */
1984 *puthere = (v >> gpnvm) & 1;
1991 * Clears the selected GPNVM bit.
1992 * @param pPrivate info about the bank
1993 * @param gpnvm GPNVM index.
1994 * @returns 0 if successful; otherwise returns an error code.
1996 static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2002 if (pPrivate->bank_number != 0) {
2003 LOG_ERROR("GPNVM only works with Bank0");
2007 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2008 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2009 gpnvm, pPrivate->pChip->details.n_gpnvms);
2013 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2014 if (r != ERROR_OK) {
2015 LOG_DEBUG("Failed: %d", r);
2018 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
2019 LOG_DEBUG("End: %d", r);
2024 * Sets the selected GPNVM bit.
2025 * @param pPrivate info about the bank
2026 * @param gpnvm GPNVM index.
2028 static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2033 if (pPrivate->bank_number != 0) {
2034 LOG_ERROR("GPNVM only works with Bank0");
2038 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2039 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2040 gpnvm, pPrivate->pChip->details.n_gpnvms);
2044 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2052 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2058 * Returns a bit field (at most 64) of locked regions within a page.
2059 * @param pPrivate info about the bank
2060 * @param v where to store locked bits
2062 static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
2066 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
2068 r = EFC_GetResult(pPrivate, v);
2069 LOG_DEBUG("End: %d", r);
2074 * Unlocks all the regions in the given address range.
2075 * @param pPrivate info about the bank
2076 * @param start_sector first sector to unlock
2077 * @param end_sector last (inclusive) to unlock
2080 static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
2081 unsigned start_sector,
2082 unsigned end_sector)
2087 uint32_t pages_per_sector;
2089 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2091 /* Unlock all pages */
2092 while (start_sector <= end_sector) {
2093 pg = start_sector * pages_per_sector;
2095 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
2106 * @param pPrivate - info about the bank
2107 * @param start_sector - first sector to lock
2108 * @param end_sector - last sector (inclusive) to lock
2110 static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
2111 unsigned start_sector,
2112 unsigned end_sector)
2116 uint32_t pages_per_sector;
2119 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2121 /* Lock all pages */
2122 while (start_sector <= end_sector) {
2123 pg = start_sector * pages_per_sector;
2125 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
2133 /****** END SAM3 CODE ********/
2135 /* begin helpful debug code */
2136 /* print the fieldname, the field value, in dec & hex, and return field value */
2137 static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
2138 const char *regname,
2147 /* extract the field */
2149 v = v & ((1 << width)-1);
2158 /* show the basics */
2159 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
2160 REG_NAME_WIDTH, regname,
2166 static const char _unknown[] = "unknown";
2167 static const char *const eproc_names[] = {
2171 "cortex-m3", /* 3 */
2173 "arm926ejs", /* 5 */
2186 #define nvpsize2 nvpsize /* these two tables are identical */
2187 static const char *const nvpsize[] = {
2190 "16K bytes", /* 2 */
2191 "32K bytes", /* 3 */
2193 "64K bytes", /* 5 */
2195 "128K bytes", /* 7 */
2197 "256K bytes", /* 9 */
2198 "512K bytes", /* 10 */
2200 "1024K bytes", /* 12 */
2202 "2048K bytes", /* 14 */
2206 static const char *const sramsize[] = {
2207 "48K Bytes", /* 0 */
2211 "112K Bytes", /* 4 */
2213 "80K Bytes", /* 6 */
2214 "160K Bytes", /* 7 */
2216 "16K Bytes", /* 9 */
2217 "32K Bytes", /* 10 */
2218 "64K Bytes", /* 11 */
2219 "128K Bytes", /* 12 */
2220 "256K Bytes", /* 13 */
2221 "96K Bytes", /* 14 */
2222 "512K Bytes", /* 15 */
2226 static const struct archnames { unsigned value; const char *name; } archnames[] = {
2227 { 0x19, "AT91SAM9xx Series" },
2228 { 0x29, "AT91SAM9XExx Series" },
2229 { 0x34, "AT91x34 Series" },
2230 { 0x37, "CAP7 Series" },
2231 { 0x39, "CAP9 Series" },
2232 { 0x3B, "CAP11 Series" },
2233 { 0x40, "AT91x40 Series" },
2234 { 0x42, "AT91x42 Series" },
2235 { 0x55, "AT91x55 Series" },
2236 { 0x60, "AT91SAM7Axx Series" },
2237 { 0x61, "AT91SAM7AQxx Series" },
2238 { 0x63, "AT91x63 Series" },
2239 { 0x70, "AT91SAM7Sxx Series" },
2240 { 0x71, "AT91SAM7XCxx Series" },
2241 { 0x72, "AT91SAM7SExx Series" },
2242 { 0x73, "AT91SAM7Lxx Series" },
2243 { 0x75, "AT91SAM7Xxx Series" },
2244 { 0x76, "AT91SAM7SLxx Series" },
2245 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2246 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2247 { 0x83, "ATSAM3AxC Series (100-pin version)" },
2248 { 0x84, "ATSAM3XxC Series (100-pin version)" },
2249 { 0x85, "ATSAM3XxE Series (144-pin version)" },
2250 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2251 { 0x88, "ATSAM3SxA Series (48-pin version)" },
2252 { 0x89, "ATSAM3SxB Series (64-pin version)" },
2253 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2254 { 0x92, "AT91x92 Series" },
2255 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2256 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2257 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2258 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2259 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2260 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2261 { 0xA5, "ATSAM5A" },
2262 { 0xF0, "AT75Cxx Series" },
2266 static const char *const nvptype[] = {
2268 "romless or onchip flash", /* 1 */
2269 "embedded flash memory",/* 2 */
2270 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2271 "sram emulating flash", /* 4 */
2277 static const char *_yes_or_no(uint32_t v)
2285 static const char *const _rc_freq[] = {
2286 "4 MHz", "8 MHz", "12 MHz", "reserved"
2289 static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
2294 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2295 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2296 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2297 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2298 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2299 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2300 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2301 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2303 pChip->cfg.rc_freq = 0;
2307 pChip->cfg.rc_freq = 0;
2310 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2313 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2316 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2321 v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2322 LOG_USER("(startup clks, time= %f uSecs)",
2323 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2324 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2325 LOG_USER("(mainosc source: %s)",
2326 v ? "external xtal" : "internal RC");
2328 v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2329 LOG_USER("(clock failure enabled: %s)",
2333 static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
2339 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2342 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2343 LOG_USER("%s", eproc_names[v]);
2345 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2346 LOG_USER("%s", nvpsize[v]);
2348 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2349 LOG_USER("%s", nvpsize2[v]);
2351 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2352 LOG_USER("%s", sramsize[v]);
2354 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2356 for (x = 0; archnames[x].name; x++) {
2357 if (v == archnames[x].value) {
2358 cp = archnames[x].name;
2365 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2366 LOG_USER("%s", nvptype[v]);
2368 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2369 LOG_USER("(exists: %s)", _yes_or_no(v));
2372 static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
2376 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2377 LOG_USER("(main ready: %s)", _yes_or_no(v));
2379 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2381 v = (v * pChip->cfg.slow_freq) / 16;
2382 pChip->cfg.mainosc_freq = v;
2384 LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
2386 pChip->cfg.slow_freq / 1000,
2387 pChip->cfg.slow_freq % 1000);
2390 static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
2392 uint32_t mula, diva;
2394 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2396 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2398 pChip->cfg.plla_freq = 0;
2400 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2402 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2403 else if (diva == 1) {
2404 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
2405 LOG_USER("\tPLLA Freq: %3.03f MHz",
2406 _tomhz(pChip->cfg.plla_freq));
2410 static void sam3_explain_mckr(struct sam3_chip *pChip)
2412 uint32_t css, pres, fin = 0;
2414 const char *cp = NULL;
2416 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2419 fin = pChip->cfg.slow_freq;
2423 fin = pChip->cfg.mainosc_freq;
2427 fin = pChip->cfg.plla_freq;
2431 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2432 fin = 480 * 1000 * 1000;
2436 cp = "upll (*ERROR* UPLL is disabled)";
2444 LOG_USER("%s (%3.03f Mhz)",
2447 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2448 switch (pres & 0x07) {
2451 cp = "selected clock";
2485 LOG_USER("(%s)", cp);
2487 /* sam3 has a *SINGLE* clock - */
2488 /* other at91 series parts have divisors for these. */
2489 pChip->cfg.cpu_freq = fin;
2490 pChip->cfg.mclk_freq = fin;
2491 pChip->cfg.fclk_freq = fin;
2492 LOG_USER("\t\tResult CPU Freq: %3.03f",
2497 static struct sam3_chip *target2sam3(struct target *pTarget)
2499 struct sam3_chip *pChip;
2501 if (pTarget == NULL)
2504 pChip = all_sam3_chips;
2506 if (pChip->target == pTarget)
2507 break; /* return below */
2509 pChip = pChip->next;
2515 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
2517 /* this function exists to help */
2518 /* keep funky offsetof() errors */
2519 /* and casting from causing bugs */
2521 /* By using prototypes - we can detect what would */
2522 /* be casting errors. */
2524 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2528 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2530 NAME), # NAME, FUNC }
2531 static const struct sam3_reg_list sam3_all_regs[] = {
2532 SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2533 SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2534 SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2535 SAM3_ENTRY(CKGR_UCKR, NULL),
2536 SAM3_ENTRY(PMC_FSMR, NULL),
2537 SAM3_ENTRY(PMC_FSPR, NULL),
2538 SAM3_ENTRY(PMC_IMR, NULL),
2539 SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2540 SAM3_ENTRY(PMC_PCK0, NULL),
2541 SAM3_ENTRY(PMC_PCK1, NULL),
2542 SAM3_ENTRY(PMC_PCK2, NULL),
2543 SAM3_ENTRY(PMC_PCSR, NULL),
2544 SAM3_ENTRY(PMC_SCSR, NULL),
2545 SAM3_ENTRY(PMC_SR, NULL),
2546 SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2547 SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2548 SAM3_ENTRY(CHIPID_EXID, NULL),
2549 SAM3_ENTRY(CHIPID_EXID2, NULL),
2550 /* TERMINATE THE LIST */
2555 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2557 return (struct sam3_bank_private *)(bank->driver_priv);
2561 * Given a pointer to where it goes in the structure,
2562 * determine the register name, address from the all registers table.
2564 static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
2566 const struct sam3_reg_list *pReg;
2568 pReg = &(sam3_all_regs[0]);
2569 while (pReg->name) {
2570 uint32_t *pPossible;
2572 /* calculate where this one go.. */
2573 /* it is "possibly" this register. */
2575 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2577 /* well? Is it this register */
2578 if (pPossible == goes_here) {
2586 /* This is *TOTAL*PANIC* - we are totally screwed. */
2587 LOG_ERROR("INVALID SAM3 REGISTER");
2591 static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
2593 const struct sam3_reg_list *pReg;
2596 pReg = sam3_GetReg(pChip, goes_here);
2600 r = target_read_u32(pChip->target, pReg->address, goes_here);
2601 if (r != ERROR_OK) {
2602 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2603 pReg->name, (unsigned)(pReg->address), r);
2608 static int sam3_ReadAllRegs(struct sam3_chip *pChip)
2611 const struct sam3_reg_list *pReg;
2613 pReg = &(sam3_all_regs[0]);
2614 while (pReg->name) {
2615 r = sam3_ReadThisReg(pChip,
2616 sam3_get_reg_ptr(&(pChip->cfg), pReg));
2617 if (r != ERROR_OK) {
2618 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
2619 pReg->name, ((unsigned)(pReg->address)), r);
2625 /* Chip identification register
2627 * Unfortunately, the chip identification register is not at
2628 * a constant address across all of the SAM3 series'. As a
2629 * consequence, a simple heuristic is used to find where it's
2632 * If the contents at the first address is zero, then we know
2633 * that the second address is where the chip id register is.
2634 * We can deduce this because for those SAM's that have the
2635 * chip id @ 0x400e0940, the first address, 0x400e0740, is
2636 * located in the memory map of the Power Management Controller
2637 * (PMC). Furthermore, the address is not used by the PMC.
2638 * So when read, the memory controller returns zero.*/
2639 if (pChip->cfg.CHIPID_CIDR == 0) {
2640 /*Put the correct CIDR and EXID values in the pChip structure */
2641 pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
2642 pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
2647 static int sam3_GetInfo(struct sam3_chip *pChip)
2649 const struct sam3_reg_list *pReg;
2652 pReg = &(sam3_all_regs[0]);
2653 while (pReg->name) {
2654 /* display all regs */
2655 LOG_DEBUG("Start: %s", pReg->name);
2656 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
2657 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2662 if (pReg->explain_func)
2663 (*(pReg->explain_func))(pChip);
2664 LOG_DEBUG("End: %s", pReg->name);
2667 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2668 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2669 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2670 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2671 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2673 LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2674 pChip->cfg.unique_id[0],
2675 pChip->cfg.unique_id[1],
2676 pChip->cfg.unique_id[2],
2677 pChip->cfg.unique_id[3]);
2682 static int sam3_erase_check(struct flash_bank *bank)
2687 if (bank->target->state != TARGET_HALTED) {
2688 LOG_ERROR("Target not halted");
2689 return ERROR_TARGET_NOT_HALTED;
2691 if (0 == bank->num_sectors) {
2692 LOG_ERROR("Target: not supported/not probed");
2696 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2697 for (x = 0; x < bank->num_sectors; x++)
2698 bank->sectors[x].is_erased = 1;
2704 static int sam3_protect_check(struct flash_bank *bank)
2709 struct sam3_bank_private *pPrivate;
2712 if (bank->target->state != TARGET_HALTED) {
2713 LOG_ERROR("Target not halted");
2714 return ERROR_TARGET_NOT_HALTED;
2717 pPrivate = get_sam3_bank_private(bank);
2719 LOG_ERROR("no private for this bank?");
2722 if (!(pPrivate->probed))
2723 return ERROR_FLASH_BANK_NOT_PROBED;
2725 r = FLASHD_GetLockBits(pPrivate, &v);
2726 if (r != ERROR_OK) {
2727 LOG_DEBUG("Failed: %d", r);
2731 for (x = 0; x < pPrivate->nsectors; x++)
2732 bank->sectors[x].is_protected = (!!(v & (1 << x)));
2737 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
2739 struct sam3_chip *pChip;
2741 pChip = all_sam3_chips;
2743 /* is this an existing chip? */
2745 if (pChip->target == bank->target)
2747 pChip = pChip->next;
2751 /* this is a *NEW* chip */
2752 pChip = calloc(1, sizeof(struct sam3_chip));
2754 LOG_ERROR("NO RAM!");
2757 pChip->target = bank->target;
2758 /* insert at head */
2759 pChip->next = all_sam3_chips;
2760 all_sam3_chips = pChip;
2761 pChip->target = bank->target;
2762 /* assumption is this runs at 32khz */
2763 pChip->cfg.slow_freq = 32768;
2767 switch (bank->base) {
2769 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
2770 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
2771 "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
2772 ((unsigned int)(bank->base)),
2773 ((unsigned int)(FLASH_BANK0_BASE_U)),
2774 ((unsigned int)(FLASH_BANK1_BASE_U)),
2775 ((unsigned int)(FLASH_BANK_BASE_S)),
2776 ((unsigned int)(FLASH_BANK_BASE_N)),
2777 ((unsigned int)(FLASH_BANK0_BASE_AX)),
2778 ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
2779 ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
2783 /* at91sam3s and at91sam3n series only has bank 0*/
2784 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
2785 case FLASH_BANK_BASE_S:
2786 case FLASH_BANK0_BASE_U:
2787 bank->driver_priv = &(pChip->details.bank[0]);
2788 bank->bank_number = 0;
2789 pChip->details.bank[0].pChip = pChip;
2790 pChip->details.bank[0].pBank = bank;
2793 /* Bank 1 of at91sam3u or at91sam3ax series */
2794 case FLASH_BANK1_BASE_U:
2795 case FLASH_BANK1_BASE_256K_AX:
2796 case FLASH_BANK1_BASE_512K_AX:
2797 bank->driver_priv = &(pChip->details.bank[1]);
2798 bank->bank_number = 1;
2799 pChip->details.bank[1].pChip = pChip;
2800 pChip->details.bank[1].pBank = bank;
2804 /* we initialize after probing. */
2808 static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
2810 const struct sam3_chip_details *pDetails;
2811 struct sam3_chip *pChip;
2812 struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
2816 pDetails = all_sam3_details;
2817 while (pDetails->name) {
2818 /* Compare cidr without version bits */
2819 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2824 if (pDetails->name == NULL) {
2825 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2826 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2827 /* Help the victim, print details about the chip */
2828 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
2829 pPrivate->pChip->cfg.CHIPID_CIDR);
2830 sam3_explain_chipid_cidr(pPrivate->pChip);
2834 /* DANGER: THERE ARE DRAGONS HERE */
2836 /* get our pChip - it is going */
2837 /* to be over-written shortly */
2838 pChip = pPrivate->pChip;
2840 /* Note that, in reality: */
2842 /* pPrivate = &(pChip->details.bank[0]) */
2843 /* or pPrivate = &(pChip->details.bank[1]) */
2846 /* save the "bank" pointers */
2847 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
2848 saved_banks[x] = pChip->details.bank[x].pBank;
2850 /* Overwrite the "details" structure. */
2851 memcpy(&(pPrivate->pChip->details),
2853 sizeof(pPrivate->pChip->details));
2855 /* now fix the ghosted pointers */
2856 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2857 pChip->details.bank[x].pChip = pChip;
2858 pChip->details.bank[x].pBank = saved_banks[x];
2861 /* update the *BANK*SIZE* */
2867 static int _sam3_probe(struct flash_bank *bank, int noise)
2871 struct sam3_bank_private *pPrivate;
2874 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2875 if (bank->target->state != TARGET_HALTED) {
2876 LOG_ERROR("Target not halted");
2877 return ERROR_TARGET_NOT_HALTED;
2880 pPrivate = get_sam3_bank_private(bank);
2882 LOG_ERROR("Invalid/unknown bank number");
2886 r = sam3_ReadAllRegs(pPrivate->pChip);
2891 if (pPrivate->pChip->probed)
2892 r = sam3_GetInfo(pPrivate->pChip);
2894 r = sam3_GetDetails(pPrivate);
2898 /* update the flash bank size */
2899 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2900 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2901 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2906 if (bank->sectors == NULL) {
2907 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2908 if (bank->sectors == NULL) {
2909 LOG_ERROR("No memory!");
2912 bank->num_sectors = pPrivate->nsectors;
2914 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2915 bank->sectors[x].size = pPrivate->sector_size;
2916 bank->sectors[x].offset = x * (pPrivate->sector_size);
2917 /* mark as unknown */
2918 bank->sectors[x].is_erased = -1;
2919 bank->sectors[x].is_protected = -1;
2923 pPrivate->probed = 1;
2925 r = sam3_protect_check(bank);
2929 LOG_DEBUG("Bank = %d, nbanks = %d",
2930 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2931 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2932 /* read unique id, */
2933 /* it appears to be associated with the *last* flash bank. */
2934 FLASHD_ReadUniqueID(pPrivate);
2940 static int sam3_probe(struct flash_bank *bank)
2942 return _sam3_probe(bank, 1);
2945 static int sam3_auto_probe(struct flash_bank *bank)
2947 return _sam3_probe(bank, 0);
2950 static int sam3_erase(struct flash_bank *bank, int first, int last)
2952 struct sam3_bank_private *pPrivate;
2956 if (bank->target->state != TARGET_HALTED) {
2957 LOG_ERROR("Target not halted");
2958 return ERROR_TARGET_NOT_HALTED;
2961 r = sam3_auto_probe(bank);
2962 if (r != ERROR_OK) {
2963 LOG_DEBUG("Here,r=%d", r);
2967 pPrivate = get_sam3_bank_private(bank);
2968 if (!(pPrivate->probed))
2969 return ERROR_FLASH_BANK_NOT_PROBED;
2971 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
2974 return FLASHD_EraseEntireBank(pPrivate);
2976 LOG_INFO("sam3 auto-erases while programing (request ignored)");
2980 static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
2982 struct sam3_bank_private *pPrivate;
2986 if (bank->target->state != TARGET_HALTED) {
2987 LOG_ERROR("Target not halted");
2988 return ERROR_TARGET_NOT_HALTED;
2991 pPrivate = get_sam3_bank_private(bank);
2992 if (!(pPrivate->probed))
2993 return ERROR_FLASH_BANK_NOT_PROBED;
2996 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2998 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2999 LOG_DEBUG("End: r=%d", r);
3005 static int sam3_info(struct flash_bank *bank, char *buf, int buf_size)
3007 if (bank->target->state != TARGET_HALTED) {
3008 LOG_ERROR("Target not halted");
3009 return ERROR_TARGET_NOT_HALTED;
3015 static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3020 adr = pagenum * pPrivate->page_size;
3021 adr += adr + pPrivate->base_address;
3023 r = target_read_memory(pPrivate->pChip->target,
3025 4, /* THIS*MUST*BE* in 32bit values */
3026 pPrivate->page_size / 4,
3029 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3030 (unsigned int)(adr));
3034 /* The code below is basically this: */
3036 /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
3038 /* Only the *CPU* can write to the flash buffer. */
3039 /* the DAP cannot... so - we download this 28byte thing */
3040 /* Run the algorithm - (below) */
3041 /* to program the device */
3043 /* ======================================== */
3044 /* #include <stdint.h> */
3047 /* uint32_t *dst; */
3048 /* const uint32_t *src; */
3050 /* volatile uint32_t *base; */
3055 /* uint32_t sam3_function(struct foo *p) */
3057 /* volatile uint32_t *v; */
3059 /* const uint32_t *s; */
3074 /* v[ 1 ] = p->cmd; */
3077 /* } while (!(r&1)) */
3081 /* ======================================== */
3083 static const uint8_t
3084 sam3_page_write_opcodes[] = {
3085 /* 24 0000 0446 mov r4, r0 */
3087 /* 25 0002 6168 ldr r1, [r4, #4] */
3089 /* 26 0004 0068 ldr r0, [r0, #0] */
3091 /* 27 0006 A268 ldr r2, [r4, #8] */
3093 /* 28 @ lr needed for prologue */
3095 /* 30 0008 51F8043B ldr r3, [r1], #4 */
3096 0x51, 0xf8, 0x04, 0x3b,
3097 /* 31 000c 12F1FF32 adds r2, r2, #-1 */
3098 0x12, 0xf1, 0xff, 0x32,
3099 /* 32 0010 40F8043B str r3, [r0], #4 */
3100 0x40, 0xf8, 0x04, 0x3b,
3101 /* 33 0014 F8D1 bne .L2 */
3103 /* 34 0016 E268 ldr r2, [r4, #12] */
3105 /* 35 0018 2369 ldr r3, [r4, #16] */
3107 /* 36 001a 5360 str r3, [r2, #4] */
3109 /* 37 001c 0832 adds r2, r2, #8 */
3112 /* 39 001e 1068 ldr r0, [r2, #0] */
3114 /* 40 0020 10F0010F tst r0, #1 */
3115 0x10, 0xf0, 0x01, 0x0f,
3116 /* 41 0024 FBD0 beq .L4 */
3118 0x00, 0xBE /* bkpt #0 */
3121 static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3125 uint32_t fmr; /* EEFC Flash Mode Register */
3128 adr = pagenum * pPrivate->page_size;
3129 adr += (adr + pPrivate->base_address);
3131 /* Get flash mode register value */
3132 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
3134 LOG_DEBUG("Error Read failed: read flash mode register");
3136 /* Clear flash wait state field */
3139 /* set FWS (flash wait states) field in the FMR (flash mode register) */
3140 fmr |= (pPrivate->flash_wait_states << 8);
3142 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
3143 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
3145 LOG_DEBUG("Error Write failed: set flash mode register");
3147 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
3148 r = target_write_memory(pPrivate->pChip->target,
3150 4, /* THIS*MUST*BE* in 32bit values */
3151 pPrivate->page_size / 4,
3153 if (r != ERROR_OK) {
3154 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3155 (unsigned int)(adr));
3159 r = EFC_PerformCommand(pPrivate,
3160 /* send Erase & Write Page */
3166 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3167 (unsigned int)(adr));
3168 if (status & (1 << 2)) {
3169 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
3172 if (status & (1 << 1)) {
3173 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
3179 static int sam3_write(struct flash_bank *bank,
3188 unsigned page_offset;
3189 struct sam3_bank_private *pPrivate;
3190 uint8_t *pagebuffer;
3192 /* incase we bail further below, set this to null */
3195 /* ignore dumb requests */
3201 if (bank->target->state != TARGET_HALTED) {
3202 LOG_ERROR("Target not halted");
3203 r = ERROR_TARGET_NOT_HALTED;
3207 pPrivate = get_sam3_bank_private(bank);
3208 if (!(pPrivate->probed)) {
3209 r = ERROR_FLASH_BANK_NOT_PROBED;
3213 if ((offset + count) > pPrivate->size_bytes) {
3214 LOG_ERROR("Flash write error - past end of bank");
3215 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3216 (unsigned int)(offset),
3217 (unsigned int)(count),
3218 (unsigned int)(pPrivate->size_bytes));
3223 pagebuffer = malloc(pPrivate->page_size);
3225 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
3230 /* what page do we start & end in? */
3231 page_cur = offset / pPrivate->page_size;
3232 page_end = (offset + count - 1) / pPrivate->page_size;
3234 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
3235 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
3237 /* Special case: all one page */
3240 /* (1) non-aligned start */
3241 /* (2) body pages */
3242 /* (3) non-aligned end. */
3244 /* Handle special case - all one page. */
3245 if (page_cur == page_end) {
3246 LOG_DEBUG("Special case, all in one page");
3247 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3251 page_offset = (offset & (pPrivate->page_size-1));
3252 memcpy(pagebuffer + page_offset,
3256 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3263 /* non-aligned start */
3264 page_offset = offset & (pPrivate->page_size - 1);
3266 LOG_DEBUG("Not-Aligned start");
3267 /* read the partial */
3268 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3272 /* over-write with new data */
3273 n = (pPrivate->page_size - page_offset);
3274 memcpy(pagebuffer + page_offset,
3278 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3288 /* By checking that offset is correct here, we also
3289 fix a clang warning */
3290 assert(offset % pPrivate->page_size == 0);
3292 /* intermediate large pages */
3293 /* also - the final *terminal* */
3294 /* if that terminal page is a full page */
3295 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3296 (int)page_cur, (int)page_end, (unsigned int)(count));
3298 while ((page_cur < page_end) &&
3299 (count >= pPrivate->page_size)) {
3300 r = sam3_page_write(pPrivate, page_cur, buffer);
3303 count -= pPrivate->page_size;
3304 buffer += pPrivate->page_size;
3308 /* terminal partial page? */
3310 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3311 /* we have a partial page */
3312 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3315 /* data goes at start */
3316 memcpy(pagebuffer, buffer, count);
3317 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3329 COMMAND_HANDLER(sam3_handle_info_command)
3331 struct sam3_chip *pChip;
3332 pChip = get_current_sam3(CMD_CTX);
3339 /* bank0 must exist before we can do anything */
3340 if (pChip->details.bank[0].pBank == NULL) {
3343 command_print(CMD_CTX,
3344 "Please define bank %d via command: flash bank %s ... ",
3346 at91sam3_flash.name);
3350 /* if bank 0 is not probed, then probe it */
3351 if (!(pChip->details.bank[0].probed)) {
3352 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3356 /* above guarantees the "chip details" structure is valid */
3357 /* and thus, bank private areas are valid */
3358 /* and we have a SAM3 chip, what a concept! */
3360 /* auto-probe other banks, 0 done above */
3361 for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
3362 /* skip banks not present */
3363 if (!(pChip->details.bank[x].present))
3366 if (pChip->details.bank[x].pBank == NULL)
3369 if (pChip->details.bank[x].probed)
3372 r = sam3_auto_probe(pChip->details.bank[x].pBank);
3377 r = sam3_GetInfo(pChip);
3378 if (r != ERROR_OK) {
3379 LOG_DEBUG("Sam3Info, Failed %d", r);
3386 COMMAND_HANDLER(sam3_handle_gpnvm_command)
3390 struct sam3_chip *pChip;
3392 pChip = get_current_sam3(CMD_CTX);
3396 if (pChip->target->state != TARGET_HALTED) {
3397 LOG_ERROR("sam3 - target not halted");
3398 return ERROR_TARGET_NOT_HALTED;
3401 if (pChip->details.bank[0].pBank == NULL) {
3402 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
3403 at91sam3_flash.name);
3406 if (!pChip->details.bank[0].probed) {
3407 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3414 return ERROR_COMMAND_SYNTAX_ERROR;
3423 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3427 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3433 if (0 == strcmp("show", CMD_ARGV[0])) {
3437 for (x = 0; x < pChip->details.n_gpnvms; x++) {
3438 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3441 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
3445 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3446 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3447 command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
3450 command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
3451 return ERROR_COMMAND_SYNTAX_ERROR;
3456 command_print(CMD_CTX, "Missing GPNVM number");
3457 return ERROR_COMMAND_SYNTAX_ERROR;
3460 if (0 == strcmp("set", CMD_ARGV[0]))
3461 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3462 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3463 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
3464 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3466 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3467 r = ERROR_COMMAND_SYNTAX_ERROR;
3472 COMMAND_HANDLER(sam3_handle_slowclk_command)
3474 struct sam3_chip *pChip;
3476 pChip = get_current_sam3(CMD_CTX);
3488 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3490 /* absurd slow clock of 200Khz? */
3491 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3492 return ERROR_COMMAND_SYNTAX_ERROR;
3494 pChip->cfg.slow_freq = v;
3499 command_print(CMD_CTX, "Too many parameters");
3500 return ERROR_COMMAND_SYNTAX_ERROR;
3503 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
3504 (int)(pChip->cfg.slow_freq / 1000),
3505 (int)(pChip->cfg.slow_freq % 1000));
3509 static const struct command_registration at91sam3_exec_command_handlers[] = {
3512 .handler = sam3_handle_gpnvm_command,
3513 .mode = COMMAND_EXEC,
3514 .usage = "[('clr'|'set'|'show') bitnum]",
3515 .help = "Without arguments, shows all bits in the gpnvm "
3516 "register. Otherwise, clears, sets, or shows one "
3517 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3521 .handler = sam3_handle_info_command,
3522 .mode = COMMAND_EXEC,
3523 .help = "Print information about the current at91sam3 chip"
3524 "and its flash configuration.",
3528 .handler = sam3_handle_slowclk_command,
3529 .mode = COMMAND_EXEC,
3530 .usage = "[clock_hz]",
3531 .help = "Display or set the slowclock frequency "
3532 "(default 32768 Hz).",
3534 COMMAND_REGISTRATION_DONE
3536 static const struct command_registration at91sam3_command_handlers[] = {
3539 .mode = COMMAND_ANY,
3540 .help = "at91sam3 flash command group",
3542 .chain = at91sam3_exec_command_handlers,
3544 COMMAND_REGISTRATION_DONE
3547 struct flash_driver at91sam3_flash = {
3549 .commands = at91sam3_command_handlers,
3550 .flash_bank_command = sam3_flash_bank_command,
3551 .erase = sam3_erase,
3552 .protect = sam3_protect,
3553 .write = sam3_write,
3554 .read = default_flash_read,
3555 .probe = sam3_probe,
3556 .auto_probe = sam3_auto_probe,
3557 .erase_check = sam3_erase_check,
3558 .protect_check = sam3_protect_check,