1 /******************************************************************************
5 * @brief Ambiq Micro flash driver.
7 *****************************************************************************/
9 /******************************************************************************
10 * Copyright (c) 2015, David Racine <dracine at ambiqmicro.com>
12 * Copyright (c) 2016, Rick Foos <rfoos at solengtech.com>
14 * Copyright (c) 2015-2016, Ambiq Micro, Inc.
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
28 * 3. Neither the name of the copyright holder nor the names of its
29 * contributors may be used to endorse or promote products derived from this
30 * software without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
36 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
37 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
38 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
39 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
40 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
41 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 * POSSIBILITY OF SUCH DAMAGE.
44 *****************************************************************************/
49 #include "jtag/interface.h"
51 #include "target/algorithm.h"
52 #include "target/armv7m.h"
53 #include "target/cortex_m.h"
55 /** Check error, log error. */
56 #define CHECK_STATUS(rc, msg) { \
57 if (rc != ERROR_OK) { \
58 LOG_ERROR("status(%d):%s\n", rc, msg); } }
61 * Address and Key defines.
63 #define PROGRAM_KEY (0x12344321)
64 #define OTP_PROGRAM_KEY (0x87655678)
66 #define FLASH_PROGRAM_MAIN_FROM_SRAM 0x0800005d
67 #define FLASH_PROGRAM_OTP_FROM_SRAM 0x08000061
68 #define FLASH_ERASE_LIST_MAIN_PAGES_FROM_SRAM 0x08000065
69 #define FLASH_MASS_ERASE_MAIN_PAGES_FROM_SRAM 0x08000069
72 static const uint32_t apollo_flash_size[] = {
82 static const uint32_t apollo_sram_size[] = {
92 struct ambiqmicro_flash_bank {
93 /* chip id register */
97 const char *target_name;
106 uint32_t pages_in_lockregion;
109 uint16_t num_lockbits;
111 /* main clock status */
118 const char *iosc_desc;
119 const char *mck_desc;
125 const char *partname;
126 } ambiqmicroParts[6] = {
127 {0xFF, 0x00, "Unknown"},
128 {0x01, 0x00, "Apollo"},
129 {0x02, 0x00, "Apollo2"},
130 {0x03, 0x00, "Unknown"},
131 {0x04, 0x00, "Unknown"},
132 {0x05, 0x00, "Apollo"},
135 static char *ambiqmicroClassname[6] = {
136 "Unknown", "Apollo", "Apollo2", "Unknown", "Unknown", "Apollo"
139 /***************************************************************************
140 * openocd command interface *
141 ***************************************************************************/
143 /* flash_bank ambiqmicro <base> <size> 0 0 <target#>
145 FLASH_BANK_COMMAND_HANDLER(ambiqmicro_flash_bank_command)
147 struct ambiqmicro_flash_bank *ambiqmicro_info;
150 return ERROR_COMMAND_SYNTAX_ERROR;
152 ambiqmicro_info = calloc(sizeof(struct ambiqmicro_flash_bank), 1);
154 bank->driver_priv = ambiqmicro_info;
156 ambiqmicro_info->target_name = "Unknown target";
158 /* part wasn't probed yet */
159 ambiqmicro_info->probed = 0;
164 static int get_ambiqmicro_info(struct flash_bank *bank, char *buf, int buf_size)
166 struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
170 if (ambiqmicro_info->probed == 0) {
171 LOG_ERROR("Target not probed");
172 return ERROR_FLASH_BANK_NOT_PROBED;
175 /* Check class name in range. */
176 if (ambiqmicro_info->target_class < sizeof(ambiqmicroClassname))
177 classname = ambiqmicroClassname[ambiqmicro_info->target_class];
179 classname = ambiqmicroClassname[0];
181 printed = snprintf(buf,
183 "\nAmbiq Micro information: Chip is "
184 "class %d (%s) %s\n",
185 ambiqmicro_info->target_class,
187 ambiqmicro_info->target_name);
190 return ERROR_BUF_TOO_SMALL;
194 /***************************************************************************
195 * chip identification and status *
196 ***************************************************************************/
198 /* Fill in driver info structure */
199 static int ambiqmicro_read_part_info(struct flash_bank *bank)
201 struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
202 struct target *target = bank->target;
203 uint32_t PartNum = 0;
209 retval = target_read_u32(target, 0x40020000, &PartNum);
210 if (retval != ERROR_OK) {
211 LOG_ERROR("status(0x%x):Could not read PartNum.\n", retval);
212 /* Set PartNum to default device */
215 LOG_DEBUG("Part number: 0x%x", PartNum);
218 * Determine device class.
220 ambiqmicro_info->target_class = (PartNum & 0xFF000000) >> 24;
222 switch (ambiqmicro_info->target_class) {
223 case 1: /* 1 - Apollo */
224 case 5: /* 5 - Apollo Bootloader */
225 bank->base = bank->bank_number * 0x40000;
226 ambiqmicro_info->pagesize = 2048;
227 ambiqmicro_info->flshsiz =
228 apollo_flash_size[(PartNum & 0x00F00000) >> 20];
229 ambiqmicro_info->sramsiz =
230 apollo_sram_size[(PartNum & 0x000F0000) >> 16];
231 ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
232 ambiqmicro_info->pagesize;
233 if (ambiqmicro_info->num_pages > 128) {
234 ambiqmicro_info->num_pages = 128;
235 ambiqmicro_info->flshsiz = 1024 * 256;
240 LOG_INFO("Unknown Class. Using Apollo-64 as default.");
242 bank->base = bank->bank_number * 0x40000;
243 ambiqmicro_info->pagesize = 2048;
244 ambiqmicro_info->flshsiz = apollo_flash_size[1];
245 ambiqmicro_info->sramsiz = apollo_sram_size[0];
246 ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
247 ambiqmicro_info->pagesize;
248 if (ambiqmicro_info->num_pages > 128) {
249 ambiqmicro_info->num_pages = 128;
250 ambiqmicro_info->flshsiz = 1024 * 256;
256 if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicroParts))
257 ambiqmicro_info->target_name =
258 ambiqmicroParts[ambiqmicro_info->target_class].partname;
260 ambiqmicro_info->target_name =
261 ambiqmicroParts[0].partname;
263 LOG_DEBUG("num_pages: %d, pagesize: %d, flash: %d, sram: %d",
264 ambiqmicro_info->num_pages,
265 ambiqmicro_info->pagesize,
266 ambiqmicro_info->flshsiz,
267 ambiqmicro_info->sramsiz);
272 /***************************************************************************
274 ***************************************************************************/
276 static int ambiqmicro_protect_check(struct flash_bank *bank)
278 struct ambiqmicro_flash_bank *ambiqmicro = bank->driver_priv;
279 int status = ERROR_OK;
283 if (ambiqmicro->probed == 0) {
284 LOG_ERROR("Target not probed");
285 return ERROR_FLASH_BANK_NOT_PROBED;
288 for (i = 0; i < (unsigned) bank->num_sectors; i++)
289 bank->sectors[i].is_protected = -1;
293 /** Read flash status from bootloader. */
294 static int check_flash_status(struct target *target, uint32_t address)
298 rc = target_read_u32(target, address, &retflash);
299 /* target connection failed. */
300 if (rc != ERROR_OK) {
301 LOG_DEBUG("%s:%d:%s(): status(0x%x)\n",
302 __FILE__, __LINE__, __func__, rc);
305 /* target flash failed, unknown cause. */
307 LOG_ERROR("Flash not happy: status(0x%x)", retflash);
308 return ERROR_FLASH_OPERATION_FAILED;
313 static int ambiqmicro_exec_command(struct target *target,
315 uint32_t flash_return_address)
317 int retval, retflash;
319 retval = target_resume(
326 CHECK_STATUS(retval, "error executing ambiqmicro command");
333 if (target->state == TARGET_HALTED)
335 else if (target->state == TARGET_RUNNING ||
336 target->state == TARGET_DEBUG_RUNNING) {
338 * Keep polling until target halts.
342 LOG_DEBUG("state = %d", target->state);
344 LOG_ERROR("Target not halted or running %d", target->state);
350 * Read return value, flash error takes precedence.
352 retflash = check_flash_status(target, flash_return_address);
353 if (retflash != ERROR_OK)
356 /* Return code from target_resume OR flash. */
360 static int ambiqmicro_mass_erase(struct flash_bank *bank)
362 struct target *target = NULL;
363 struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
364 int retval = ERROR_OK;
366 ambiqmicro_info = bank->driver_priv;
367 target = bank->target;
369 if (target->state != TARGET_HALTED) {
370 LOG_ERROR("Target not halted");
371 return ERROR_TARGET_NOT_HALTED;
374 if (ambiqmicro_info->probed == 0) {
375 LOG_ERROR("Target not probed");
376 return ERROR_FLASH_BANK_NOT_PROBED;
380 * Clear Bootloader bit.
382 retval = target_write_u32(target, 0x400201a0, 0x0);
383 CHECK_STATUS(retval, "error clearing bootloader bit.");
392 retval = target_write_u32(target, 0x10000000, bank->bank_number);
393 CHECK_STATUS(retval, "error writing target SRAM parameters.");
398 retval = target_write_u32(target, 0x10000004, PROGRAM_KEY);
399 CHECK_STATUS(retval, "error writing target SRAM parameters.");
404 retval = target_write_u32(target, 0x10000008, 0xfffffffe);
405 CHECK_STATUS(retval, "error writing target SRAM parameters.");
408 * Erase the main array.
410 LOG_INFO("Mass erase on bank %d.", bank->bank_number);
413 * passed pc, addr = ROM function, handle breakpoints, not debugging.
415 retval = ambiqmicro_exec_command(target, FLASH_MASS_ERASE_MAIN_PAGES_FROM_SRAM, 0x10000008);
416 CHECK_STATUS(retval, "error executing ambiqmicro flash mass erase.");
417 if (retval != ERROR_OK)
421 * Set Bootloader bit, regardless of command execution.
423 retval = target_write_u32(target, 0x400201a0, 0x1);
424 CHECK_STATUS(retval, "error setting bootloader bit.");
430 static int ambiqmicro_erase(struct flash_bank *bank, int first, int last)
432 struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
433 struct target *target = bank->target;
434 uint32_t retval = ERROR_OK;
436 if (bank->target->state != TARGET_HALTED) {
437 LOG_ERROR("Target not halted");
438 return ERROR_TARGET_NOT_HALTED;
441 if (ambiqmicro_info->probed == 0) {
442 LOG_ERROR("Target not probed");
443 return ERROR_FLASH_BANK_NOT_PROBED;
448 * Fix num_pages for the device.
450 if ((first < 0) || (last < first) || (last >= (int)ambiqmicro_info->num_pages))
451 return ERROR_FLASH_SECTOR_INVALID;
454 * Just Mass Erase if all pages are given.
455 * TODO: Fix num_pages for the device
457 if ((first == 0) && (last == ((int)ambiqmicro_info->num_pages-1)))
458 return ambiqmicro_mass_erase(bank);
461 * Clear Bootloader bit.
463 retval = target_write_u32(target, 0x400201a0, 0x0);
464 CHECK_STATUS(retval, "error clearing bootloader bit.");
473 retval = target_write_u32(target, 0x10000000, bank->bank_number);
474 CHECK_STATUS(retval, "error writing target SRAM parameters.");
477 * Number of pages to erase.
479 retval = target_write_u32(target, 0x10000004, 1 + (last-first));
480 CHECK_STATUS(retval, "error writing target SRAM parameters.");
485 retval = target_write_u32(target, 0x10000008, PROGRAM_KEY);
486 CHECK_STATUS(retval, "error writing target SRAM parameters.");
491 retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
492 CHECK_STATUS(retval, "error writing target SRAM parameters.");
495 * Pointer to flash address.
497 retval = target_write_u32(target, 0x10000010, first);
498 CHECK_STATUS(retval, "error writing target SRAM parameters.");
499 if (retval != ERROR_OK)
505 LOG_INFO("Erasing pages %d to %d on bank %d", first, last, bank->bank_number);
508 * passed pc, addr = ROM function, handle breakpoints, not debugging.
510 retval = ambiqmicro_exec_command(target, FLASH_ERASE_LIST_MAIN_PAGES_FROM_SRAM, 0x1000000C);
511 CHECK_STATUS(retval, "error executing flash page erase");
512 if (retval != ERROR_OK)
515 LOG_INFO("%d pages erased!", 1+(last-first));
519 * Set Bootloader bit.
521 retval = target_write_u32(target, 0x400201a0, 0x1);
522 CHECK_STATUS(retval, "error setting bootloader bit.");
523 if (retval != ERROR_OK)
530 static int ambiqmicro_protect(struct flash_bank *bank, int set, int first, int last)
532 /* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
533 * struct target *target = bank->target; */
538 LOG_INFO("Not yet implemented");
540 if (bank->target->state != TARGET_HALTED) {
541 LOG_ERROR("Target not halted");
542 return ERROR_TARGET_NOT_HALTED;
548 static int ambiqmicro_write_block(struct flash_bank *bank,
549 const uint8_t *buffer, uint32_t offset, uint32_t count)
551 /* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv; */
552 struct target *target = bank->target;
553 uint32_t address = bank->base + offset;
554 uint32_t buffer_pointer = 0x10000010;
556 uint32_t thisrun_count;
557 int retval = ERROR_OK;
559 if (((count%4) != 0) || ((offset%4) != 0)) {
560 LOG_ERROR("write block must be multiple of 4 bytes in offset & length");
565 * Max buffer size for this device.
566 * Hard code 6kB for the buffer.
570 LOG_INFO("Flashing main array");
573 if (count > maxbuffer)
574 thisrun_count = maxbuffer;
576 thisrun_count = count;
585 retval = target_write_u32(target, 0x10000000, address);
586 CHECK_STATUS(retval, "error writing target SRAM parameters.");
589 * Number of 32-bit words to program.
591 retval = target_write_u32(target, 0x10000004, thisrun_count/4);
592 CHECK_STATUS(retval, "error writing target SRAM parameters.");
597 retval = target_write_u32(target, 0x10000008, PROGRAM_KEY);
598 CHECK_STATUS(retval, "error writing target SRAM parameters.");
603 retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
604 CHECK_STATUS(retval, "error writing target SRAM parameters.");
609 retval = target_write_buffer(target, buffer_pointer, thisrun_count, buffer);
611 if (retval != ERROR_OK) {
612 CHECK_STATUS(retval, "error writing target SRAM parameters.");
616 LOG_DEBUG("address = 0x%08x", address);
618 retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_MAIN_FROM_SRAM, 0x1000000c);
619 CHECK_STATUS(retval, "error executing ambiqmicro flash write algorithm");
620 if (retval != ERROR_OK)
622 buffer += thisrun_count;
623 address += thisrun_count;
624 count -= thisrun_count;
628 LOG_INFO("Main array flashed");
631 * Clear Bootloader bit.
633 retval = target_write_u32(target, 0x400201a0, 0x0);
634 CHECK_STATUS(retval, "error clearing bootloader bit");
639 static int ambiqmicro_write(struct flash_bank *bank, const uint8_t *buffer,
640 uint32_t offset, uint32_t count)
644 /* try using a block write */
645 retval = ambiqmicro_write_block(bank, buffer, offset, count);
646 if (retval != ERROR_OK)
647 LOG_ERROR("write failed");
652 static int ambiqmicro_probe(struct flash_bank *bank)
654 struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
657 /* If this is a ambiqmicro chip, it has flash; probe() is just
658 * to figure out how much is present. Only do it once.
660 if (ambiqmicro_info->probed == 1) {
661 LOG_INFO("Target already probed");
665 /* ambiqmicro_read_part_info() already handled error checking and
666 * reporting. Note that it doesn't write, so we don't care about
667 * whether the target is halted or not.
669 retval = ambiqmicro_read_part_info(bank);
670 if (retval != ERROR_OK)
675 bank->sectors = NULL;
678 /* provide this for the benefit of the NOR flash framework */
679 bank->size = ambiqmicro_info->pagesize * ambiqmicro_info->num_pages;
680 bank->num_sectors = ambiqmicro_info->num_pages;
681 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
682 for (int i = 0; i < bank->num_sectors; i++) {
683 bank->sectors[i].offset = i * ambiqmicro_info->pagesize;
684 bank->sectors[i].size = ambiqmicro_info->pagesize;
685 bank->sectors[i].is_erased = -1;
686 bank->sectors[i].is_protected = -1;
690 * Part has been probed.
692 ambiqmicro_info->probed = 1;
697 static int ambiqmicro_otp_program(struct flash_bank *bank,
698 uint32_t offset, uint32_t count)
700 struct target *target = NULL;
701 struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
702 uint32_t retval = ERROR_OK;
704 ambiqmicro_info = bank->driver_priv;
705 target = bank->target;
707 if (target->state != TARGET_HALTED) {
708 LOG_ERROR("Target not halted");
709 return ERROR_TARGET_NOT_HALTED;
712 if (ambiqmicro_info->probed == 0) {
713 LOG_ERROR("Target not probed");
714 return ERROR_FLASH_BANK_NOT_PROBED;
718 LOG_ERROR("Count must be < 256");
719 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
723 * Clear Bootloader bit.
725 retval = target_write_u32(target, 0x400201a0, 0x0);
726 CHECK_STATUS(retval, "error clearing bootloader bit.");
735 retval = target_write_u32(target, 0x10000000, offset);
736 CHECK_STATUS(retval, "error setting target SRAM parameters.");
739 * Num of words to program.
741 retval = target_write_u32(target, 0x10000004, count);
742 CHECK_STATUS(retval, "error setting target SRAM parameters.");
747 retval = target_write_u32(target, 0x10000008, OTP_PROGRAM_KEY);
748 CHECK_STATUS(retval, "error setting target SRAM parameters.");
753 retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
754 CHECK_STATUS(retval, "error setting target SRAM parameters.");
755 if (retval != ERROR_OK)
761 LOG_INFO("Programming OTP offset 0x%08x", offset);
764 * passed pc, addr = ROM function, handle breakpoints, not debugging.
766 retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_OTP_FROM_SRAM, 0x1000000C);
767 CHECK_STATUS(retval, "error executing ambiqmicro otp program algorithm");
769 LOG_INFO("Programming OTP finished.");
776 COMMAND_HANDLER(ambiqmicro_handle_mass_erase_command)
781 return ERROR_COMMAND_SYNTAX_ERROR;
783 struct flash_bank *bank;
784 uint32_t retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
785 if (ERROR_OK != retval)
788 if (ambiqmicro_mass_erase(bank) == ERROR_OK) {
789 /* set all sectors as erased */
790 for (i = 0; i < bank->num_sectors; i++)
791 bank->sectors[i].is_erased = 1;
793 command_print(CMD, "ambiqmicro mass erase complete");
795 command_print(CMD, "ambiqmicro mass erase failed");
800 COMMAND_HANDLER(ambiqmicro_handle_page_erase_command)
802 struct flash_bank *bank;
803 uint32_t first, last;
807 return ERROR_COMMAND_SYNTAX_ERROR;
809 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], first);
810 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], last);
812 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
813 if (ERROR_OK != retval)
816 if (ambiqmicro_erase(bank, first, last) == ERROR_OK)
817 command_print(CMD, "ambiqmicro page erase complete");
819 command_print(CMD, "ambiqmicro page erase failed");
826 * Program the otp block.
828 COMMAND_HANDLER(ambiqmicro_handle_program_otp_command)
830 struct flash_bank *bank;
831 uint32_t offset, count;
835 return ERROR_COMMAND_SYNTAX_ERROR;
837 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], offset);
838 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
840 command_print(CMD, "offset=0x%08x count=%d", offset, count);
842 CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
844 retval = ambiqmicro_otp_program(bank, offset, count);
846 if (retval != ERROR_OK)
847 LOG_ERROR("error check log");
854 static const struct command_registration ambiqmicro_exec_command_handlers[] = {
856 .name = "mass_erase",
858 .handler = ambiqmicro_handle_mass_erase_command,
859 .mode = COMMAND_EXEC,
860 .help = "Erase entire device",
863 .name = "page_erase",
864 .usage = "<bank> <first> <last>",
865 .handler = ambiqmicro_handle_page_erase_command,
866 .mode = COMMAND_EXEC,
867 .help = "Erase device pages",
870 .name = "program_otp",
871 .handler = ambiqmicro_handle_program_otp_command,
872 .mode = COMMAND_EXEC,
873 .usage = "<bank> <offset> <count>",
875 "Program OTP (assumes you have already written array starting at 0x10000010)",
877 COMMAND_REGISTRATION_DONE
879 static const struct command_registration ambiqmicro_command_handlers[] = {
881 .name = "ambiqmicro",
882 .mode = COMMAND_EXEC,
883 .help = "ambiqmicro flash command group",
884 .usage = "Support for Ambiq Micro parts.",
885 .chain = ambiqmicro_exec_command_handlers,
887 COMMAND_REGISTRATION_DONE
890 const struct flash_driver ambiqmicro_flash = {
891 .name = "ambiqmicro",
892 .commands = ambiqmicro_command_handlers,
893 .flash_bank_command = ambiqmicro_flash_bank_command,
894 .erase = ambiqmicro_erase,
895 .protect = ambiqmicro_protect,
896 .write = ambiqmicro_write,
897 .read = default_flash_read,
898 .probe = ambiqmicro_probe,
899 .auto_probe = ambiqmicro_probe,
900 .erase_check = default_flash_blank_check,
901 .protect_check = ambiqmicro_protect_check,
902 .info = get_ambiqmicro_info,
903 .free_driver_priv = default_flash_free_driver_priv,