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   1 /******************************************************************************
   2  *
   3  * @file ambiqmicro.c
   4  *
   5  * @brief Ambiq Micro flash driver.
   6  *
   7  *****************************************************************************/
   8
   9 /******************************************************************************
  10  * Copyright (c) 2015, David Racine <dracine at ambiqmicro.com>
  11  *
  12  * Copyright (c) 2016, Rick Foos <rfoos at solengtech.com>
  13  *
  14  * Copyright (c) 2015-2016, Ambiq Micro, Inc.
  15  *
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are met:
  20  *
  21  * 1. Redistributions of source code must retain the above copyright notice,
  22  * this list of conditions and the following disclaimer.
  23  *
  24  * 2. Redistributions in binary form must reproduce the above copyright
  25  * notice, this list of conditions and the following disclaimer in the
  26  * documentation and/or other materials provided with the distribution.
  27  *
  28  * 3. Neither the name of the copyright holder nor the names of its
  29  * contributors may be used to endorse or promote products derived from this
  30  * software without specific prior written permission.
  31  *
  32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  33  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  34  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  35  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  36  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  37  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  38  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  39  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  40  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  41  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  42  * POSSIBILITY OF SUCH DAMAGE.
  43  *
  44  *****************************************************************************/
  45 #ifdef HAVE_CONFIG_H
  46 #include "config.h"
  47 #endif
  48
  49 #include "jtag/interface.h"
  50 #include "imp.h"
  51 #include "target/algorithm.h"
  52 #include "target/armv7m.h"
  53 #include "target/cortex_m.h"
  54
  55 /** Check error, log error. */
  56 #define CHECK_STATUS(rc, msg) { \
  57                 if (rc != ERROR_OK) { \
  58                         LOG_ERROR("status(%d):%s\n", rc, msg); } }
  59
  60 /*
  61  * Address and Key defines.
  62  */
  63 #define PROGRAM_KEY      (0x12344321)
  64 #define OTP_PROGRAM_KEY  (0x87655678)
  65
  66 #define FLASH_PROGRAM_MAIN_FROM_SRAM                0x0800005d
  67 #define FLASH_PROGRAM_OTP_FROM_SRAM                 0x08000061
  68 #define FLASH_ERASE_LIST_MAIN_PAGES_FROM_SRAM       0x08000065
  69 #define FLASH_MASS_ERASE_MAIN_PAGES_FROM_SRAM       0x08000069
  70
  71
  72 static const uint32_t apollo_flash_size[] = {
  73         1 << 15,
  74         1 << 16,
  75         1 << 17,
  76         1 << 18,
  77         1 << 19,
  78         1 << 20,
  79         1 << 21
  80 };
  81
  82 static const uint32_t apollo_sram_size[] = {
  83         1 << 15,
  84         1 << 16,
  85         1 << 17,
  86         1 << 18,
  87         1 << 19,
  88         1 << 20,
  89         1 << 21
  90 };
  91
  92 struct ambiqmicro_flash_bank {
  93         /* chip id register */
  94
  95         bool probed;
  96
  97         const char *target_name;
  98         uint8_t target_class;
  99
 100         uint32_t sramsiz;
 101         uint32_t flshsiz;
 102
 103         /* flash geometry */
 104         uint32_t num_pages;
 105         uint32_t pagesize;
 106         uint32_t pages_in_lockregion;
 107
 108         /* nv memory bits */
 109         uint16_t num_lockbits;
 110
 111         /* main clock status */
 112         uint32_t rcc;
 113         uint32_t rcc2;
 114         uint8_t mck_valid;
 115         uint8_t xtal_mask;
 116         uint32_t iosc_freq;
 117         uint32_t mck_freq;
 118         const char *iosc_desc;
 119         const char *mck_desc;
 120 };
 121
 122 static struct {
 123         uint8_t class;
 124         uint8_t partno;
 125         const char *partname;
 126 } ambiqmicro_parts[6] = {
 127         {0xFF, 0x00, "Unknown"},
 128         {0x01, 0x00, "Apollo"},
 129         {0x02, 0x00, "Apollo2"},
 130         {0x03, 0x00, "Unknown"},
 131         {0x04, 0x00, "Unknown"},
 132         {0x05, 0x00, "Apollo"},
 133 };
 134
 135 static char *ambiqmicro_classname[6] = {
 136         "Unknown", "Apollo", "Apollo2", "Unknown", "Unknown", "Apollo"
 137 };
 138
 139 /***************************************************************************
 140 *       openocd command interface                                              *
 141 ***************************************************************************/
 142
 143 /* flash_bank ambiqmicro <base> <size> 0 0 <target#>
 144  */
 145 FLASH_BANK_COMMAND_HANDLER(ambiqmicro_flash_bank_command)
 146 {
 147         struct ambiqmicro_flash_bank *ambiqmicro_info;
 148
 149         if (CMD_ARGC < 6)
 150                 return ERROR_COMMAND_SYNTAX_ERROR;
 151
 152         ambiqmicro_info = calloc(sizeof(struct ambiqmicro_flash_bank), 1);
 153
 154         bank->driver_priv = ambiqmicro_info;
 155
 156         ambiqmicro_info->target_name = "Unknown target";
 157
 158         /* part wasn't probed yet */
 159         ambiqmicro_info->probed = false;
 160
 161         return ERROR_OK;
 162 }
 163
 164 static int get_ambiqmicro_info(struct flash_bank *bank, struct command_invocation *cmd)
 165 {
 166         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 167         char *classname;
 168
 169         if (!ambiqmicro_info->probed) {
 170                 LOG_ERROR("Target not probed");
 171                 return ERROR_FLASH_BANK_NOT_PROBED;
 172         }
 173
 174         /* Check class name in range. */
 175         if (ambiqmicro_info->target_class < sizeof(ambiqmicro_classname))
 176                 classname = ambiqmicro_classname[ambiqmicro_info->target_class];
 177         else
 178                 classname = ambiqmicro_classname[0];
 179
 180         command_print_sameline(cmd, "\nAmbiq Micro information: Chip is "
 181                 "class %d (%s) %s\n",
 182                 ambiqmicro_info->target_class,
 183                 classname,
 184                 ambiqmicro_info->target_name);
 185
 186         return ERROR_OK;
 187 }
 188
 189 /***************************************************************************
 190 *       chip identification and status                                         *
 191 ***************************************************************************/
 192
 193 /* Fill in driver info structure */
 194 static int ambiqmicro_read_part_info(struct flash_bank *bank)
 195 {
 196         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 197         struct target *target = bank->target;
 198         uint32_t part_num = 0;
 199         int retval;
 200
 201         /*
 202          * Read Part Number.
 203          */
 204         retval = target_read_u32(target, 0x40020000, &part_num);
 205         if (retval != ERROR_OK) {
 206                 LOG_ERROR("status(0x%x):Could not read part_num.\n", retval);
 207                 /* Set part_num to default device */
 208                 part_num = 0;
 209         }
 210         LOG_DEBUG("Part number: 0x%" PRIx32, part_num);
 211
 212         /*
 213          * Determine device class.
 214          */
 215         ambiqmicro_info->target_class = (part_num & 0xFF000000) >> 24;
 216
 217         switch (ambiqmicro_info->target_class) {
 218                 case 1:         /* 1 - Apollo */
 219                 case 5:         /* 5 - Apollo Bootloader */
 220                         bank->base = bank->bank_number * 0x40000;
 221                         ambiqmicro_info->pagesize = 2048;
 222                         ambiqmicro_info->flshsiz =
 223                         apollo_flash_size[(part_num & 0x00F00000) >> 20];
 224                         ambiqmicro_info->sramsiz =
 225                         apollo_sram_size[(part_num & 0x000F0000) >> 16];
 226                         ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
 227                         ambiqmicro_info->pagesize;
 228                         if (ambiqmicro_info->num_pages > 128) {
 229                                 ambiqmicro_info->num_pages = 128;
 230                                 ambiqmicro_info->flshsiz = 1024 * 256;
 231                         }
 232                         break;
 233
 234                 default:
 235                         LOG_INFO("Unknown Class. Using Apollo-64 as default.");
 236
 237                         bank->base = bank->bank_number * 0x40000;
 238                         ambiqmicro_info->pagesize = 2048;
 239                         ambiqmicro_info->flshsiz = apollo_flash_size[1];
 240                         ambiqmicro_info->sramsiz = apollo_sram_size[0];
 241                         ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
 242                         ambiqmicro_info->pagesize;
 243                         if (ambiqmicro_info->num_pages > 128) {
 244                                 ambiqmicro_info->num_pages = 128;
 245                                 ambiqmicro_info->flshsiz = 1024 * 256;
 246                         }
 247                         break;
 248
 249         }
 250
 251         if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicro_parts))
 252                 ambiqmicro_info->target_name =
 253                         ambiqmicro_parts[ambiqmicro_info->target_class].partname;
 254         else
 255                 ambiqmicro_info->target_name =
 256                         ambiqmicro_parts[0].partname;
 257
 258         LOG_DEBUG("num_pages: %" PRIu32 ", pagesize: %" PRIu32 ", flash: %" PRIu32 ", sram: %" PRIu32,
 259                 ambiqmicro_info->num_pages,
 260                 ambiqmicro_info->pagesize,
 261                 ambiqmicro_info->flshsiz,
 262                 ambiqmicro_info->sramsiz);
 263
 264         return ERROR_OK;
 265 }
 266
 267 /***************************************************************************
 268 *       flash operations                                                       *
 269 ***************************************************************************/
 270
 271 static int ambiqmicro_protect_check(struct flash_bank *bank)
 272 {
 273         struct ambiqmicro_flash_bank *ambiqmicro = bank->driver_priv;
 274         int status = ERROR_OK;
 275         uint32_t i;
 276
 277
 278         if (!ambiqmicro->probed) {
 279                 LOG_ERROR("Target not probed");
 280                 return ERROR_FLASH_BANK_NOT_PROBED;
 281         }
 282
 283         for (i = 0; i < (unsigned) bank->num_sectors; i++)
 284                 bank->sectors[i].is_protected = -1;
 285
 286         return status;
 287 }
 288 /** Read flash status from bootloader. */
 289 static int check_flash_status(struct target *target, uint32_t address)
 290 {
 291         uint32_t retflash;
 292         int rc;
 293         rc = target_read_u32(target, address, &retflash);
 294         /* target connection failed. */
 295         if (rc != ERROR_OK) {
 296                 LOG_DEBUG("%s:%d:%s(): status(0x%x)\n",
 297                         __FILE__, __LINE__, __func__, rc);
 298                 return rc;
 299         }
 300         /* target flash failed, unknown cause. */
 301         if (retflash != 0) {
 302                 LOG_ERROR("Flash not happy: status(0x%" PRIx32 ")", retflash);
 303                 return ERROR_FLASH_OPERATION_FAILED;
 304         }
 305         return ERROR_OK;
 306 }
 307
 308 static int ambiqmicro_exec_command(struct target *target,
 309         uint32_t command,
 310         uint32_t flash_return_address)
 311 {
 312         int retval, retflash;
 313
 314         retval = target_resume(
 315                 target,
 316                 false,
 317                 command,
 318                 true,
 319                 true);
 320
 321         CHECK_STATUS(retval, "error executing ambiqmicro command");
 322
 323         /*
 324          * Wait for halt.
 325          */
 326         for (;; ) {
 327                 target_poll(target);
 328                 if (target->state == TARGET_HALTED)
 329                         break;
 330                 else if (target->state == TARGET_RUNNING ||
 331                         target->state == TARGET_DEBUG_RUNNING) {
 332                         /*
 333                          * Keep polling until target halts.
 334                          */
 335                         target_poll(target);
 336                         alive_sleep(100);
 337                         LOG_DEBUG("state = %d", target->state);
 338                 } else {
 339                         LOG_ERROR("Target not halted or running %d", target->state);
 340                         break;
 341                 }
 342         }
 343
 344         /*
 345          * Read return value, flash error takes precedence.
 346          */
 347         retflash = check_flash_status(target, flash_return_address);
 348         if (retflash != ERROR_OK)
 349                 retval = retflash;
 350
 351         /* Return code from target_resume OR flash. */
 352         return retval;
 353 }
 354
 355 static int ambiqmicro_mass_erase(struct flash_bank *bank)
 356 {
 357         struct target *target = NULL;
 358         struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
 359         int retval = ERROR_OK;
 360
 361         ambiqmicro_info = bank->driver_priv;
 362         target = bank->target;
 363
 364         if (target->state != TARGET_HALTED) {
 365                 LOG_ERROR("Target not halted");
 366                 return ERROR_TARGET_NOT_HALTED;
 367         }
 368
 369         if (!ambiqmicro_info->probed) {
 370                 LOG_ERROR("Target not probed");
 371                 return ERROR_FLASH_BANK_NOT_PROBED;
 372         }
 373
 374         /*
 375          * Clear Bootloader bit.
 376          */
 377         retval = target_write_u32(target, 0x400201a0, 0x0);
 378         CHECK_STATUS(retval, "error clearing bootloader bit.");
 379
 380         /*
 381          * Set up the SRAM.
 382          */
 383
 384         /*
 385          * Bank.
 386          */
 387         retval = target_write_u32(target, 0x10000000, bank->bank_number);
 388         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 389
 390         /*
 391          * Write Key.
 392          */
 393         retval = target_write_u32(target, 0x10000004, PROGRAM_KEY);
 394         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 395
 396         /*
 397          * Breakpoint.
 398          */
 399         retval = target_write_u32(target, 0x10000008, 0xfffffffe);
 400         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 401
 402         /*
 403          * Erase the main array.
 404          */
 405         LOG_INFO("Mass erase on bank %d.", bank->bank_number);
 406
 407         /*
 408          * passed pc, addr = ROM function, handle breakpoints, not debugging.
 409          */
 410         retval = ambiqmicro_exec_command(target, FLASH_MASS_ERASE_MAIN_PAGES_FROM_SRAM, 0x10000008);
 411         CHECK_STATUS(retval, "error executing ambiqmicro flash mass erase.");
 412         if (retval != ERROR_OK)
 413                 return retval;
 414
 415         /*
 416          * Set Bootloader bit, regardless of command execution.
 417          */
 418         retval = target_write_u32(target, 0x400201a0, 0x1);
 419         CHECK_STATUS(retval, "error setting bootloader bit.");
 420
 421         return retval;
 422 }
 423
 424
 425 static int ambiqmicro_erase(struct flash_bank *bank, unsigned int first,
 426                 unsigned int last)
 427 {
 428         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 429         struct target *target = bank->target;
 430         int retval;
 431
 432         if (bank->target->state != TARGET_HALTED) {
 433                 LOG_ERROR("Target not halted");
 434                 return ERROR_TARGET_NOT_HALTED;
 435         }
 436
 437         if (!ambiqmicro_info->probed) {
 438                 LOG_ERROR("Target not probed");
 439                 return ERROR_FLASH_BANK_NOT_PROBED;
 440         }
 441
 442         /*
 443          * Check pages.
 444          * Fix num_pages for the device.
 445          */
 446         if ((last < first) || (last >= ambiqmicro_info->num_pages))
 447                 return ERROR_FLASH_SECTOR_INVALID;
 448
 449         /*
 450          * Just Mass Erase if all pages are given.
 451          * TODO: Fix num_pages for the device
 452          */
 453         if ((first == 0) && (last == (ambiqmicro_info->num_pages - 1)))
 454                 return ambiqmicro_mass_erase(bank);
 455
 456         /*
 457          * Clear Bootloader bit.
 458          */
 459         retval = target_write_u32(target, 0x400201a0, 0x0);
 460         CHECK_STATUS(retval, "error clearing bootloader bit.");
 461
 462         /*
 463          * Set up the SRAM.
 464          */
 465
 466         /*
 467          * Bank.
 468          */
 469         retval = target_write_u32(target, 0x10000000, bank->bank_number);
 470         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 471
 472         /*
 473          * Number of pages to erase.
 474          */
 475         retval = target_write_u32(target, 0x10000004, 1 + (last-first));
 476         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 477
 478         /*
 479          * Write Key.
 480          */
 481         retval = target_write_u32(target, 0x10000008, PROGRAM_KEY);
 482         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 483
 484         /*
 485          * Breakpoint.
 486          */
 487         retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
 488         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 489
 490         /*
 491          * Pointer to flash address.
 492          */
 493         retval = target_write_u32(target, 0x10000010, first);
 494         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 495         if (retval != ERROR_OK)
 496                 return retval;
 497
 498         /*
 499          * Erase the pages.
 500          */
 501         LOG_INFO("Erasing pages %u to %u on bank %u", first, last, bank->bank_number);
 502
 503         /*
 504          * passed pc, addr = ROM function, handle breakpoints, not debugging.
 505          */
 506         retval = ambiqmicro_exec_command(target, FLASH_ERASE_LIST_MAIN_PAGES_FROM_SRAM, 0x1000000C);
 507         CHECK_STATUS(retval, "error executing flash page erase");
 508         if (retval != ERROR_OK)
 509                 return retval;
 510
 511         LOG_INFO("%u pages erased!", 1+(last-first));
 512
 513         if (first == 0) {
 514                 /*
 515                  * Set Bootloader bit.
 516                  */
 517                 retval = target_write_u32(target, 0x400201a0, 0x1);
 518                 CHECK_STATUS(retval, "error setting bootloader bit.");
 519                 if (retval != ERROR_OK)
 520                         return retval;
 521         }
 522
 523         return retval;
 524 }
 525
 526 static int ambiqmicro_protect(struct flash_bank *bank, int set,
 527                 unsigned int first, unsigned int last)
 528 {
 529         /* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 530          * struct target *target = bank->target; */
 531
 532         /*
 533          * TODO
 534          */
 535         LOG_INFO("Not yet implemented");
 536
 537         if (bank->target->state != TARGET_HALTED) {
 538                 LOG_ERROR("Target not halted");
 539                 return ERROR_TARGET_NOT_HALTED;
 540         }
 541
 542         return ERROR_OK;
 543 }
 544
 545 static int ambiqmicro_write_block(struct flash_bank *bank,
 546         const uint8_t *buffer, uint32_t offset, uint32_t count)
 547 {
 548         /* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv; */
 549         struct target *target = bank->target;
 550         uint32_t address = bank->base + offset;
 551         uint32_t buffer_pointer = 0x10000010;
 552         uint32_t maxbuffer;
 553         uint32_t thisrun_count;
 554         int retval = ERROR_OK;
 555
 556         if (((count%4) != 0) || ((offset%4) != 0)) {
 557                 LOG_ERROR("write block must be multiple of 4 bytes in offset & length");
 558                 return ERROR_FAIL;
 559         }
 560
 561         /*
 562          * Max buffer size for this device.
 563          * Hard code 6kB for the buffer.
 564          */
 565         maxbuffer = 0x1800;
 566
 567         LOG_INFO("Flashing main array");
 568
 569         while (count > 0) {
 570                 if (count > maxbuffer)
 571                         thisrun_count = maxbuffer;
 572                 else
 573                         thisrun_count = count;
 574
 575                 /*
 576                  * Set up the SRAM.
 577                  */
 578
 579                 /*
 580                  * Pointer to flash.
 581                  */
 582                 retval = target_write_u32(target, 0x10000000, address);
 583                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 584
 585                 /*
 586                  * Number of 32-bit words to program.
 587                  */
 588                 retval = target_write_u32(target, 0x10000004, thisrun_count/4);
 589                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 590
 591                 /*
 592                  * Write Key.
 593                  */
 594                 retval = target_write_u32(target, 0x10000008, PROGRAM_KEY);
 595                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 596
 597                 /*
 598                  * Breakpoint.
 599                  */
 600                 retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
 601                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 602
 603                 /*
 604                  * Write Buffer.
 605                  */
 606                 retval = target_write_buffer(target, buffer_pointer, thisrun_count, buffer);
 607
 608                 if (retval != ERROR_OK) {
 609                         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 610                         break;
 611                 }
 612
 613                 LOG_DEBUG("address = 0x%08" PRIx32, address);
 614
 615                 retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_MAIN_FROM_SRAM, 0x1000000c);
 616                 CHECK_STATUS(retval, "error executing ambiqmicro flash write algorithm");
 617                 if (retval != ERROR_OK)
 618                         break;
 619                 buffer += thisrun_count;
 620                 address += thisrun_count;
 621                 count -= thisrun_count;
 622         }
 623
 624
 625         LOG_INFO("Main array flashed");
 626
 627         /*
 628          * Clear Bootloader bit.
 629          */
 630         retval = target_write_u32(target, 0x400201a0, 0x0);
 631         CHECK_STATUS(retval, "error clearing bootloader bit");
 632
 633         return retval;
 634 }
 635
 636 static int ambiqmicro_write(struct flash_bank *bank, const uint8_t *buffer,
 637         uint32_t offset, uint32_t count)
 638 {
 639         int retval;
 640
 641         /* try using a block write */
 642         retval = ambiqmicro_write_block(bank, buffer, offset, count);
 643         if (retval != ERROR_OK)
 644                 LOG_ERROR("write failed");
 645
 646         return retval;
 647 }
 648
 649 static int ambiqmicro_probe(struct flash_bank *bank)
 650 {
 651         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 652         int retval;
 653
 654         /* If this is a ambiqmicro chip, it has flash; probe() is just
 655          * to figure out how much is present.  Only do it once.
 656          */
 657         if (ambiqmicro_info->probed) {
 658                 LOG_INFO("Target already probed");
 659                 return ERROR_OK;
 660         }
 661
 662         /* ambiqmicro_read_part_info() already handled error checking and
 663          * reporting.  Note that it doesn't write, so we don't care about
 664          * whether the target is halted or not.
 665          */
 666         retval = ambiqmicro_read_part_info(bank);
 667         if (retval != ERROR_OK)
 668                 return retval;
 669
 670         free(bank->sectors);
 671
 672         /* provide this for the benefit of the NOR flash framework */
 673         bank->size = ambiqmicro_info->pagesize * ambiqmicro_info->num_pages;
 674         bank->num_sectors = ambiqmicro_info->num_pages;
 675         bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 676         for (unsigned int i = 0; i < bank->num_sectors; i++) {
 677                 bank->sectors[i].offset = i * ambiqmicro_info->pagesize;
 678                 bank->sectors[i].size = ambiqmicro_info->pagesize;
 679                 bank->sectors[i].is_erased = -1;
 680                 bank->sectors[i].is_protected = -1;
 681         }
 682
 683         /*
 684          * Part has been probed.
 685          */
 686         ambiqmicro_info->probed = true;
 687
 688         return retval;
 689 }
 690
 691 static int ambiqmicro_otp_program(struct flash_bank *bank,
 692         uint32_t offset, uint32_t count)
 693 {
 694         struct target *target = NULL;
 695         struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
 696         int retval;
 697
 698         ambiqmicro_info = bank->driver_priv;
 699         target = bank->target;
 700
 701         if (target->state != TARGET_HALTED) {
 702                 LOG_ERROR("Target not halted");
 703                 return ERROR_TARGET_NOT_HALTED;
 704         }
 705
 706         if (!ambiqmicro_info->probed) {
 707                 LOG_ERROR("Target not probed");
 708                 return ERROR_FLASH_BANK_NOT_PROBED;
 709         }
 710
 711         if (count > 256) {
 712                 LOG_ERROR("Count must be < 256");
 713                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 714         }
 715
 716         /*
 717          * Clear Bootloader bit.
 718          */
 719         retval = target_write_u32(target, 0x400201a0, 0x0);
 720         CHECK_STATUS(retval, "error clearing bootloader bit.");
 721
 722         /*
 723          * Set up the SRAM.
 724          */
 725
 726         /*
 727          * Bank.
 728          */
 729         retval = target_write_u32(target, 0x10000000, offset);
 730         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 731
 732         /*
 733          * Num of words to program.
 734          */
 735         retval = target_write_u32(target, 0x10000004, count);
 736         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 737
 738         /*
 739          * Write Key.
 740          */
 741         retval = target_write_u32(target, 0x10000008, OTP_PROGRAM_KEY);
 742         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 743
 744         /*
 745          * Breakpoint.
 746          */
 747         retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
 748         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 749         if (retval != ERROR_OK)
 750                 return retval;
 751
 752         /*
 753          * Program OTP.
 754          */
 755         LOG_INFO("Programming OTP offset 0x%08" PRIx32, offset);
 756
 757         /*
 758          * passed pc, addr = ROM function, handle breakpoints, not debugging.
 759          */
 760         retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_OTP_FROM_SRAM, 0x1000000C);
 761         CHECK_STATUS(retval, "error executing ambiqmicro otp program algorithm");
 762
 763         LOG_INFO("Programming OTP finished.");
 764
 765         return retval;
 766 }
 767
 768
 769
 770 COMMAND_HANDLER(ambiqmicro_handle_mass_erase_command)
 771 {
 772         if (CMD_ARGC < 1)
 773                 return ERROR_COMMAND_SYNTAX_ERROR;
 774
 775         struct flash_bank *bank;
 776         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 777         if (retval != ERROR_OK)
 778                 return retval;
 779
 780         if (ambiqmicro_mass_erase(bank) == ERROR_OK) {
 781                 /* set all sectors as erased */
 782                 for (unsigned int i = 0; i < bank->num_sectors; i++)
 783                         bank->sectors[i].is_erased = 1;
 784
 785                 command_print(CMD, "ambiqmicro mass erase complete");
 786         } else
 787                 command_print(CMD, "ambiqmicro mass erase failed");
 788
 789         return ERROR_OK;
 790 }
 791
 792 COMMAND_HANDLER(ambiqmicro_handle_page_erase_command)
 793 {
 794         struct flash_bank *bank;
 795         uint32_t first, last;
 796         int retval;
 797
 798         if (CMD_ARGC < 3)
 799                 return ERROR_COMMAND_SYNTAX_ERROR;
 800
 801         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], first);
 802         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], last);
 803
 804         retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 805         if (retval != ERROR_OK)
 806                 return retval;
 807
 808         if (ambiqmicro_erase(bank, first, last) == ERROR_OK)
 809                 command_print(CMD, "ambiqmicro page erase complete");
 810         else
 811                 command_print(CMD, "ambiqmicro page erase failed");
 812
 813         return ERROR_OK;
 814 }
 815
 816
 817 /**
 818  * Program the otp block.
 819  */
 820 COMMAND_HANDLER(ambiqmicro_handle_program_otp_command)
 821 {
 822         struct flash_bank *bank;
 823         uint32_t offset, count;
 824         int retval;
 825
 826         if (CMD_ARGC < 3)
 827                 return ERROR_COMMAND_SYNTAX_ERROR;
 828
 829         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], offset);
 830         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
 831
 832         command_print(CMD, "offset=0x%08" PRIx32 " count=%" PRIu32, offset, count);
 833
 834         CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 835
 836         retval = ambiqmicro_otp_program(bank, offset, count);
 837
 838         if (retval != ERROR_OK)
 839                 LOG_ERROR("error check log");
 840
 841         return ERROR_OK;
 842 }
 843
 844
 845
 846 static const struct command_registration ambiqmicro_exec_command_handlers[] = {
 847         {
 848                 .name = "mass_erase",
 849                 .usage = "<bank>",
 850                 .handler = ambiqmicro_handle_mass_erase_command,
 851                 .mode = COMMAND_EXEC,
 852                 .help = "Erase entire device",
 853         },
 854         {
 855                 .name = "page_erase",
 856                 .usage = "<bank> <first> <last>",
 857                 .handler = ambiqmicro_handle_page_erase_command,
 858                 .mode = COMMAND_EXEC,
 859                 .help = "Erase device pages",
 860         },
 861         {
 862                 .name = "program_otp",
 863                 .handler = ambiqmicro_handle_program_otp_command,
 864                 .mode = COMMAND_EXEC,
 865                 .usage = "<bank> <offset> <count>",
 866                 .help =
 867                         "Program OTP (assumes you have already written array starting at 0x10000010)",
 868         },
 869         COMMAND_REGISTRATION_DONE
 870 };
 871 static const struct command_registration ambiqmicro_command_handlers[] = {
 872         {
 873                 .name = "ambiqmicro",
 874                 .mode = COMMAND_EXEC,
 875                 .help = "ambiqmicro flash command group",
 876                 .usage = "Support for Ambiq Micro parts.",
 877                 .chain = ambiqmicro_exec_command_handlers,
 878         },
 879         COMMAND_REGISTRATION_DONE
 880 };
 881
 882 const struct flash_driver ambiqmicro_flash = {
 883         .name = "ambiqmicro",
 884         .commands = ambiqmicro_command_handlers,
 885         .flash_bank_command = ambiqmicro_flash_bank_command,
 886         .erase = ambiqmicro_erase,
 887         .protect = ambiqmicro_protect,
 888         .write = ambiqmicro_write,
 889         .read = default_flash_read,
 890         .probe = ambiqmicro_probe,
 891         .auto_probe = ambiqmicro_probe,
 892         .erase_check = default_flash_blank_check,
 893         .protect_check = ambiqmicro_protect_check,
 894         .info = get_ambiqmicro_info,
 895         .free_driver_priv = default_flash_free_driver_priv,
 896 };