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   1 /******************************************************************************
   2  *
   3  * @file ambiqmicro.c
   4  *
   5  * @brief Ambiq Micro flash driver.
   6  *
   7  *****************************************************************************/
   8
   9 /******************************************************************************
  10  * Copyright (c) 2015, David Racine <dracine at ambiqmicro.com>
  11  *
  12  * Copyright (c) 2016, Rick Foos <rfoos at solengtech.com>
  13  *
  14  * Copyright (c) 2015-2016, Ambiq Micro, Inc.
  15  *
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are met:
  20  *
  21  * 1. Redistributions of source code must retain the above copyright notice,
  22  * this list of conditions and the following disclaimer.
  23  *
  24  * 2. Redistributions in binary form must reproduce the above copyright
  25  * notice, this list of conditions and the following disclaimer in the
  26  * documentation and/or other materials provided with the distribution.
  27  *
  28  * 3. Neither the name of the copyright holder nor the names of its
  29  * contributors may be used to endorse or promote products derived from this
  30  * software without specific prior written permission.
  31  *
  32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  33  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  34  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  35  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  36  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  37  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  38  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  39  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  40  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  41  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  42  * POSSIBILITY OF SUCH DAMAGE.
  43  *
  44  *****************************************************************************/
  45 #ifdef HAVE_CONFIG_H
  46 #include "config.h"
  47 #endif
  48
  49 #include "jtag/interface.h"
  50 #include "imp.h"
  51 #include "target/algorithm.h"
  52 #include "target/armv7m.h"
  53 #include "target/cortex_m.h"
  54
  55 /** Check error, log error. */
  56 #define CHECK_STATUS(rc, msg) { \
  57                 if (rc != ERROR_OK) { \
  58                         LOG_ERROR("status(%d):%s\n", rc, msg); } }
  59
  60 /*
  61  * Address and Key defines.
  62  */
  63 #define PROGRAM_KEY      (0x12344321)
  64 #define OTP_PROGRAM_KEY  (0x87655678)
  65
  66 #define FLASH_PROGRAM_MAIN_FROM_SRAM                0x0800005d
  67 #define FLASH_PROGRAM_OTP_FROM_SRAM                 0x08000061
  68 #define FLASH_ERASE_LIST_MAIN_PAGES_FROM_SRAM       0x08000065
  69 #define FLASH_MASS_ERASE_MAIN_PAGES_FROM_SRAM       0x08000069
  70
  71
  72 static const uint32_t apollo_flash_size[] = {
  73         1 << 15,
  74         1 << 16,
  75         1 << 17,
  76         1 << 18,
  77         1 << 19,
  78         1 << 20,
  79         1 << 21
  80 };
  81
  82 static const uint32_t apollo_sram_size[] = {
  83         1 << 15,
  84         1 << 16,
  85         1 << 17,
  86         1 << 18,
  87         1 << 19,
  88         1 << 20,
  89         1 << 21
  90 };
  91
  92 struct ambiqmicro_flash_bank {
  93         /* chip id register */
  94
  95         uint32_t probed;
  96
  97         const char *target_name;
  98         uint8_t target_class;
  99
 100         uint32_t sramsiz;
 101         uint32_t flshsiz;
 102
 103         /* flash geometry */
 104         uint32_t num_pages;
 105         uint32_t pagesize;
 106         uint32_t pages_in_lockregion;
 107
 108         /* nv memory bits */
 109         uint16_t num_lockbits;
 110
 111         /* main clock status */
 112         uint32_t rcc;
 113         uint32_t rcc2;
 114         uint8_t mck_valid;
 115         uint8_t xtal_mask;
 116         uint32_t iosc_freq;
 117         uint32_t mck_freq;
 118         const char *iosc_desc;
 119         const char *mck_desc;
 120 };
 121
 122 static struct {
 123         uint8_t class;
 124         uint8_t partno;
 125         const char *partname;
 126 } ambiqmicroParts[6] = {
 127         {0xFF, 0x00, "Unknown"},
 128         {0x01, 0x00, "Apollo"},
 129         {0x02, 0x00, "Apollo2"},
 130         {0x03, 0x00, "Unknown"},
 131         {0x04, 0x00, "Unknown"},
 132         {0x05, 0x00, "Apollo"},
 133 };
 134
 135 static char *ambiqmicroClassname[6] = {
 136         "Unknown", "Apollo", "Apollo2", "Unknown", "Unknown", "Apollo"
 137 };
 138
 139 /***************************************************************************
 140 *       openocd command interface                                              *
 141 ***************************************************************************/
 142
 143 /* flash_bank ambiqmicro <base> <size> 0 0 <target#>
 144  */
 145 FLASH_BANK_COMMAND_HANDLER(ambiqmicro_flash_bank_command)
 146 {
 147         struct ambiqmicro_flash_bank *ambiqmicro_info;
 148
 149         if (CMD_ARGC < 6)
 150                 return ERROR_COMMAND_SYNTAX_ERROR;
 151
 152         ambiqmicro_info = calloc(sizeof(struct ambiqmicro_flash_bank), 1);
 153
 154         bank->driver_priv = ambiqmicro_info;
 155
 156         ambiqmicro_info->target_name = "Unknown target";
 157
 158         /* part wasn't probed yet */
 159         ambiqmicro_info->probed = 0;
 160
 161         return ERROR_OK;
 162 }
 163
 164 static int get_ambiqmicro_info(struct flash_bank *bank, char *buf, int buf_size)
 165 {
 166         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 167         int printed;
 168         char *classname;
 169
 170         if (ambiqmicro_info->probed == 0) {
 171                 LOG_ERROR("Target not probed");
 172                 return ERROR_FLASH_BANK_NOT_PROBED;
 173         }
 174
 175         /* Check class name in range. */
 176         if (ambiqmicro_info->target_class < sizeof(ambiqmicroClassname))
 177                 classname = ambiqmicroClassname[ambiqmicro_info->target_class];
 178         else
 179                 classname = ambiqmicroClassname[0];
 180
 181         printed = snprintf(buf,
 182                 buf_size,
 183                 "\nAmbiq Micro information: Chip is "
 184                 "class %d (%s) %s\n",
 185                 ambiqmicro_info->target_class,
 186                 classname,
 187                 ambiqmicro_info->target_name);
 188
 189         if ((printed < 0))
 190                 return ERROR_BUF_TOO_SMALL;
 191         return ERROR_OK;
 192 }
 193
 194 /***************************************************************************
 195 *       chip identification and status                                         *
 196 ***************************************************************************/
 197
 198 /* Fill in driver info structure */
 199 static int ambiqmicro_read_part_info(struct flash_bank *bank)
 200 {
 201         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 202         struct target *target = bank->target;
 203         uint32_t PartNum = 0;
 204         int retval;
 205
 206         /*
 207          * Read Part Number.
 208          */
 209         retval = target_read_u32(target, 0x40020000, &PartNum);
 210         if (retval != ERROR_OK) {
 211                 LOG_ERROR("status(0x%x):Could not read PartNum.\n", retval);
 212                 /* Set PartNum to default device */
 213                 PartNum = 0;
 214         }
 215         LOG_DEBUG("Part number: 0x%x", PartNum);
 216
 217         /*
 218          * Determine device class.
 219          */
 220         ambiqmicro_info->target_class = (PartNum & 0xFF000000) >> 24;
 221
 222         switch (ambiqmicro_info->target_class) {
 223                 case 1:         /* 1 - Apollo */
 224                 case 5:         /* 5 - Apollo Bootloader */
 225                         bank->base = bank->bank_number * 0x40000;
 226                         ambiqmicro_info->pagesize = 2048;
 227                         ambiqmicro_info->flshsiz =
 228                         apollo_flash_size[(PartNum & 0x00F00000) >> 20];
 229                         ambiqmicro_info->sramsiz =
 230                         apollo_sram_size[(PartNum & 0x000F0000) >> 16];
 231                         ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
 232                         ambiqmicro_info->pagesize;
 233                         if (ambiqmicro_info->num_pages > 128) {
 234                                 ambiqmicro_info->num_pages = 128;
 235                                 ambiqmicro_info->flshsiz = 1024 * 256;
 236                         }
 237                         break;
 238
 239                 default:
 240                         LOG_INFO("Unknown Class. Using Apollo-64 as default.");
 241
 242                         bank->base = bank->bank_number * 0x40000;
 243                         ambiqmicro_info->pagesize = 2048;
 244                         ambiqmicro_info->flshsiz = apollo_flash_size[1];
 245                         ambiqmicro_info->sramsiz = apollo_sram_size[0];
 246                         ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
 247                         ambiqmicro_info->pagesize;
 248                         if (ambiqmicro_info->num_pages > 128) {
 249                                 ambiqmicro_info->num_pages = 128;
 250                                 ambiqmicro_info->flshsiz = 1024 * 256;
 251                         }
 252                         break;
 253
 254         }
 255
 256         if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicroParts))
 257                 ambiqmicro_info->target_name =
 258                         ambiqmicroParts[ambiqmicro_info->target_class].partname;
 259         else
 260                 ambiqmicro_info->target_name =
 261                         ambiqmicroParts[0].partname;
 262
 263         LOG_DEBUG("num_pages: %d, pagesize: %d, flash: %d, sram: %d",
 264                 ambiqmicro_info->num_pages,
 265                 ambiqmicro_info->pagesize,
 266                 ambiqmicro_info->flshsiz,
 267                 ambiqmicro_info->sramsiz);
 268
 269         return ERROR_OK;
 270 }
 271
 272 /***************************************************************************
 273 *       flash operations                                                       *
 274 ***************************************************************************/
 275
 276 static int ambiqmicro_protect_check(struct flash_bank *bank)
 277 {
 278         struct ambiqmicro_flash_bank *ambiqmicro = bank->driver_priv;
 279         int status = ERROR_OK;
 280         uint32_t i;
 281
 282
 283         if (ambiqmicro->probed == 0) {
 284                 LOG_ERROR("Target not probed");
 285                 return ERROR_FLASH_BANK_NOT_PROBED;
 286         }
 287
 288         for (i = 0; i < (unsigned) bank->num_sectors; i++)
 289                 bank->sectors[i].is_protected = -1;
 290
 291         return status;
 292 }
 293 /** Read flash status from bootloader. */
 294 static int check_flash_status(struct target *target, uint32_t address)
 295 {
 296         uint32_t retflash;
 297         int rc;
 298         rc = target_read_u32(target, address, &retflash);
 299         /* target connection failed. */
 300         if (rc != ERROR_OK) {
 301                 LOG_DEBUG("%s:%d:%s(): status(0x%x)\n",
 302                         __FILE__, __LINE__, __func__, rc);
 303                 return rc;
 304         }
 305         /* target flash failed, unknown cause. */
 306         if (retflash != 0) {
 307                 LOG_ERROR("Flash not happy: status(0x%x)", retflash);
 308                 return ERROR_FLASH_OPERATION_FAILED;
 309         }
 310         return ERROR_OK;
 311 }
 312
 313 static int ambiqmicro_exec_command(struct target *target,
 314         uint32_t command,
 315         uint32_t flash_return_address)
 316 {
 317         int retval, retflash;
 318
 319         retval = target_resume(
 320                 target,
 321                 false,
 322                 command,
 323                 true,
 324                 true);
 325
 326         CHECK_STATUS(retval, "error executing ambiqmicro command");
 327
 328         /*
 329          * Wait for halt.
 330          */
 331         for (;; ) {
 332                 target_poll(target);
 333                 if (target->state == TARGET_HALTED)
 334                         break;
 335                 else if (target->state == TARGET_RUNNING ||
 336                         target->state == TARGET_DEBUG_RUNNING) {
 337                         /*
 338                          * Keep polling until target halts.
 339                          */
 340                         target_poll(target);
 341                         alive_sleep(100);
 342                         LOG_DEBUG("state = %d", target->state);
 343                 } else {
 344                         LOG_ERROR("Target not halted or running %d", target->state);
 345                         break;
 346                 }
 347         }
 348
 349         /*
 350          * Read return value, flash error takes precedence.
 351          */
 352         retflash = check_flash_status(target, flash_return_address);
 353         if (retflash != ERROR_OK)
 354                 retval = retflash;
 355
 356         /* Return code from target_resume OR flash. */
 357         return retval;
 358 }
 359
 360 static int ambiqmicro_mass_erase(struct flash_bank *bank)
 361 {
 362         struct target *target = NULL;
 363         struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
 364         int retval = ERROR_OK;
 365
 366         ambiqmicro_info = bank->driver_priv;
 367         target = bank->target;
 368
 369         if (target->state != TARGET_HALTED) {
 370                 LOG_ERROR("Target not halted");
 371                 return ERROR_TARGET_NOT_HALTED;
 372         }
 373
 374         if (ambiqmicro_info->probed == 0) {
 375                 LOG_ERROR("Target not probed");
 376                 return ERROR_FLASH_BANK_NOT_PROBED;
 377         }
 378
 379         /*
 380          * Clear Bootloader bit.
 381          */
 382         retval = target_write_u32(target, 0x400201a0, 0x0);
 383         CHECK_STATUS(retval, "error clearing bootloader bit.");
 384
 385         /*
 386          * Set up the SRAM.
 387          */
 388
 389         /*
 390          * Bank.
 391          */
 392         retval = target_write_u32(target, 0x10000000, bank->bank_number);
 393         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 394
 395         /*
 396          * Write Key.
 397          */
 398         retval = target_write_u32(target, 0x10000004, PROGRAM_KEY);
 399         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 400
 401         /*
 402          * Breakpoint.
 403          */
 404         retval = target_write_u32(target, 0x10000008, 0xfffffffe);
 405         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 406
 407         /*
 408          * Erase the main array.
 409          */
 410         LOG_INFO("Mass erase on bank %d.", bank->bank_number);
 411
 412         /*
 413          * passed pc, addr = ROM function, handle breakpoints, not debugging.
 414          */
 415         retval = ambiqmicro_exec_command(target, FLASH_MASS_ERASE_MAIN_PAGES_FROM_SRAM, 0x10000008);
 416         CHECK_STATUS(retval, "error executing ambiqmicro flash mass erase.");
 417         if (retval != ERROR_OK)
 418                 return retval;
 419
 420         /*
 421          * Set Bootloader bit, regardless of command execution.
 422          */
 423         retval = target_write_u32(target, 0x400201a0, 0x1);
 424         CHECK_STATUS(retval, "error setting bootloader bit.");
 425
 426         return retval;
 427 }
 428
 429
 430 static int ambiqmicro_erase(struct flash_bank *bank, unsigned int first,
 431                 unsigned int last)
 432 {
 433         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 434         struct target *target = bank->target;
 435         uint32_t retval = ERROR_OK;
 436
 437         if (bank->target->state != TARGET_HALTED) {
 438                 LOG_ERROR("Target not halted");
 439                 return ERROR_TARGET_NOT_HALTED;
 440         }
 441
 442         if (ambiqmicro_info->probed == 0) {
 443                 LOG_ERROR("Target not probed");
 444                 return ERROR_FLASH_BANK_NOT_PROBED;
 445         }
 446
 447         /*
 448          * Check pages.
 449          * Fix num_pages for the device.
 450          */
 451         if ((last < first) || (last >= ambiqmicro_info->num_pages))
 452                 return ERROR_FLASH_SECTOR_INVALID;
 453
 454         /*
 455          * Just Mass Erase if all pages are given.
 456          * TODO: Fix num_pages for the device
 457          */
 458         if ((first == 0) && (last == (ambiqmicro_info->num_pages - 1)))
 459                 return ambiqmicro_mass_erase(bank);
 460
 461         /*
 462          * Clear Bootloader bit.
 463          */
 464         retval = target_write_u32(target, 0x400201a0, 0x0);
 465         CHECK_STATUS(retval, "error clearing bootloader bit.");
 466
 467         /*
 468          * Set up the SRAM.
 469          */
 470
 471         /*
 472          * Bank.
 473          */
 474         retval = target_write_u32(target, 0x10000000, bank->bank_number);
 475         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 476
 477         /*
 478          * Number of pages to erase.
 479          */
 480         retval = target_write_u32(target, 0x10000004, 1 + (last-first));
 481         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 482
 483         /*
 484          * Write Key.
 485          */
 486         retval = target_write_u32(target, 0x10000008, PROGRAM_KEY);
 487         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 488
 489         /*
 490          * Breakpoint.
 491          */
 492         retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
 493         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 494
 495         /*
 496          * Pointer to flash address.
 497          */
 498         retval = target_write_u32(target, 0x10000010, first);
 499         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 500         if (retval != ERROR_OK)
 501                 return retval;
 502
 503         /*
 504          * Erase the pages.
 505          */
 506         LOG_INFO("Erasing pages %u to %u on bank %u", first, last, bank->bank_number);
 507
 508         /*
 509          * passed pc, addr = ROM function, handle breakpoints, not debugging.
 510          */
 511         retval = ambiqmicro_exec_command(target, FLASH_ERASE_LIST_MAIN_PAGES_FROM_SRAM, 0x1000000C);
 512         CHECK_STATUS(retval, "error executing flash page erase");
 513         if (retval != ERROR_OK)
 514                 return retval;
 515
 516         LOG_INFO("%u pages erased!", 1+(last-first));
 517
 518         if (first == 0) {
 519                 /*
 520                  * Set Bootloader bit.
 521                  */
 522                 retval = target_write_u32(target, 0x400201a0, 0x1);
 523                 CHECK_STATUS(retval, "error setting bootloader bit.");
 524                 if (retval != ERROR_OK)
 525                         return retval;
 526         }
 527
 528         return retval;
 529 }
 530
 531 static int ambiqmicro_protect(struct flash_bank *bank, int set,
 532                 unsigned int first, unsigned int last)
 533 {
 534         /* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 535          * struct target *target = bank->target; */
 536
 537         /*
 538          * TODO
 539          */
 540         LOG_INFO("Not yet implemented");
 541
 542         if (bank->target->state != TARGET_HALTED) {
 543                 LOG_ERROR("Target not halted");
 544                 return ERROR_TARGET_NOT_HALTED;
 545         }
 546
 547         return ERROR_OK;
 548 }
 549
 550 static int ambiqmicro_write_block(struct flash_bank *bank,
 551         const uint8_t *buffer, uint32_t offset, uint32_t count)
 552 {
 553         /* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv; */
 554         struct target *target = bank->target;
 555         uint32_t address = bank->base + offset;
 556         uint32_t buffer_pointer = 0x10000010;
 557         uint32_t maxbuffer;
 558         uint32_t thisrun_count;
 559         int retval = ERROR_OK;
 560
 561         if (((count%4) != 0) || ((offset%4) != 0)) {
 562                 LOG_ERROR("write block must be multiple of 4 bytes in offset & length");
 563                 return ERROR_FAIL;
 564         }
 565
 566         /*
 567          * Max buffer size for this device.
 568          * Hard code 6kB for the buffer.
 569          */
 570         maxbuffer = 0x1800;
 571
 572         LOG_INFO("Flashing main array");
 573
 574         while (count > 0) {
 575                 if (count > maxbuffer)
 576                         thisrun_count = maxbuffer;
 577                 else
 578                         thisrun_count = count;
 579
 580                 /*
 581                  * Set up the SRAM.
 582                  */
 583
 584                 /*
 585                  * Pointer to flash.
 586                  */
 587                 retval = target_write_u32(target, 0x10000000, address);
 588                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 589
 590                 /*
 591                  * Number of 32-bit words to program.
 592                  */
 593                 retval = target_write_u32(target, 0x10000004, thisrun_count/4);
 594                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 595
 596                 /*
 597                  * Write Key.
 598                  */
 599                 retval = target_write_u32(target, 0x10000008, PROGRAM_KEY);
 600                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 601
 602                 /*
 603                  * Breakpoint.
 604                  */
 605                 retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
 606                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 607
 608                 /*
 609                  * Write Buffer.
 610                  */
 611                 retval = target_write_buffer(target, buffer_pointer, thisrun_count, buffer);
 612
 613                 if (retval != ERROR_OK) {
 614                         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 615                         break;
 616                 }
 617
 618                 LOG_DEBUG("address = 0x%08x", address);
 619
 620                 retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_MAIN_FROM_SRAM, 0x1000000c);
 621                 CHECK_STATUS(retval, "error executing ambiqmicro flash write algorithm");
 622                 if (retval != ERROR_OK)
 623                         break;
 624                 buffer += thisrun_count;
 625                 address += thisrun_count;
 626                 count -= thisrun_count;
 627         }
 628
 629
 630         LOG_INFO("Main array flashed");
 631
 632         /*
 633          * Clear Bootloader bit.
 634          */
 635         retval = target_write_u32(target, 0x400201a0, 0x0);
 636         CHECK_STATUS(retval, "error clearing bootloader bit");
 637
 638         return retval;
 639 }
 640
 641 static int ambiqmicro_write(struct flash_bank *bank, const uint8_t *buffer,
 642         uint32_t offset, uint32_t count)
 643 {
 644         uint32_t retval;
 645
 646         /* try using a block write */
 647         retval = ambiqmicro_write_block(bank, buffer, offset, count);
 648         if (retval != ERROR_OK)
 649                 LOG_ERROR("write failed");
 650
 651         return retval;
 652 }
 653
 654 static int ambiqmicro_probe(struct flash_bank *bank)
 655 {
 656         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 657         uint32_t retval;
 658
 659         /* If this is a ambiqmicro chip, it has flash; probe() is just
 660          * to figure out how much is present.  Only do it once.
 661          */
 662         if (ambiqmicro_info->probed == 1) {
 663                 LOG_INFO("Target already probed");
 664                 return ERROR_OK;
 665         }
 666
 667         /* ambiqmicro_read_part_info() already handled error checking and
 668          * reporting.  Note that it doesn't write, so we don't care about
 669          * whether the target is halted or not.
 670          */
 671         retval = ambiqmicro_read_part_info(bank);
 672         if (retval != ERROR_OK)
 673                 return retval;
 674
 675         if (bank->sectors) {
 676                 free(bank->sectors);
 677                 bank->sectors = NULL;
 678         }
 679
 680         /* provide this for the benefit of the NOR flash framework */
 681         bank->size = ambiqmicro_info->pagesize * ambiqmicro_info->num_pages;
 682         bank->num_sectors = ambiqmicro_info->num_pages;
 683         bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 684         for (unsigned int i = 0; i < bank->num_sectors; i++) {
 685                 bank->sectors[i].offset = i * ambiqmicro_info->pagesize;
 686                 bank->sectors[i].size = ambiqmicro_info->pagesize;
 687                 bank->sectors[i].is_erased = -1;
 688                 bank->sectors[i].is_protected = -1;
 689         }
 690
 691         /*
 692          * Part has been probed.
 693          */
 694         ambiqmicro_info->probed = 1;
 695
 696         return retval;
 697 }
 698
 699 static int ambiqmicro_otp_program(struct flash_bank *bank,
 700         uint32_t offset, uint32_t count)
 701 {
 702         struct target *target = NULL;
 703         struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
 704         uint32_t retval = ERROR_OK;
 705
 706         ambiqmicro_info = bank->driver_priv;
 707         target = bank->target;
 708
 709         if (target->state != TARGET_HALTED) {
 710                 LOG_ERROR("Target not halted");
 711                 return ERROR_TARGET_NOT_HALTED;
 712         }
 713
 714         if (ambiqmicro_info->probed == 0) {
 715                 LOG_ERROR("Target not probed");
 716                 return ERROR_FLASH_BANK_NOT_PROBED;
 717         }
 718
 719         if (count > 256) {
 720                 LOG_ERROR("Count must be < 256");
 721                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 722         }
 723
 724         /*
 725          * Clear Bootloader bit.
 726          */
 727         retval = target_write_u32(target, 0x400201a0, 0x0);
 728         CHECK_STATUS(retval, "error clearing bootloader bit.");
 729
 730         /*
 731          * Set up the SRAM.
 732          */
 733
 734         /*
 735          * Bank.
 736          */
 737         retval = target_write_u32(target, 0x10000000, offset);
 738         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 739
 740         /*
 741          * Num of words to program.
 742          */
 743         retval = target_write_u32(target, 0x10000004, count);
 744         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 745
 746         /*
 747          * Write Key.
 748          */
 749         retval = target_write_u32(target, 0x10000008, OTP_PROGRAM_KEY);
 750         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 751
 752         /*
 753          * Breakpoint.
 754          */
 755         retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
 756         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 757         if (retval != ERROR_OK)
 758                 return retval;
 759
 760         /*
 761          * Program OTP.
 762          */
 763         LOG_INFO("Programming OTP offset 0x%08x", offset);
 764
 765         /*
 766          * passed pc, addr = ROM function, handle breakpoints, not debugging.
 767          */
 768         retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_OTP_FROM_SRAM, 0x1000000C);
 769         CHECK_STATUS(retval, "error executing ambiqmicro otp program algorithm");
 770
 771         LOG_INFO("Programming OTP finished.");
 772
 773         return retval;
 774 }
 775
 776
 777
 778 COMMAND_HANDLER(ambiqmicro_handle_mass_erase_command)
 779 {
 780         if (CMD_ARGC < 1)
 781                 return ERROR_COMMAND_SYNTAX_ERROR;
 782
 783         struct flash_bank *bank;
 784         uint32_t retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 785         if (ERROR_OK != retval)
 786                 return retval;
 787
 788         if (ambiqmicro_mass_erase(bank) == ERROR_OK) {
 789                 /* set all sectors as erased */
 790                 for (unsigned int i = 0; i < bank->num_sectors; i++)
 791                         bank->sectors[i].is_erased = 1;
 792
 793                 command_print(CMD, "ambiqmicro mass erase complete");
 794         } else
 795                 command_print(CMD, "ambiqmicro mass erase failed");
 796
 797         return ERROR_OK;
 798 }
 799
 800 COMMAND_HANDLER(ambiqmicro_handle_page_erase_command)
 801 {
 802         struct flash_bank *bank;
 803         uint32_t first, last;
 804         uint32_t retval;
 805
 806         if (CMD_ARGC < 3)
 807                 return ERROR_COMMAND_SYNTAX_ERROR;
 808
 809         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], first);
 810         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], last);
 811
 812         retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 813         if (ERROR_OK != retval)
 814                 return retval;
 815
 816         if (ambiqmicro_erase(bank, first, last) == ERROR_OK)
 817                 command_print(CMD, "ambiqmicro page erase complete");
 818         else
 819                 command_print(CMD, "ambiqmicro page erase failed");
 820
 821         return ERROR_OK;
 822 }
 823
 824
 825 /**
 826  * Program the otp block.
 827  */
 828 COMMAND_HANDLER(ambiqmicro_handle_program_otp_command)
 829 {
 830         struct flash_bank *bank;
 831         uint32_t offset, count;
 832         uint32_t retval;
 833
 834         if (CMD_ARGC < 3)
 835                 return ERROR_COMMAND_SYNTAX_ERROR;
 836
 837         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], offset);
 838         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
 839
 840         command_print(CMD, "offset=0x%08x count=%d", offset, count);
 841
 842         CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 843
 844         retval = ambiqmicro_otp_program(bank, offset, count);
 845
 846         if (retval != ERROR_OK)
 847                 LOG_ERROR("error check log");
 848
 849         return ERROR_OK;
 850 }
 851
 852
 853
 854 static const struct command_registration ambiqmicro_exec_command_handlers[] = {
 855         {
 856                 .name = "mass_erase",
 857                 .usage = "<bank>",
 858                 .handler = ambiqmicro_handle_mass_erase_command,
 859                 .mode = COMMAND_EXEC,
 860                 .help = "Erase entire device",
 861         },
 862         {
 863                 .name = "page_erase",
 864                 .usage = "<bank> <first> <last>",
 865                 .handler = ambiqmicro_handle_page_erase_command,
 866                 .mode = COMMAND_EXEC,
 867                 .help = "Erase device pages",
 868         },
 869         {
 870                 .name = "program_otp",
 871                 .handler = ambiqmicro_handle_program_otp_command,
 872                 .mode = COMMAND_EXEC,
 873                 .usage = "<bank> <offset> <count>",
 874                 .help =
 875                         "Program OTP (assumes you have already written array starting at 0x10000010)",
 876         },
 877         COMMAND_REGISTRATION_DONE
 878 };
 879 static const struct command_registration ambiqmicro_command_handlers[] = {
 880         {
 881                 .name = "ambiqmicro",
 882                 .mode = COMMAND_EXEC,
 883                 .help = "ambiqmicro flash command group",
 884                 .usage = "Support for Ambiq Micro parts.",
 885                 .chain = ambiqmicro_exec_command_handlers,
 886         },
 887         COMMAND_REGISTRATION_DONE
 888 };
 889
 890 const struct flash_driver ambiqmicro_flash = {
 891         .name = "ambiqmicro",
 892         .commands = ambiqmicro_command_handlers,
 893         .flash_bank_command = ambiqmicro_flash_bank_command,
 894         .erase = ambiqmicro_erase,
 895         .protect = ambiqmicro_protect,
 896         .write = ambiqmicro_write,
 897         .read = default_flash_read,
 898         .probe = ambiqmicro_probe,
 899         .auto_probe = ambiqmicro_probe,
 900         .erase_check = default_flash_blank_check,
 901         .protect_check = ambiqmicro_protect_check,
 902         .info = get_ambiqmicro_info,
 903         .free_driver_priv = default_flash_free_driver_priv,
 904 };