nand_flash_controller_t -> struct nand_flash_controller
[fw/openocd] / src / flash / nand.h
1 /***************************************************************************
2  *   Copyright (C) 2007 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   Partially based on linux/include/linux/mtd/nand.h                     *
6  *   Copyright (C) 2000 David Woodhouse <dwmw2@mvhi.com>                   *
7  *   Copyright (C) 2000 Steven J. Hill <sjhill@realitydiluted.com>         *
8  *   Copyright (C) 2000 Thomas Gleixner <tglx@linutronix.de>               *
9  *                                                                         *
10  *   This program is free software; you can redistribute it and/or modify  *
11  *   it under the terms of the GNU General Public License as published by  *
12  *   the Free Software Foundation; either version 2 of the License, or     *
13  *   (at your option) any later version.                                   *
14  *                                                                         *
15  *   This program is distributed in the hope that it will be useful,       *
16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
18  *   GNU General Public License for more details.                          *
19  *                                                                         *
20  *   You should have received a copy of the GNU General Public License     *
21  *   along with this program; if not, write to the                         *
22  *   Free Software Foundation, Inc.,                                       *
23  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
24  ***************************************************************************/
25 #ifndef NAND_H
26 #define NAND_H
27
28 #include "flash.h"
29
30 struct nand_device_s;
31
32 #define __NAND_DEVICE_COMMAND(name) \
33                 COMMAND_HELPER(name, struct nand_device_s *nand)
34
35 struct nand_flash_controller
36 {
37         char *name;
38         __NAND_DEVICE_COMMAND((*nand_device_command));
39         int (*register_commands)(struct command_context_s *cmd_ctx);
40         int (*init)(struct nand_device_s *nand);
41         int (*reset)(struct nand_device_s *nand);
42         int (*command)(struct nand_device_s *nand, uint8_t command);
43         int (*address)(struct nand_device_s *nand, uint8_t address);
44         int (*write_data)(struct nand_device_s *nand, uint16_t data);
45         int (*read_data)(struct nand_device_s *nand, void *data);
46         int (*write_block_data)(struct nand_device_s *nand, uint8_t *data, int size);
47         int (*read_block_data)(struct nand_device_s *nand, uint8_t *data, int size);
48         int (*write_page)(struct nand_device_s *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
49         int (*read_page)(struct nand_device_s *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
50         int (*controller_ready)(struct nand_device_s *nand, int timeout);
51         int (*nand_ready)(struct nand_device_s *nand, int timeout);
52 };
53
54 #define NAND_DEVICE_COMMAND_HANDLER(name) static __NAND_DEVICE_COMMAND(name)
55
56 typedef struct nand_block_s
57 {
58         uint32_t offset;
59         uint32_t size;
60         int is_erased;
61         int is_bad;
62 } nand_block_t;
63
64 struct nand_oobfree {
65         int offset;
66         int length;
67 };
68
69 typedef struct nand_ecclayout_s {
70         int eccbytes;
71         int eccpos[64];
72         int oobavail;
73         struct nand_oobfree oobfree[2];
74 } nand_ecclayout_t;
75
76 typedef struct nand_device_s
77 {
78         struct nand_flash_controller *controller;
79         void *controller_priv;
80         struct nand_manufacturer_s *manufacturer;
81         struct nand_info_s *device;
82         int bus_width;
83         int address_cycles;
84         int page_size;
85         int erase_size;
86         int use_raw;
87         int num_blocks;
88         nand_block_t *blocks;
89         struct nand_device_s *next;
90 } nand_device_t;
91
92 /* NAND Flash Manufacturer ID Codes
93  */
94 enum
95 {
96         NAND_MFR_TOSHIBA = 0x98,
97         NAND_MFR_SAMSUNG = 0xec,
98         NAND_MFR_FUJITSU = 0x04,
99         NAND_MFR_NATIONAL = 0x8f,
100         NAND_MFR_RENESAS = 0x07,
101         NAND_MFR_STMICRO = 0x20,
102         NAND_MFR_HYNIX = 0xad,
103         NAND_MFR_MICRON = 0x2c,
104 };
105
106 typedef struct nand_manufacturer_s
107 {
108         int id;
109         char *name;
110 } nand_manufacturer_t;
111
112 typedef struct nand_info_s
113 {
114         char *name;
115         int id;
116         int page_size;
117         int chip_size;
118         int erase_size;
119         int options;
120 } nand_info_t;
121
122 /* Option constants for bizarre disfunctionality and real features
123  */
124 enum {
125         /* Chip can not auto increment pages */
126         NAND_NO_AUTOINCR = 0x00000001,
127
128         /* Buswitdh is 16 bit */
129         NAND_BUSWIDTH_16 = 0x00000002,
130
131         /* Device supports partial programming without padding */
132         NAND_NO_PADDING = 0x00000004,
133
134         /* Chip has cache program function */
135         NAND_CACHEPRG = 0x00000008,
136
137         /* Chip has copy back function */
138         NAND_COPYBACK = 0x00000010,
139
140         /* AND Chip which has 4 banks and a confusing page / block
141          * assignment. See Renesas datasheet for further information */
142         NAND_IS_AND = 0x00000020,
143
144         /* Chip has a array of 4 pages which can be read without
145          * additional ready /busy waits */
146         NAND_4PAGE_ARRAY = 0x00000040,
147
148         /* Chip requires that BBT is periodically rewritten to prevent
149          * bits from adjacent blocks from 'leaking' in altering data.
150          * This happens with the Renesas AG-AND chips, possibly others.  */
151         BBT_AUTO_REFRESH = 0x00000080,
152
153         /* Chip does not require ready check on read. True
154          * for all large page devices, as they do not support
155          * autoincrement.*/
156         NAND_NO_READRDY = 0x00000100,
157
158         /* Options valid for Samsung large page devices */
159         NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
160
161         /* Options for new chips with large page size. The pagesize and the
162          * erasesize is determined from the extended id bytes
163          */
164         LP_OPTIONS = (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR),
165         LP_OPTIONS16 = (LP_OPTIONS | NAND_BUSWIDTH_16),
166 };
167
168 enum
169 {
170         /* Standard NAND flash commands */
171         NAND_CMD_READ0 = 0x0,
172         NAND_CMD_READ1 = 0x1,
173         NAND_CMD_RNDOUT = 0x5,
174         NAND_CMD_PAGEPROG = 0x10,
175         NAND_CMD_READOOB = 0x50,
176         NAND_CMD_ERASE1 = 0x60,
177         NAND_CMD_STATUS = 0x70,
178         NAND_CMD_STATUS_MULTI = 0x71,
179         NAND_CMD_SEQIN = 0x80,
180         NAND_CMD_RNDIN = 0x85,
181         NAND_CMD_READID = 0x90,
182         NAND_CMD_ERASE2 = 0xd0,
183         NAND_CMD_RESET = 0xff,
184
185         /* Extended commands for large page devices */
186         NAND_CMD_READSTART = 0x30,
187         NAND_CMD_RNDOUTSTART = 0xE0,
188         NAND_CMD_CACHEDPROG = 0x15,
189 };
190
191 /* Status bits */
192 enum
193 {
194         NAND_STATUS_FAIL = 0x01,
195         NAND_STATUS_FAIL_N1 = 0x02,
196         NAND_STATUS_TRUE_READY = 0x20,
197         NAND_STATUS_READY = 0x40,
198         NAND_STATUS_WP = 0x80,
199 };
200
201 /* OOB (spare) data formats */
202 enum oob_formats
203 {
204         NAND_OOB_NONE = 0x0,    /* no OOB data at all */
205         NAND_OOB_RAW = 0x1,             /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */
206         NAND_OOB_ONLY = 0x2,    /* only OOB data */
207         NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
208         NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
209         NAND_OOB_SW_ECC_KW = 0x40, /* when writing, use Marvell's Kirkwood bootrom format */
210         NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
211         NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
212 };
213
214
215 nand_device_t *get_nand_device_by_num(int num);
216
217 int nand_read_page_raw(struct nand_device_s *nand, uint32_t page,
218                 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
219 int nand_write_page_raw(struct nand_device_s *nand, uint32_t page,
220                 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
221
222 int nand_read_status(struct nand_device_s *nand, uint8_t *status);
223
224 int nand_calculate_ecc(struct nand_device_s *nand,
225                 const uint8_t *dat, uint8_t *ecc_code);
226 int nand_calculate_ecc_kw(struct nand_device_s *nand,
227                 const uint8_t *dat, uint8_t *ecc_code);
228
229 int nand_register_commands(struct command_context_s *cmd_ctx);
230 int nand_init(struct command_context_s *cmd_ctx);
231
232 /// helper for parsing a nand device command argument string
233 int nand_command_get_device_by_num(struct command_context_s *cmd_ctx,
234                 const char *str, nand_device_t **nand);
235
236
237 #define         ERROR_NAND_DEVICE_INVALID               (-1100)
238 #define         ERROR_NAND_OPERATION_FAILED             (-1101)
239 #define         ERROR_NAND_OPERATION_TIMEOUT    (-1102)
240 #define         ERROR_NAND_OPERATION_NOT_SUPPORTED      (-1103)
241 #define         ERROR_NAND_DEVICE_NOT_PROBED    (-1104)
242 #define         ERROR_NAND_ERROR_CORRECTION_FAILED      (-1105)
243 #define         ERROR_NAND_NO_BUFFER                    (-1106)
244
245 #endif /* NAND_H */