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   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Partially based on linux/include/linux/mtd/nand.h                     *
   6  *   Copyright (C) 2000 David Woodhouse <dwmw2@mvhi.com>                   *
   7  *   Copyright (C) 2000 Steven J. Hill <sjhill@realitydiluted.com>         *
   8  *   Copyright (C) 2000 Thomas Gleixner <tglx@linutronix.de>               *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  ***************************************************************************/
  25 #ifndef NAND_H
  26 #define NAND_H
  27
  28 #include "flash.h"
  29
  30 struct nand_device;
  31
  32 #define __NAND_DEVICE_COMMAND(name) \
  33                 COMMAND_HELPER(name, struct nand_device *nand)
  34
  35 struct nand_flash_controller
  36 {
  37         char *name;
  38         __NAND_DEVICE_COMMAND((*nand_device_command));
  39         int (*register_commands)(struct command_context *cmd_ctx);
  40         int (*init)(struct nand_device *nand);
  41         int (*reset)(struct nand_device *nand);
  42         int (*command)(struct nand_device *nand, uint8_t command);
  43         int (*address)(struct nand_device *nand, uint8_t address);
  44         int (*write_data)(struct nand_device *nand, uint16_t data);
  45         int (*read_data)(struct nand_device *nand, void *data);
  46         int (*write_block_data)(struct nand_device *nand, uint8_t *data, int size);
  47         int (*read_block_data)(struct nand_device *nand, uint8_t *data, int size);
  48         int (*write_page)(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
  49         int (*read_page)(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
  50         int (*controller_ready)(struct nand_device *nand, int timeout);
  51         int (*nand_ready)(struct nand_device *nand, int timeout);
  52 };
  53
  54 #define NAND_DEVICE_COMMAND_HANDLER(name) static __NAND_DEVICE_COMMAND(name)
  55
  56 struct nand_block
  57 {
  58         uint32_t offset;
  59         uint32_t size;
  60         int is_erased;
  61         int is_bad;
  62 };
  63
  64 struct nand_oobfree {
  65         int offset;
  66         int length;
  67 };
  68
  69 struct nand_ecclayout {
  70         int eccbytes;
  71         int eccpos[64];
  72         int oobavail;
  73         struct nand_oobfree oobfree[2];
  74 };
  75
  76 struct nand_device
  77 {
  78         char *name;
  79         struct nand_flash_controller *controller;
  80         void *controller_priv;
  81         struct nand_manufacturer *manufacturer;
  82         struct nand_info *device;
  83         int bus_width;
  84         int address_cycles;
  85         int page_size;
  86         int erase_size;
  87         int use_raw;
  88         int num_blocks;
  89         struct nand_block *blocks;
  90         struct nand_device *next;
  91 };
  92
  93 /* NAND Flash Manufacturer ID Codes
  94  */
  95 enum
  96 {
  97         NAND_MFR_TOSHIBA = 0x98,
  98         NAND_MFR_SAMSUNG = 0xec,
  99         NAND_MFR_FUJITSU = 0x04,
 100         NAND_MFR_NATIONAL = 0x8f,
 101         NAND_MFR_RENESAS = 0x07,
 102         NAND_MFR_STMICRO = 0x20,
 103         NAND_MFR_HYNIX = 0xad,
 104         NAND_MFR_MICRON = 0x2c,
 105 };
 106
 107 struct nand_manufacturer
 108 {
 109         int id;
 110         char *name;
 111 };
 112
 113 struct nand_info
 114 {
 115         char *name;
 116         int id;
 117         int page_size;
 118         int chip_size;
 119         int erase_size;
 120         int options;
 121 };
 122
 123 /* Option constants for bizarre disfunctionality and real features
 124  */
 125 enum {
 126         /* Chip can not auto increment pages */
 127         NAND_NO_AUTOINCR = 0x00000001,
 128
 129         /* Buswitdh is 16 bit */
 130         NAND_BUSWIDTH_16 = 0x00000002,
 131
 132         /* Device supports partial programming without padding */
 133         NAND_NO_PADDING = 0x00000004,
 134
 135         /* Chip has cache program function */
 136         NAND_CACHEPRG = 0x00000008,
 137
 138         /* Chip has copy back function */
 139         NAND_COPYBACK = 0x00000010,
 140
 141         /* AND Chip which has 4 banks and a confusing page / block
 142          * assignment. See Renesas datasheet for further information */
 143         NAND_IS_AND = 0x00000020,
 144
 145         /* Chip has a array of 4 pages which can be read without
 146          * additional ready /busy waits */
 147         NAND_4PAGE_ARRAY = 0x00000040,
 148
 149         /* Chip requires that BBT is periodically rewritten to prevent
 150          * bits from adjacent blocks from 'leaking' in altering data.
 151          * This happens with the Renesas AG-AND chips, possibly others.  */
 152         BBT_AUTO_REFRESH = 0x00000080,
 153
 154         /* Chip does not require ready check on read. True
 155          * for all large page devices, as they do not support
 156          * autoincrement.*/
 157         NAND_NO_READRDY = 0x00000100,
 158
 159         /* Options valid for Samsung large page devices */
 160         NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
 161
 162         /* Options for new chips with large page size. The pagesize and the
 163          * erasesize is determined from the extended id bytes
 164          */
 165         LP_OPTIONS = (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR),
 166         LP_OPTIONS16 = (LP_OPTIONS | NAND_BUSWIDTH_16),
 167 };
 168
 169 enum
 170 {
 171         /* Standard NAND flash commands */
 172         NAND_CMD_READ0 = 0x0,
 173         NAND_CMD_READ1 = 0x1,
 174         NAND_CMD_RNDOUT = 0x5,
 175         NAND_CMD_PAGEPROG = 0x10,
 176         NAND_CMD_READOOB = 0x50,
 177         NAND_CMD_ERASE1 = 0x60,
 178         NAND_CMD_STATUS = 0x70,
 179         NAND_CMD_STATUS_MULTI = 0x71,
 180         NAND_CMD_SEQIN = 0x80,
 181         NAND_CMD_RNDIN = 0x85,
 182         NAND_CMD_READID = 0x90,
 183         NAND_CMD_ERASE2 = 0xd0,
 184         NAND_CMD_RESET = 0xff,
 185
 186         /* Extended commands for large page devices */
 187         NAND_CMD_READSTART = 0x30,
 188         NAND_CMD_RNDOUTSTART = 0xE0,
 189         NAND_CMD_CACHEDPROG = 0x15,
 190 };
 191
 192 /* Status bits */
 193 enum
 194 {
 195         NAND_STATUS_FAIL = 0x01,
 196         NAND_STATUS_FAIL_N1 = 0x02,
 197         NAND_STATUS_TRUE_READY = 0x20,
 198         NAND_STATUS_READY = 0x40,
 199         NAND_STATUS_WP = 0x80,
 200 };
 201
 202 /* OOB (spare) data formats */
 203 enum oob_formats
 204 {
 205         NAND_OOB_NONE = 0x0,    /* no OOB data at all */
 206         NAND_OOB_RAW = 0x1,             /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */
 207         NAND_OOB_ONLY = 0x2,    /* only OOB data */
 208         NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
 209         NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
 210         NAND_OOB_SW_ECC_KW = 0x40, /* when writing, use Marvell's Kirkwood bootrom format */
 211         NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
 212         NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
 213 };
 214
 215
 216 /**
 217  * Returns the flash bank specified by @a name, which matches the
 218  * driver name and a suffix (option) specify the driver-specific
 219  * bank number. The suffix consists of the '.' and the driver-specific
 220  * bank number: when two davinci banks are defined, then 'davinci.1' refers
 221  * to the second (e.g. DM355EVM).
 222  */
 223 struct nand_device *get_nand_device_by_name(const char *name);
 224
 225 struct nand_device *get_nand_device_by_num(int num);
 226
 227 int nand_read_page_raw(struct nand_device *nand, uint32_t page,
 228                 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
 229 int nand_write_page_raw(struct nand_device *nand, uint32_t page,
 230                 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
 231
 232 int nand_read_status(struct nand_device *nand, uint8_t *status);
 233
 234 int nand_calculate_ecc(struct nand_device *nand,
 235                 const uint8_t *dat, uint8_t *ecc_code);
 236 int nand_calculate_ecc_kw(struct nand_device *nand,
 237                 const uint8_t *dat, uint8_t *ecc_code);
 238
 239 int nand_register_commands(struct command_context *cmd_ctx);
 240 int nand_init(struct command_context *cmd_ctx);
 241
 242 /// helper for parsing a nand device command argument string
 243 COMMAND_HELPER(nand_command_get_device, unsigned name_index,
 244                 struct nand_device **nand);
 245
 246
 247 #define         ERROR_NAND_DEVICE_INVALID               (-1100)
 248 #define         ERROR_NAND_OPERATION_FAILED             (-1101)
 249 #define         ERROR_NAND_OPERATION_TIMEOUT    (-1102)
 250 #define         ERROR_NAND_OPERATION_NOT_SUPPORTED      (-1103)
 251 #define         ERROR_NAND_DEVICE_NOT_PROBED    (-1104)
 252 #define         ERROR_NAND_ERROR_CORRECTION_FAILED      (-1105)
 253 #define         ERROR_NAND_NO_BUFFER                    (-1106)
 254
 255 #endif /* NAND_H */