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   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Partially based on linux/include/linux/mtd/nand.h                     *
   6  *   Copyright (C) 2000 David Woodhouse <dwmw2@mvhi.com>                   *
   7  *   Copyright (C) 2000 Steven J. Hill <sjhill@realitydiluted.com>         *
   8  *   Copyright (C) 2000 Thomas Gleixner <tglx@linutronix.de>               *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  ***************************************************************************/
  25 #ifndef NAND_H
  26 #define NAND_H
  27
  28 #include "flash.h"
  29
  30 struct nand_device_s;
  31
  32 typedef struct nand_flash_controller_s
  33 {
  34         char *name;
  35         int (*nand_device_command)(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
  36         int (*register_commands)(struct command_context_s *cmd_ctx);
  37         int (*init)(struct nand_device_s *device);
  38         int (*reset)(struct nand_device_s *device);
  39         int (*command)(struct nand_device_s *device, u8 command);
  40         int (*address)(struct nand_device_s *device, u8 address);
  41         int (*write_data)(struct nand_device_s *device, u16 data);
  42         int (*read_data)(struct nand_device_s *device, void *data);
  43         int (*write_block_data)(struct nand_device_s *device, u8 *data, int size);
  44         int (*read_block_data)(struct nand_device_s *device, u8 *data, int size);
  45         int (*write_page)(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  46         int (*read_page)(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  47         int (*controller_ready)(struct nand_device_s *device, int timeout);
  48         int (*nand_ready)(struct nand_device_s *device, int timeout);
  49 } nand_flash_controller_t;
  50
  51 typedef struct nand_block_s
  52 {
  53         u32 offset;
  54         u32 size;
  55         int is_erased;
  56         int is_bad;
  57 } nand_block_t;
  58
  59 typedef struct nand_device_s
  60 {
  61         nand_flash_controller_t *controller;
  62         void *controller_priv;
  63         struct nand_manufacturer_s *manufacturer;
  64         struct nand_info_s *device;
  65         int bus_width;
  66         int address_cycles;
  67         int page_size;
  68         int erase_size;
  69         int use_raw;
  70         int num_blocks;
  71         nand_block_t *blocks;
  72         struct nand_device_s *next;
  73 } nand_device_t;
  74
  75 /* NAND Flash Manufacturer ID Codes
  76  */
  77 enum
  78 {
  79         NAND_MFR_TOSHIBA = 0x98,
  80         NAND_MFR_SAMSUNG = 0xec,
  81         NAND_MFR_FUJITSU = 0x04,
  82         NAND_MFR_NATIONAL = 0x8f,
  83         NAND_MFR_RENESAS = 0x07,
  84         NAND_MFR_STMICRO = 0x20,
  85         NAND_MFR_HYNIX = 0xad,
  86 };
  87
  88 typedef struct nand_manufacturer_s
  89 {
  90     int id;
  91         char *name;
  92 } nand_manufacturer_t;
  93
  94 typedef struct nand_info_s
  95 {
  96         char *name;
  97         int id;
  98         int page_size;
  99         int chip_size;
 100         int erase_size;
 101         int options;
 102 } nand_info_t;
 103
 104 /* Option constants for bizarre disfunctionality and real features
 105  */
 106 enum {
 107         /* Chip can not auto increment pages */
 108         NAND_NO_AUTOINCR = 0x00000001,
 109
 110         /* Buswitdh is 16 bit */
 111         NAND_BUSWIDTH_16 = 0x00000002,
 112
 113         /* Device supports partial programming without padding */
 114         NAND_NO_PADDING = 0x00000004,
 115
 116         /* Chip has cache program function */
 117         NAND_CACHEPRG = 0x00000008,
 118
 119         /* Chip has copy back function */
 120         NAND_COPYBACK = 0x00000010,
 121
 122         /* AND Chip which has 4 banks and a confusing page / block
 123          * assignment. See Renesas datasheet for further information */
 124         NAND_IS_AND = 0x00000020,
 125
 126         /* Chip has a array of 4 pages which can be read without
 127          * additional ready /busy waits */
 128         NAND_4PAGE_ARRAY = 0x00000040,
 129
 130         /* Chip requires that BBT is periodically rewritten to prevent
 131          * bits from adjacent blocks from 'leaking' in altering data.
 132          * This happens with the Renesas AG-AND chips, possibly others.  */
 133         BBT_AUTO_REFRESH = 0x00000080,
 134
 135         /* Chip does not require ready check on read. True
 136          * for all large page devices, as they do not support
 137          * autoincrement.*/
 138         NAND_NO_READRDY = 0x00000100,
 139
 140         /* Options valid for Samsung large page devices */
 141         NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
 142
 143         /* Options for new chips with large page size. The pagesize and the
 144          * erasesize is determined from the extended id bytes
 145          */
 146         LP_OPTIONS = (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR),
 147         LP_OPTIONS16 = (LP_OPTIONS | NAND_BUSWIDTH_16),
 148 };
 149
 150 enum
 151 {
 152         /* Standard NAND flash commands */
 153         NAND_CMD_READ0 = 0x0,
 154         NAND_CMD_READ1 = 0x1,
 155         NAND_CMD_RNDOUT = 0x5,
 156         NAND_CMD_PAGEPROG = 0x10,
 157         NAND_CMD_READOOB = 0x50,
 158         NAND_CMD_ERASE1 = 0x60,
 159         NAND_CMD_STATUS = 0x70,
 160         NAND_CMD_STATUS_MULTI = 0x71,
 161         NAND_CMD_SEQIN = 0x80,
 162         NAND_CMD_RNDIN = 0x85,
 163         NAND_CMD_READID = 0x90,
 164         NAND_CMD_ERASE2 = 0xd0,
 165         NAND_CMD_RESET = 0xff,
 166
 167         /* Extended commands for large page devices */
 168         NAND_CMD_READSTART = 0x30,
 169         NAND_CMD_RNDOUTSTART = 0xE0,
 170         NAND_CMD_CACHEDPROG = 0x15,
 171 };
 172
 173 /* Status bits */
 174 enum
 175 {
 176         NAND_STATUS_FAIL = 0x01,
 177         NAND_STATUS_FAIL_N1 = 0x02,
 178         NAND_STATUS_TRUE_READY = 0x20,
 179         NAND_STATUS_READY = 0x40,
 180         NAND_STATUS_WP = 0x80,
 181 };
 182
 183 /* OOB (spare) data formats */
 184 enum oob_formats
 185 {
 186         NAND_OOB_NONE = 0x0,    /* no OOB data at all */
 187         NAND_OOB_RAW = 0x1,             /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */
 188         NAND_OOB_ONLY = 0x2,    /* only OOB data */
 189         NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
 190         NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
 191         NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
 192         NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
 193 };
 194
 195 /* Function prototypes */
 196 extern nand_device_t *get_nand_device_by_num(int num);
 197 extern int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
 198 extern int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
 199 extern int nand_read_status(struct nand_device_s *device, u8 *status);
 200
 201 extern int nand_register_commands(struct command_context_s *cmd_ctx);
 202 extern int nand_init(struct command_context_s *cmd_ctx);
 203
 204 #define         ERROR_NAND_DEVICE_INVALID               (-1100)
 205 #define         ERROR_NAND_OPERATION_FAILED             (-1101)
 206 #define         ERROR_NAND_OPERATION_TIMEOUT    (-1102)
 207 #define         ERROR_NAND_OPERATION_NOT_SUPPORTED      (-1103)
 208 #define         ERROR_NAND_DEVICE_NOT_PROBED    (-1104)
 209 #define         ERROR_NAND_ERROR_CORRECTION_FAILED      (-1105)
 210
 211 #endif /* NAND_H */