1 /***************************************************************************
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2 * Copyright (C) 2007 by Dominic Rath *
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3 * Dominic.Rath@gmx.de *
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5 * partially based on *
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6 * drivers/mtd/nand_ids.c *
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8 * Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de) *
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10 * This program is free software; you can redistribute it and/or modify *
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11 * it under the terms of the GNU General Public License as published by *
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12 * the Free Software Foundation; either version 2 of the License, or *
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13 * (at your option) any later version. *
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15 * This program is distributed in the hope that it will be useful, *
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16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
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17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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18 * GNU General Public License for more details. *
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20 * You should have received a copy of the GNU General Public License *
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21 * along with this program; if not, write to the *
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22 * Free Software Foundation, Inc., *
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23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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24 ***************************************************************************/
\r
25 #ifdef HAVE_CONFIG_H
\r
29 #include "replacements.h"
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34 #include <inttypes.h>
\r
40 #include "time_support.h"
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44 int nand_register_commands(struct command_context_s *cmd_ctx);
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45 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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46 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
47 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
48 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
49 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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50 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
51 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
52 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
54 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
56 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
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57 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
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58 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
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60 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
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61 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
\r
63 /* NAND flash controller
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65 extern nand_flash_controller_t lpc3180_nand_controller;
\r
66 extern nand_flash_controller_t s3c2410_nand_controller;
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67 extern nand_flash_controller_t s3c2412_nand_controller;
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68 extern nand_flash_controller_t s3c2440_nand_controller;
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69 extern nand_flash_controller_t s3c2443_nand_controller;
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71 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
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73 nand_flash_controller_t *nand_flash_controllers[] =
\r
75 &lpc3180_nand_controller,
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76 &s3c2410_nand_controller,
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77 &s3c2412_nand_controller,
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78 &s3c2440_nand_controller,
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79 &s3c2443_nand_controller,
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80 /* &boundary_scan_nand_controller, */
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84 /* configured NAND devices and NAND Flash command handler */
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85 nand_device_t *nand_devices = NULL;
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86 static command_t *nand_cmd;
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90 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
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93 * Pagesize; 0, 256, 512
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94 * 0 get this information from the extended chip ID
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95 * 256 256 Byte page size
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96 * 512 512 Byte page size
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98 nand_info_t nand_flash_ids[] =
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100 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
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101 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
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102 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
\r
103 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
\r
104 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
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105 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
\r
106 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
\r
107 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
\r
108 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
\r
109 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
\r
111 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
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112 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
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113 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
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114 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
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116 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
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117 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
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118 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
\r
119 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
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121 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
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122 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
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123 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
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124 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
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126 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
\r
127 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
\r
128 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
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129 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
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131 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
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132 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
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133 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
\r
134 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
\r
135 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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136 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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137 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
\r
139 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
\r
141 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
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142 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
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143 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
\r
144 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
\r
146 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
\r
147 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
\r
148 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
\r
149 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
\r
151 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
\r
152 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
\r
153 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
\r
154 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
\r
156 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
\r
157 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
\r
158 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
\r
159 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
\r
161 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
\r
162 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
\r
163 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
\r
164 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
\r
166 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
\r
167 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
\r
168 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
\r
169 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
\r
174 /* Manufacturer ID list
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176 nand_manufacturer_t nand_manuf_ids[] =
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179 {NAND_MFR_TOSHIBA, "Toshiba"},
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180 {NAND_MFR_SAMSUNG, "Samsung"},
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181 {NAND_MFR_FUJITSU, "Fujitsu"},
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182 {NAND_MFR_NATIONAL, "National"},
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183 {NAND_MFR_RENESAS, "Renesas"},
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184 {NAND_MFR_STMICRO, "ST Micro"},
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185 {NAND_MFR_HYNIX, "Hynix"},
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189 /* nand device <nand_controller> [controller options]
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191 int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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198 WARNING("incomplete flash device nand configuration");
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199 return ERROR_FLASH_BANK_INVALID;
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202 for (i = 0; nand_flash_controllers[i]; i++)
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204 nand_device_t *p, *c;
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206 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
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208 /* register flash specific commands */
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209 if (nand_flash_controllers[i]->register_commands(cmd_ctx) != ERROR_OK)
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211 ERROR("couldn't register '%s' commands", args[0]);
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215 c = malloc(sizeof(nand_device_t));
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217 c->controller = nand_flash_controllers[i];
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218 c->controller_priv = NULL;
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219 c->manufacturer = NULL;
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222 c->address_cycles = 0;
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227 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
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229 ERROR("'%s' driver rejected nand flash", c->controller->name);
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234 /* put NAND device in linked list */
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237 /* find last flash device */
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238 for (p = nand_devices; p && p->next; p = p->next);
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251 /* no valid NAND controller was found (i.e. the configuration option,
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252 * didn't match one of the compiled-in controllers)
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254 ERROR("No valid NAND flash controller found (%s)", args[0]);
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255 ERROR("compiled-in NAND flash controllers:");
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256 for (i = 0; nand_flash_controllers[i]; i++)
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258 ERROR("%i: %s", i, nand_flash_controllers[i]->name);
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264 int nand_register_commands(struct command_context_s *cmd_ctx)
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266 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
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268 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
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273 int nand_init(struct command_context_s *cmd_ctx)
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277 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
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278 "list configured NAND flash devices");
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279 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
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280 "print info about NAND flash device <num>");
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281 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
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282 "identify NAND flash device <num>");
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283 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
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284 "check NAND flash device <num> for bad blocks [<first> <last>]");
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285 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
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286 "erase blocks on NAND flash device <num> <first> <last>");
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287 register_command(cmd_ctx, nand_cmd, "copy", handle_nand_copy_command, COMMAND_EXEC,
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288 "copy from NAND flash device <num> <offset> <length> <ram-address>");
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289 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
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290 "dump from NAND flash device <num> <filename> <offset> <size> [options]");
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291 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
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292 "write to NAND flash device <num> <filename> <offset> [options]");
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293 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
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294 "raw access to NAND flash device <num> ['enable'|'disable']");
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300 nand_device_t *get_nand_device_by_num(int num)
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305 for (p = nand_devices; p; p = p->next)
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316 int nand_build_bbt(struct nand_device_s *device, int first, int last)
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324 if ((first < 0) || (first >= device->num_blocks))
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327 if ((last >= device->num_blocks) || (last == -1))
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328 last = device->num_blocks - 1;
\r
330 for (i = first; i < last; i++)
\r
332 nand_read_page(device, page, NULL, 0, oob, 6);
\r
334 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
\r
335 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
\r
336 ((device->page_size == 2048) && (oob[0] != 0xff))))
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338 WARNING("invalid block: %i", i);
\r
339 device->blocks[i].is_bad = 1;
\r
343 device->blocks[i].is_bad = 0;
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346 page += (device->erase_size / device->page_size);
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352 int nand_read_status(struct nand_device_s *device, u8 *status)
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354 if (!device->device)
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355 return ERROR_NAND_DEVICE_NOT_PROBED;
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357 /* Send read status command */
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358 device->controller->command(device, NAND_CMD_STATUS);
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363 if (device->device->options & NAND_BUSWIDTH_16)
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366 device->controller->read_data(device, &data);
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367 *status = data & 0xff;
\r
371 device->controller->read_data(device, status);
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377 int nand_probe(struct nand_device_s *device)
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379 u8 manufacturer_id, device_id;
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384 /* clear device data */
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385 device->device = NULL;
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386 device->manufacturer = NULL;
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388 /* clear device parameters */
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389 device->bus_width = 0;
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390 device->address_cycles = 0;
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391 device->page_size = 0;
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392 device->erase_size = 0;
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394 /* initialize controller (device parameters are zero, use controller default) */
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395 if ((retval = device->controller->init(device) != ERROR_OK))
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399 case ERROR_NAND_OPERATION_FAILED:
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400 DEBUG("controller initialization failed");
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401 return ERROR_NAND_OPERATION_FAILED;
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402 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
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403 ERROR("BUG: controller reported that it doesn't support default parameters");
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404 return ERROR_NAND_OPERATION_FAILED;
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406 ERROR("BUG: unknown controller initialization failure");
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407 return ERROR_NAND_OPERATION_FAILED;
\r
411 device->controller->command(device, NAND_CMD_RESET);
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412 device->controller->reset(device);
\r
414 device->controller->command(device, NAND_CMD_READID);
\r
415 device->controller->address(device, 0x0);
\r
417 if (device->bus_width == 8)
\r
419 device->controller->read_data(device, &manufacturer_id);
\r
420 device->controller->read_data(device, &device_id);
\r
425 device->controller->read_data(device, &data_buf);
\r
426 manufacturer_id = data_buf & 0xff;
\r
427 device->controller->read_data(device, &data_buf);
\r
428 device_id = data_buf & 0xff;
\r
431 for (i = 0; nand_flash_ids[i].name; i++)
\r
433 if (nand_flash_ids[i].id == device_id)
\r
435 device->device = &nand_flash_ids[i];
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440 for (i = 0; nand_manuf_ids[i].name; i++)
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442 if (nand_manuf_ids[i].id == manufacturer_id)
\r
444 device->manufacturer = &nand_manuf_ids[i];
\r
449 if (!device->manufacturer)
\r
451 device->manufacturer = &nand_manuf_ids[0];
\r
452 device->manufacturer->id = manufacturer_id;
\r
455 if (!device->device)
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457 ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
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458 manufacturer_id, device_id);
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459 return ERROR_NAND_OPERATION_FAILED;
\r
462 DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
\r
464 /* initialize device parameters */
\r
467 if (device->device->options & NAND_BUSWIDTH_16)
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468 device->bus_width = 16;
\r
470 device->bus_width = 8;
\r
472 /* Do we need extended device probe information? */
\r
473 if (device->device->page_size == 0 ||
\r
474 device->device->erase_size == 0)
\r
476 if (device->bus_width == 8)
\r
478 device->controller->read_data(device, id_buff+3);
\r
479 device->controller->read_data(device, id_buff+4);
\r
480 device->controller->read_data(device, id_buff+5);
\r
486 device->controller->read_data(device, &data_buf);
\r
487 id_buff[3] = data_buf;
\r
489 device->controller->read_data(device, &data_buf);
\r
490 id_buff[4] = data_buf;
\r
492 device->controller->read_data(device, &data_buf);
\r
493 id_buff[5] = data_buf >> 8;
\r
498 if (device->device->page_size == 0)
\r
500 device->page_size = 1 << (10 + (id_buff[4] & 3));
\r
502 else if (device->device->page_size == 256)
\r
504 ERROR("NAND flashes with 256 byte pagesize are not supported");
\r
505 return ERROR_NAND_OPERATION_FAILED;
\r
509 device->page_size = device->device->page_size;
\r
512 /* number of address cycles */
\r
513 if (device->page_size <= 512)
\r
515 /* small page devices */
\r
516 if (device->device->chip_size <= 32)
\r
517 device->address_cycles = 3;
\r
518 else if (device->device->chip_size <= 8*1024)
\r
519 device->address_cycles = 4;
\r
522 ERROR("BUG: small page NAND device with more than 8 GiB encountered");
\r
523 device->address_cycles = 5;
\r
528 /* large page devices */
\r
529 if (device->device->chip_size <= 128)
\r
530 device->address_cycles = 4;
\r
531 else if (device->device->chip_size <= 32*1024)
\r
532 device->address_cycles = 5;
\r
535 ERROR("BUG: small page NAND device with more than 32 GiB encountered");
\r
536 device->address_cycles = 6;
\r
541 if (device->device->erase_size == 0)
\r
543 switch ((id_buff[4] >> 4) & 3) {
\r
545 device->erase_size = 64 << 10;
\r
548 device->erase_size = 128 << 10;
\r
551 device->erase_size = 256 << 10;
\r
554 device->erase_size =512 << 10;
\r
560 device->erase_size = device->device->erase_size;
\r
563 /* initialize controller, but leave parameters at the controllers default */
\r
564 if ((retval = device->controller->init(device) != ERROR_OK))
\r
568 case ERROR_NAND_OPERATION_FAILED:
\r
569 DEBUG("controller initialization failed");
\r
570 return ERROR_NAND_OPERATION_FAILED;
\r
571 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
\r
572 ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
\r
573 device->bus_width, device->address_cycles, device->page_size);
\r
574 return ERROR_NAND_OPERATION_FAILED;
\r
576 ERROR("BUG: unknown controller initialization failure");
\r
577 return ERROR_NAND_OPERATION_FAILED;
\r
581 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
\r
582 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
\r
584 for (i = 0; i < device->num_blocks; i++)
\r
586 device->blocks[i].size = device->erase_size;
\r
587 device->blocks[i].offset = i * device->erase_size;
\r
588 device->blocks[i].is_erased = -1;
\r
589 device->blocks[i].is_bad = -1;
\r
595 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
\r
602 if (!device->device)
\r
603 return ERROR_NAND_DEVICE_NOT_PROBED;
\r
605 if ((first_block < 0) || (last_block > device->num_blocks))
\r
606 return ERROR_INVALID_ARGUMENTS;
\r
608 /* make sure we know if a block is bad before erasing it */
\r
609 for (i = first_block; i <= last_block; i++)
\r
611 if (device->blocks[i].is_bad == -1)
\r
613 nand_build_bbt(device, i, last_block);
\r
618 for (i = first_block; i <= last_block; i++)
\r
620 /* Send erase setup command */
\r
621 device->controller->command(device, NAND_CMD_ERASE1);
\r
623 page = i * (device->erase_size / device->page_size);
\r
625 /* Send page address */
\r
626 if (device->page_size <= 512)
\r
629 device->controller->address(device, page & 0xff);
\r
630 device->controller->address(device, (page >> 8) & 0xff);
\r
632 /* 3rd cycle only on devices with more than 32 MiB */
\r
633 if (device->address_cycles >= 4)
\r
634 device->controller->address(device, (page >> 16) & 0xff);
\r
636 /* 4th cycle only on devices with more than 8 GiB */
\r
637 if (device->address_cycles >= 5)
\r
638 device->controller->address(device, (page >> 24) & 0xff);
\r
643 device->controller->address(device, page & 0xff);
\r
644 device->controller->address(device, (page >> 8) & 0xff);
\r
646 /* 3rd cycle only on devices with more than 128 MiB */
\r
647 if (device->address_cycles >= 5)
\r
648 device->controller->address(device, (page >> 16) & 0xff);
\r
651 /* Send erase confirm command */
\r
652 device->controller->command(device, NAND_CMD_ERASE2);
\r
654 if (!device->controller->nand_ready(device, 1000))
\r
656 ERROR("timeout waiting for NAND flash block erase to complete");
\r
657 return ERROR_NAND_OPERATION_TIMEOUT;
\r
660 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
\r
662 ERROR("couldn't read status");
\r
663 return ERROR_NAND_OPERATION_FAILED;
\r
668 ERROR("erase operation didn't pass, status: 0x%2.2x", status);
\r
669 return ERROR_NAND_OPERATION_FAILED;
\r
676 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
\r
680 if (!device->device)
\r
681 return ERROR_NAND_DEVICE_NOT_PROBED;
\r
683 if (address % device->page_size)
\r
685 ERROR("reads need to be page aligned");
\r
686 return ERROR_NAND_OPERATION_FAILED;
\r
689 page = malloc(device->page_size);
\r
691 while (data_size > 0 )
\r
693 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
\r
697 page_address = address / device->page_size;
\r
699 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
\r
701 memcpy(data, page, thisrun_size);
\r
703 address += thisrun_size;
\r
704 data += thisrun_size;
\r
705 data_size -= thisrun_size;
\r
713 int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
\r
717 if (!device->device)
\r
718 return ERROR_NAND_DEVICE_NOT_PROBED;
\r
720 if (address % device->page_size)
\r
722 ERROR("writes need to be page aligned");
\r
723 return ERROR_NAND_OPERATION_FAILED;
\r
726 page = malloc(device->page_size);
\r
728 while (data_size > 0 )
\r
730 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
\r
733 memset(page, 0xff, device->page_size);
\r
734 memcpy(page, data, thisrun_size);
\r
736 page_address = address / device->page_size;
\r
738 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
\r
740 address += thisrun_size;
\r
741 data += thisrun_size;
\r
742 data_size -= thisrun_size;
\r
750 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
\r
752 if (!device->device)
\r
753 return ERROR_NAND_DEVICE_NOT_PROBED;
\r
755 if (device->use_raw || device->controller->write_page == NULL)
\r
756 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
\r
758 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
\r
761 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
\r
763 if (!device->device)
\r
764 return ERROR_NAND_DEVICE_NOT_PROBED;
\r
766 if (device->use_raw || device->controller->read_page == NULL)
\r
767 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
\r
769 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
\r
772 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
\r
776 if (!device->device)
\r
777 return ERROR_NAND_DEVICE_NOT_PROBED;
\r
779 if (device->page_size <= 512)
\r
781 /* small page device */
\r
783 device->controller->command(device, NAND_CMD_READ0);
\r
785 device->controller->command(device, NAND_CMD_READOOB);
\r
787 /* column (always 0, we start at the beginning of a page/OOB area) */
\r
788 device->controller->address(device, 0x0);
\r
791 device->controller->address(device, page & 0xff);
\r
792 device->controller->address(device, (page >> 8) & 0xff);
\r
794 /* 4th cycle only on devices with more than 32 MiB */
\r
795 if (device->address_cycles >= 4)
\r
796 device->controller->address(device, (page >> 16) & 0xff);
\r
798 /* 5th cycle only on devices with more than 8 GiB */
\r
799 if (device->address_cycles >= 5)
\r
800 device->controller->address(device, (page >> 24) & 0xff);
\r
804 /* large page device */
\r
805 device->controller->command(device, NAND_CMD_READ0);
\r
807 /* column (0 when we start at the beginning of a page,
\r
808 * or 2048 for the beginning of OOB area)
\r
810 device->controller->address(device, 0x0);
\r
811 device->controller->address(device, 0x8);
\r
814 device->controller->address(device, page & 0xff);
\r
815 device->controller->address(device, (page >> 8) & 0xff);
\r
817 /* 5th cycle only on devices with more than 128 MiB */
\r
818 if (device->address_cycles >= 5)
\r
819 device->controller->address(device, (page >> 16) & 0xff);
\r
821 /* large page devices need a start command */
\r
822 device->controller->command(device, NAND_CMD_READSTART);
\r
825 if (!device->controller->nand_ready(device, 100))
\r
826 return ERROR_NAND_OPERATION_TIMEOUT;
\r
830 if (device->controller->read_block_data != NULL)
\r
831 (device->controller->read_block_data)(device, data, data_size);
\r
834 for (i = 0; i < data_size;)
\r
836 if (device->device->options & NAND_BUSWIDTH_16)
\r
838 device->controller->read_data(device, data);
\r
844 device->controller->read_data(device, data);
\r
854 if (device->controller->read_block_data != NULL)
\r
855 (device->controller->read_block_data)(device, oob, oob_size);
\r
858 for (i = 0; i < oob_size;)
\r
860 if (device->device->options & NAND_BUSWIDTH_16)
\r
862 device->controller->read_data(device, oob);
\r
868 device->controller->read_data(device, oob);
\r
879 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
\r
885 if (!device->device)
\r
886 return ERROR_NAND_DEVICE_NOT_PROBED;
\r
888 device->controller->command(device, NAND_CMD_SEQIN);
\r
890 if (device->page_size <= 512)
\r
892 /* column (always 0, we start at the beginning of a page/OOB area) */
\r
893 device->controller->address(device, 0x0);
\r
896 device->controller->address(device, page & 0xff);
\r
897 device->controller->address(device, (page >> 8) & 0xff);
\r
899 /* 4th cycle only on devices with more than 32 MiB */
\r
900 if (device->address_cycles >= 4)
\r
901 device->controller->address(device, (page >> 16) & 0xff);
\r
903 /* 5th cycle only on devices with more than 8 GiB */
\r
904 if (device->address_cycles >= 5)
\r
905 device->controller->address(device, (page >> 24) & 0xff);
\r
909 /* column (0 when we start at the beginning of a page,
\r
910 * or 2048 for the beginning of OOB area)
\r
912 device->controller->address(device, 0x0);
\r
913 device->controller->address(device, 0x8);
\r
916 device->controller->address(device, page & 0xff);
\r
917 device->controller->address(device, (page >> 8) & 0xff);
\r
919 /* 5th cycle only on devices with more than 128 MiB */
\r
920 if (device->address_cycles >= 5)
\r
921 device->controller->address(device, (page >> 16) & 0xff);
\r
926 if (device->controller->write_block_data != NULL)
\r
927 (device->controller->write_block_data)(device, data, data_size);
\r
930 for (i = 0; i < data_size;)
\r
932 if (device->device->options & NAND_BUSWIDTH_16)
\r
934 u16 data_buf = le_to_h_u16(data);
\r
935 device->controller->write_data(device, data_buf);
\r
941 device->controller->write_data(device, *data);
\r
951 if (device->controller->write_block_data != NULL)
\r
952 (device->controller->write_block_data)(device, oob, oob_size);
\r
955 for (i = 0; i < oob_size;)
\r
957 if (device->device->options & NAND_BUSWIDTH_16)
\r
959 u16 oob_buf = le_to_h_u16(data);
\r
960 device->controller->write_data(device, oob_buf);
\r
966 device->controller->write_data(device, *oob);
\r
974 device->controller->command(device, NAND_CMD_PAGEPROG);
\r
976 if (!device->controller->nand_ready(device, 100))
\r
977 return ERROR_NAND_OPERATION_TIMEOUT;
\r
979 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
\r
981 ERROR("couldn't read status");
\r
982 return ERROR_NAND_OPERATION_FAILED;
\r
985 if (status & NAND_STATUS_FAIL)
\r
987 ERROR("write operation didn't pass, status: 0x%2.2x", status);
\r
988 return ERROR_NAND_OPERATION_FAILED;
\r
994 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
1001 command_print(cmd_ctx, "no NAND flash devices configured");
\r
1005 for (p = nand_devices; p; p = p->next)
\r
1008 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
\r
1009 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
\r
1011 command_print(cmd_ctx, "#%i: not probed");
\r
1017 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
1025 if ((argc < 1) || (argc > 3))
\r
1027 return ERROR_COMMAND_SYNTAX_ERROR;
\r
1033 first = last = strtoul(args[1], NULL, 0);
\r
1035 else if (argc == 3)
\r
1037 first = strtoul(args[1], NULL, 0);
\r
1038 last = strtoul(args[2], NULL, 0);
\r
1041 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
\r
1046 if (first >= p->num_blocks)
\r
1047 first = p->num_blocks - 1;
\r
1049 if (last >= p->num_blocks)
\r
1050 last = p->num_blocks - 1;
\r
1052 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
\r
1053 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
\r
1055 for (j = first; j <= last; j++)
\r
1057 char *erase_state, *bad_state;
\r
1059 if (p->blocks[j].is_erased == 0)
\r
1060 erase_state = "not erased";
\r
1061 else if (p->blocks[j].is_erased == 1)
\r
1062 erase_state = "erased";
\r
1064 erase_state = "erase state unknown";
\r
1066 if (p->blocks[j].is_bad == 0)
\r
1068 else if (p->blocks[j].is_bad == 1)
\r
1069 bad_state = " (marked bad)";
\r
1071 bad_state = " (block condition unknown)";
\r
1073 command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
\r
1074 j, p->blocks[j].offset, p->blocks[j].size / 1024,
\r
1075 erase_state, bad_state);
\r
1080 command_print(cmd_ctx, "#%i: not probed");
\r
1087 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
1094 return ERROR_COMMAND_SYNTAX_ERROR;
\r
1097 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
\r
1100 if ((retval = nand_probe(p)) == ERROR_OK)
\r
1102 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
\r
1104 else if (retval == ERROR_NAND_OPERATION_FAILED)
\r
1106 command_print(cmd_ctx, "probing failed for NAND flash device");
\r
1110 command_print(cmd_ctx, "unknown error when probing NAND flash device");
\r
1115 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
\r
1121 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
1128 return ERROR_COMMAND_SYNTAX_ERROR;
\r
1132 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
\r
1135 int first = strtoul(args[1], NULL, 0);
\r
1136 int last = strtoul(args[2], NULL, 0);
\r
1138 if ((retval = nand_erase(p, first, last)) == ERROR_OK)
\r
1140 command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
\r
1142 else if (retval == ERROR_NAND_OPERATION_FAILED)
\r
1144 command_print(cmd_ctx, "erase failed");
\r
1148 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
\r
1153 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
\r
1159 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
1166 if ((argc < 1) || (argc > 3) || (argc == 2))
\r
1168 return ERROR_COMMAND_SYNTAX_ERROR;
\r
1174 first = strtoul(args[1], NULL, 0);
\r
1175 last = strtoul(args[2], NULL, 0);
\r
1178 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
\r
1181 if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
\r
1183 command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks", p->device->name);
\r
1185 else if (retval == ERROR_NAND_OPERATION_FAILED)
\r
1187 command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
\r
1191 command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
\r
1196 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
\r
1202 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
1208 return ERROR_COMMAND_SYNTAX_ERROR;
\r
1212 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
\r
1219 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
\r
1225 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
1230 enum oob_formats oob_format = NAND_OOB_NONE;
\r
1234 duration_t duration;
\r
1235 char *duration_text;
\r
1241 return ERROR_COMMAND_SYNTAX_ERROR;
\r
1245 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
\r
1249 u32 page_size = 0;
\r
1253 duration_start_measure(&duration);
\r
1254 offset = strtoul(args[2], NULL, 0);
\r
1259 for (i = 3; i < argc; i++)
\r
1261 if (!strcmp(args[i], "oob_raw"))
\r
1262 oob_format |= NAND_OOB_RAW;
\r
1263 else if (!strcmp(args[i], "oob_only"))
\r
1264 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
\r
1267 command_print(cmd_ctx, "unknown option: %s", args[i]);
\r
1272 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
\r
1274 command_print(cmd_ctx, "file open error: %s", fileio.error_str);
\r
1278 buf_cnt = binary_size = fileio.size;
\r
1280 if (!(oob_format & NAND_OOB_ONLY))
\r
1282 page_size = p->page_size;
\r
1283 page = malloc(p->page_size);
\r
1286 if (oob_format & NAND_OOB_RAW)
\r
1288 if (p->page_size == 512)
\r
1290 else if (p->page_size == 2048)
\r
1292 oob = malloc(oob_size);
\r
1295 if (offset % p->page_size)
\r
1297 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
\r
1301 while (buf_cnt > 0)
\r
1307 fileio_read(&fileio, page_size, page, &size_read);
\r
1308 buf_cnt -= size_read;
\r
1309 if (size_read < page_size)
\r
1311 memset(page + size_read, 0xff, page_size - size_read);
\r
1317 fileio_read(&fileio, oob_size, oob, &size_read);
\r
1318 buf_cnt -= size_read;
\r
1319 if (size_read < oob_size)
\r
1321 memset(oob + size_read, 0xff, oob_size - size_read);
\r
1325 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
\r
1327 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
\r
1328 args[1], args[0], offset);
\r
1331 offset += page_size;
\r
1334 fileio_close(&fileio);
\r
1336 duration_stop_measure(&duration, &duration_text);
\r
1337 command_print(cmd_ctx, "wrote file %s to NAND flash %s at offset 0x%8.8x in %s",
\r
1338 args[1], args[0], offset, duration_text);
\r
1339 free(duration_text);
\r
1343 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
\r
1349 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
1355 return ERROR_COMMAND_SYNTAX_ERROR;
\r
1358 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
\r
1364 duration_t duration;
\r
1365 char *duration_text;
\r
1369 u32 page_size = 0;
\r
1372 u32 address = strtoul(args[2], NULL, 0);
\r
1373 u32 size = strtoul(args[3], NULL, 0);
\r
1374 u32 bytes_done = 0;
\r
1375 enum oob_formats oob_format = NAND_OOB_NONE;
\r
1380 for (i = 4; i < argc; i++)
\r
1382 if (!strcmp(args[i], "oob_raw"))
\r
1383 oob_format |= NAND_OOB_RAW;
\r
1384 else if (!strcmp(args[i], "oob_only"))
\r
1385 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
\r
1387 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
\r
1391 if ((address % p->page_size) || (size % p->page_size))
\r
1393 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
\r
1397 if (!(oob_format & NAND_OOB_ONLY))
\r
1399 page_size = p->page_size;
\r
1400 page = malloc(p->page_size);
\r
1403 if (oob_format & NAND_OOB_RAW)
\r
1405 if (p->page_size == 512)
\r
1407 else if (p->page_size == 2048)
\r
1409 oob = malloc(oob_size);
\r
1412 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
\r
1414 command_print(cmd_ctx, "dump_image error: %s", fileio.error_str);
\r
1418 duration_start_measure(&duration);
\r
1423 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
\r
1425 command_print(cmd_ctx, "reading NAND flash page failed");
\r
1431 fileio_write(&fileio, page_size, page, &size_written);
\r
1432 bytes_done += page_size;
\r
1437 fileio_write(&fileio, oob_size, oob, &size_written);
\r
1438 bytes_done += oob_size;
\r
1441 size -= p->page_size;
\r
1442 address += p->page_size;
\r
1451 fileio_close(&fileio);
\r
1453 duration_stop_measure(&duration, &duration_text);
\r
1454 command_print(cmd_ctx, "dumped %"PRIi64" byte in %s", fileio.size, duration_text);
\r
1455 free(duration_text);
\r
1459 command_print(cmd_ctx, "#%i: not probed");
\r
1464 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
\r
1470 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
1474 if ((argc < 1) || (argc > 2))
\r
1476 return ERROR_COMMAND_SYNTAX_ERROR;
\r
1479 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
\r
1486 if (strcmp("enable", args[1]) == 0)
\r
1490 else if (strcmp("disable", args[1]) == 0)
\r
1496 return ERROR_COMMAND_SYNTAX_ERROR;
\r
1500 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
\r
1504 command_print(cmd_ctx, "#%i: not probed");
\r
1509 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
\r