flash/nor/at91samd: Use 32-bit register writes for ST-Link compat
[fw/openocd] / src / flash / nand / s3c24xx.h
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 /***************************************************************************
4  *   Copyright (C) 2007, 2008 by Ben Dooks                                 *
5  *   ben@fluff.org                                                         *
6  ***************************************************************************/
7
8 #ifndef OPENOCD_FLASH_NAND_S3C24XX_H
9 #define OPENOCD_FLASH_NAND_S3C24XX_H
10
11 /*
12  * S3C24XX Series OpenOCD NAND Flash controller support.
13  *
14  * Many thanks to Simtec Electronics for sponsoring this work.
15  */
16
17 #include "imp.h"
18 #include "s3c24xx_regs.h"
19 #include <target/target.h>
20
21 struct s3c24xx_nand_controller {
22         /* register addresses */
23         uint32_t                 cmd;
24         uint32_t                 addr;
25         uint32_t                 data;
26         uint32_t                 nfstat;
27 };
28
29 /* Default to using the un-translated NAND register based address */
30 #undef S3C2410_NFREG
31 #define S3C2410_NFREG(x) ((x) + 0x4e000000)
32
33 #define S3C24XX_DEVICE_COMMAND() \
34                 COMMAND_HELPER(s3c24xx_nand_device_command, \
35                                 struct nand_device *nand, \
36                                 struct s3c24xx_nand_controller **info)
37
38 S3C24XX_DEVICE_COMMAND();
39
40 #define CALL_S3C24XX_DEVICE_COMMAND(d, i) \
41         do { \
42                 int retval = CALL_COMMAND_HANDLER(s3c24xx_nand_device_command, d, i); \
43                 if (retval != ERROR_OK) \
44                         return retval; \
45         } while (0)
46
47 int s3c24xx_reset(struct nand_device *nand);
48
49 int s3c24xx_command(struct nand_device *nand, uint8_t command);
50 int s3c24xx_address(struct nand_device *nand, uint8_t address);
51
52 int s3c24xx_write_data(struct nand_device *nand, uint16_t data);
53 int s3c24xx_read_data(struct nand_device *nand, void *data);
54
55 #define s3c24xx_write_page NULL
56 #define s3c24xx_read_page NULL
57
58 /* code shared between different controllers */
59
60 int s3c2440_nand_ready(struct nand_device *nand, int timeout);
61
62 int s3c2440_read_block_data(struct nand_device *nand,
63                 uint8_t *data, int data_size);
64 int s3c2440_write_block_data(struct nand_device *nand,
65                 uint8_t *data, int data_size);
66
67 #endif /* OPENOCD_FLASH_NAND_S3C24XX_H */