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   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Marvell Semiconductors, Inc.                    *
   3  *   Written by Nicolas Pitre <nico at marvell.com>                        *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 /*
  20  * NAND controller interface for Marvell Orion/Kirkwood SoCs.
  21  */
  22
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "imp.h"
  28 #include "arm_io.h"
  29 #include <target/arm.h>
  30
  31 struct orion_nand_controller {
  32         struct arm_nand_data    io;
  33
  34         uint32_t                cmd;
  35         uint32_t                addr;
  36         uint32_t                data;
  37 };
  38
  39 #define CHECK_HALTED \
  40         do { \
  41                 if (target->state != TARGET_HALTED) { \
  42                         LOG_ERROR("NAND flash access requires halted target"); \
  43                         return ERROR_NAND_OPERATION_FAILED; \
  44                 } \
  45         } while (0)
  46
  47 static int orion_nand_command(struct nand_device *nand, uint8_t command)
  48 {
  49         struct orion_nand_controller *hw = nand->controller_priv;
  50         struct target *target = nand->target;
  51
  52         CHECK_HALTED;
  53         target_write_u8(target, hw->cmd, command);
  54         return ERROR_OK;
  55 }
  56
  57 static int orion_nand_address(struct nand_device *nand, uint8_t address)
  58 {
  59         struct orion_nand_controller *hw = nand->controller_priv;
  60         struct target *target = nand->target;
  61
  62         CHECK_HALTED;
  63         target_write_u8(target, hw->addr, address);
  64         return ERROR_OK;
  65 }
  66
  67 static int orion_nand_read(struct nand_device *nand, void *data)
  68 {
  69         struct orion_nand_controller *hw = nand->controller_priv;
  70         struct target *target = nand->target;
  71
  72         CHECK_HALTED;
  73         target_read_u8(target, hw->data, data);
  74         return ERROR_OK;
  75 }
  76
  77 static int orion_nand_write(struct nand_device *nand, uint16_t data)
  78 {
  79         struct orion_nand_controller *hw = nand->controller_priv;
  80         struct target *target = nand->target;
  81
  82         CHECK_HALTED;
  83         target_write_u8(target, hw->data, data);
  84         return ERROR_OK;
  85 }
  86
  87 static int orion_nand_slow_block_write(struct nand_device *nand, uint8_t *data, int size)
  88 {
  89         while (size--)
  90                 orion_nand_write(nand, *data++);
  91         return ERROR_OK;
  92 }
  93
  94 static int orion_nand_fast_block_write(struct nand_device *nand, uint8_t *data, int size)
  95 {
  96         struct orion_nand_controller *hw = nand->controller_priv;
  97         int retval;
  98
  99         hw->io.chunk_size = nand->page_size;
 100
 101         retval = arm_nandwrite(&hw->io, data, size);
 102         if (retval == ERROR_NAND_NO_BUFFER)
 103                 retval = orion_nand_slow_block_write(nand, data, size);
 104
 105         return retval;
 106 }
 107
 108 static int orion_nand_reset(struct nand_device *nand)
 109 {
 110         return orion_nand_command(nand, NAND_CMD_RESET);
 111 }
 112
 113 NAND_DEVICE_COMMAND_HANDLER(orion_nand_device_command)
 114 {
 115         struct orion_nand_controller *hw;
 116         uint32_t base;
 117         uint8_t ale, cle;
 118
 119         if (CMD_ARGC != 3)
 120                 return ERROR_COMMAND_SYNTAX_ERROR;
 121
 122         hw = calloc(1, sizeof(*hw));
 123         if (!hw) {
 124                 LOG_ERROR("no memory for nand controller");
 125                 return ERROR_NAND_DEVICE_INVALID;
 126         }
 127
 128         nand->controller_priv = hw;
 129
 130         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], base);
 131         cle = 0;
 132         ale = 1;
 133
 134         hw->data = base;
 135         hw->cmd = base + (1 << cle);
 136         hw->addr = base + (1 << ale);
 137
 138         hw->io.target = nand->target;
 139         hw->io.data = hw->data;
 140         hw->io.op = ARM_NAND_NONE;
 141
 142         return ERROR_OK;
 143 }
 144
 145 static int orion_nand_init(struct nand_device *nand)
 146 {
 147         return ERROR_OK;
 148 }
 149
 150 struct nand_flash_controller orion_nand_controller = {
 151         .name = "orion",
 152         .usage = "<target_id> <NAND_address>",
 153         .command = orion_nand_command,
 154         .address = orion_nand_address,
 155         .read_data = orion_nand_read,
 156         .write_data = orion_nand_write,
 157         .write_block_data = orion_nand_fast_block_write,
 158         .reset = orion_nand_reset,
 159         .nand_device_command = orion_nand_device_command,
 160         .init = orion_nand_init,
 161 };