2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
7 * Copyright (C) 2011 by Erik Ahlen *
8 * Avalon Innovation, Sweden *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
27 * Freescale iMX OpenOCD NAND Flash controller support.
28 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
30 * Many thanks to Ben Dooks for writing s3c24xx driver.
33 #define MXC_NF_BUFSIZ (mxc_nf_info->mxc_regs_addr + 0x00)
34 #define MXC_NF_BUFADDR (mxc_nf_info->mxc_regs_addr + 0x04)
35 #define MXC_NF_FADDR (mxc_nf_info->mxc_regs_addr + 0x06)
36 #define MXC_NF_FCMD (mxc_nf_info->mxc_regs_addr + 0x08)
37 #define MXC_NF_BUFCFG (mxc_nf_info->mxc_regs_addr + 0x0a)
38 #define MXC_NF_ECCSTATUS (mxc_nf_info->mxc_regs_addr + 0x0c)
39 #define MXC_NF_ECCMAINPOS (mxc_nf_info->mxc_regs_addr + 0x0e)
40 #define MXC_NF_ECCSPAREPOS (mxc_nf_info->mxc_regs_addr + 0x10)
41 #define MXC_NF_FWP (mxc_nf_info->mxc_regs_addr + 0x12)
42 #define MXC_NF_V1_UNLOCKSTART (mxc_nf_info->mxc_regs_addr + 0x14)
43 #define MXC_NF_V1_UNLOCKEND (mxc_nf_info->mxc_regs_addr + 0x16)
44 #define MXC_NF_V2_UNLOCKSTART0 (mxc_nf_info->mxc_regs_addr + 0x20)
45 #define MXC_NF_V2_UNLOCKSTART1 (mxc_nf_info->mxc_regs_addr + 0x24)
46 #define MXC_NF_V2_UNLOCKSTART2 (mxc_nf_info->mxc_regs_addr + 0x28)
47 #define MXC_NF_V2_UNLOCKSTART3 (mxc_nf_info->mxc_regs_addr + 0x2c)
48 #define MXC_NF_V2_UNLOCKEND0 (mxc_nf_info->mxc_regs_addr + 0x22)
49 #define MXC_NF_V2_UNLOCKEND1 (mxc_nf_info->mxc_regs_addr + 0x26)
50 #define MXC_NF_V2_UNLOCKEND2 (mxc_nf_info->mxc_regs_addr + 0x2a)
51 #define MXC_NF_V2_UNLOCKEND3 (mxc_nf_info->mxc_regs_addr + 0x2e)
52 #define MXC_NF_FWPSTATUS (mxc_nf_info->mxc_regs_addr + 0x18)
54 * all bits not marked as self-clearing bit
56 #define MXC_NF_CFG1 (mxc_nf_info->mxc_regs_addr + 0x1a)
57 #define MXC_NF_CFG2 (mxc_nf_info->mxc_regs_addr + 0x1c)
59 #define MXC_NF_MAIN_BUFFER0 (mxc_nf_info->mxc_base_addr + 0x0000)
60 #define MXC_NF_MAIN_BUFFER1 (mxc_nf_info->mxc_base_addr + 0x0200)
61 #define MXC_NF_MAIN_BUFFER2 (mxc_nf_info->mxc_base_addr + 0x0400)
62 #define MXC_NF_MAIN_BUFFER3 (mxc_nf_info->mxc_base_addr + 0x0600)
63 #define MXC_NF_V1_SPARE_BUFFER0 (mxc_nf_info->mxc_base_addr + 0x0800)
64 #define MXC_NF_V1_SPARE_BUFFER1 (mxc_nf_info->mxc_base_addr + 0x0810)
65 #define MXC_NF_V1_SPARE_BUFFER2 (mxc_nf_info->mxc_base_addr + 0x0820)
66 #define MXC_NF_V1_SPARE_BUFFER3 (mxc_nf_info->mxc_base_addr + 0x0830)
67 #define MXC_NF_V2_MAIN_BUFFER4 (mxc_nf_info->mxc_base_addr + 0x0800)
68 #define MXC_NF_V2_MAIN_BUFFER5 (mxc_nf_info->mxc_base_addr + 0x0a00)
69 #define MXC_NF_V2_MAIN_BUFFER6 (mxc_nf_info->mxc_base_addr + 0x0c00)
70 #define MXC_NF_V2_MAIN_BUFFER7 (mxc_nf_info->mxc_base_addr + 0x0e00)
71 #define MXC_NF_V2_SPARE_BUFFER0 (mxc_nf_info->mxc_base_addr + 0x1000)
72 #define MXC_NF_V2_SPARE_BUFFER1 (mxc_nf_info->mxc_base_addr + 0x1040)
73 #define MXC_NF_V2_SPARE_BUFFER2 (mxc_nf_info->mxc_base_addr + 0x1080)
74 #define MXC_NF_V2_SPARE_BUFFER3 (mxc_nf_info->mxc_base_addr + 0x10c0)
75 #define MXC_NF_V2_SPARE_BUFFER4 (mxc_nf_info->mxc_base_addr + 0x1100)
76 #define MXC_NF_V2_SPARE_BUFFER5 (mxc_nf_info->mxc_base_addr + 0x1140)
77 #define MXC_NF_V2_SPARE_BUFFER6 (mxc_nf_info->mxc_base_addr + 0x1180)
78 #define MXC_NF_V2_SPARE_BUFFER7 (mxc_nf_info->mxc_base_addr + 0x11c0)
79 #define MXC_NF_MAIN_BUFFER_LEN 512
80 #define MXC_NF_SPARE_BUFFER_LEN 16
81 #define MXC_NF_SPARE_BUFFER_MAX 64
82 #define MXC_NF_V1_LAST_BUFFADDR ((MXC_NF_V1_SPARE_BUFFER3) + \
83 MXC_NF_SPARE_BUFFER_LEN - 2)
84 #define MXC_NF_V2_LAST_BUFFADDR ((MXC_NF_V2_SPARE_BUFFER7) + \
85 MXC_NF_SPARE_BUFFER_LEN - 2)
87 /* bits in MXC_NF_CFG1 register */
88 #define MXC_NF_BIT_ECC_4BIT (1<<0)
89 #define MXC_NF_BIT_SPARE_ONLY_EN (1<<2)
90 #define MXC_NF_BIT_ECC_EN (1<<3)
91 #define MXC_NF_BIT_INT_DIS (1<<4)
92 #define MXC_NF_BIT_BE_EN (1<<5)
93 #define MXC_NF_BIT_RESET_EN (1<<6)
94 #define MXC_NF_BIT_FORCE_CE (1<<7)
95 #define MXC_NF_V2_CFG1_PPB(x) (((x) & 0x3) << 9)
97 /* bits in MXC_NF_CFG2 register */
99 /*Flash Command Input*/
100 #define MXC_NF_BIT_OP_FCI (1<<0)
102 * Flash Address Input
104 #define MXC_NF_BIT_OP_FAI (1<<1)
108 #define MXC_NF_BIT_OP_FDI (1<<2)
110 /* see "enum mx_dataout_type" below */
111 #define MXC_NF_BIT_DATAOUT_TYPE(x) ((x)<<3)
112 #define MXC_NF_BIT_OP_DONE (1<<15)
114 #define MXC_CCM_CGR2 0x53f80028
115 #define MXC_GPR 0x43fac008
116 #define MX2_FMCR 0x10027814
117 #define MX2_FMCR_NF_16BIT_SEL (1<<4)
118 #define MX2_FMCR_NF_FMS (1<<5)
119 #define MX3_PCSR 0x53f8000c
120 #define MX3_PCSR_NF_16BIT_SEL (1<<31)
121 #define MX3_PCSR_NF_FMS (1<<30)
122 #define MX35_RCSR 0x53f80018
123 #define MX35_RCSR_NF_16BIT_SEL (1<<14)
124 #define MX35_RCSR_NF_FMS (1<<8)
125 #define MX35_RCSR_NF_4K (1<<9)
128 MXC_VERSION_UKWN = 0,
129 MXC_VERSION_MX27 = 1,
130 MXC_VERSION_MX31 = 2,
134 enum mxc_dataout_type {
135 MXC_NF_DATAOUT_PAGE = 1,
136 MXC_NF_DATAOUT_NANDID = 2,
137 MXC_NF_DATAOUT_NANDSTATUS = 4,
140 enum mxc_nf_finalize_action {
145 struct mxc_nf_flags {
146 unsigned host_little_endian:1;
147 unsigned target_little_endian:1;
148 unsigned nand_readonly:1;
149 unsigned one_kb_sram:1;
150 unsigned hw_ecc_enabled:1;
151 unsigned biswap_enabled:1;
154 struct mxc_nf_controller {
155 enum mxc_version mxc_version;
156 uint32_t mxc_base_addr;
157 uint32_t mxc_regs_addr;
158 enum mxc_dataout_type optype;
159 enum mxc_nf_finalize_action fin;
160 struct mxc_nf_flags flags;