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   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Alexei Babich                                   *
   3  *   Rezonans plc., Chelyabinsk, Russia                                    *
   4  *   impatt@mail.ru                                                        *
   5  *                                                                         *
   6  *   Copyright (C) 2010 by Gaetan CARLIER                                  *
   7  *   Trump s.a., Belgium                                                   *
   8  *                                                                         *
   9  *   Copyright (C) 2011 by Erik Ahlen                                      *
  10  *   Avalon Innovation, Sweden                                             *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  24  ***************************************************************************/
  25
  26 /*
  27  * Freescale iMX OpenOCD NAND Flash controller support.
  28  * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
  29  */
  30
  31 /*
  32  * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
  33  * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
  34  * "nand write # file 0", "nand verify"
  35  *
  36  * get_next_halfword_from_sram_buffer() not tested
  37  * !! all function only tested with 2k page nand device; mxc_write_page
  38  *    writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
  39  * !! oob must be be used due to NFS bug
  40  * !! oob must be 64 bytes per 2KiB page
  41 */
  42 #ifdef HAVE_CONFIG_H
  43 #include "config.h"
  44 #endif
  45
  46 #include "imp.h"
  47 #include "mxc.h"
  48 #include <target/target.h>
  49
  50 #define OOB_SIZE        64
  51
  52 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
  53                 mxc_nf_info->mxc_version == MXC_VERSION_MX31)
  54 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
  55                 mxc_nf_info->mxc_version == MXC_VERSION_MX35)
  56
  57 /* This permits to print (in LOG_INFO) how much bytes
  58  * has been written after a page read or write.
  59  * This is useful when OpenOCD is used with a graphical
  60  * front-end to estimate progression of the global read/write
  61  */
  62 #undef _MXC_PRINT_STAT
  63 /* #define _MXC_PRINT_STAT */
  64
  65 static const char target_not_halted_err_msg[] =
  66         "target must be halted to use mxc NAND flash controller";
  67 static const char data_block_size_err_msg[] =
  68         "minimal granularity is one half-word, %" PRId32 " is incorrect";
  69 static const char sram_buffer_bounds_err_msg[] =
  70         "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  71 static const char get_status_register_err_msg[] = "can't get NAND status";
  72 static uint32_t in_sram_address;
  73 static unsigned char sign_of_sequental_byte_read;
  74
  75 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr);
  76 static int initialize_nf_controller(struct nand_device *nand);
  77 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
  78 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
  79 static int poll_for_complete_op(struct nand_device *nand, const char *text);
  80 static int validate_target_state(struct nand_device *nand);
  81 static int do_data_output(struct nand_device *nand);
  82
  83 static int mxc_command(struct nand_device *nand, uint8_t command);
  84 static int mxc_address(struct nand_device *nand, uint8_t address);
  85
  86 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
  87 {
  88         struct mxc_nf_controller *mxc_nf_info;
  89         int hwecc_needed;
  90
  91         mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
  92         if (mxc_nf_info == NULL) {
  93                 LOG_ERROR("no memory for nand controller");
  94                 return ERROR_FAIL;
  95         }
  96         nand->controller_priv = mxc_nf_info;
  97
  98         if (CMD_ARGC < 4) {
  99                 LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]\"");
 100                 return ERROR_FAIL;
 101         }
 102
 103         /*
 104          * check board type
 105          */
 106         if (strcmp(CMD_ARGV[2], "mx25") == 0) {
 107                 mxc_nf_info->mxc_version = MXC_VERSION_MX25;
 108                 mxc_nf_info->mxc_base_addr = 0xBB000000;
 109                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
 110         } else if (strcmp(CMD_ARGV[2], "mx27") == 0) {
 111                 mxc_nf_info->mxc_version = MXC_VERSION_MX27;
 112                 mxc_nf_info->mxc_base_addr = 0xD8000000;
 113                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
 114         } else if (strcmp(CMD_ARGV[2], "mx31") == 0) {
 115                 mxc_nf_info->mxc_version = MXC_VERSION_MX31;
 116                 mxc_nf_info->mxc_base_addr = 0xB8000000;
 117                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
 118         } else if (strcmp(CMD_ARGV[2], "mx35") == 0) {
 119                 mxc_nf_info->mxc_version = MXC_VERSION_MX35;
 120                 mxc_nf_info->mxc_base_addr = 0xBB000000;
 121                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
 122         }
 123
 124         /*
 125          * check hwecc requirements
 126          */
 127         hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
 128         if (hwecc_needed == 0)
 129                 mxc_nf_info->flags.hw_ecc_enabled = 1;
 130         else
 131                 mxc_nf_info->flags.hw_ecc_enabled = 0;
 132
 133         mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 134         mxc_nf_info->fin = MXC_NF_FIN_NONE;
 135         mxc_nf_info->flags.target_little_endian =
 136                 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
 137
 138         /*
 139          * should factory bad block indicator be swaped
 140          * as a workaround for how the nfc handles pages.
 141          */
 142         if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
 143                 LOG_DEBUG("BI-swap enabled");
 144                 mxc_nf_info->flags.biswap_enabled = 1;
 145         }
 146
 147         return ERROR_OK;
 148 }
 149
 150 COMMAND_HANDLER(handle_mxc_biswap_command)
 151 {
 152         struct nand_device *nand = NULL;
 153         struct mxc_nf_controller *mxc_nf_info = NULL;
 154
 155         if (CMD_ARGC < 1 || CMD_ARGC > 2)
 156                 return ERROR_COMMAND_SYNTAX_ERROR;
 157
 158         int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
 159         if (retval != ERROR_OK) {
 160                 command_print(CMD_CTX, "invalid nand device number or name: %s", CMD_ARGV[0]);
 161                 return ERROR_COMMAND_ARGUMENT_INVALID;
 162         }
 163
 164         mxc_nf_info = nand->controller_priv;
 165         if (CMD_ARGC == 2) {
 166                 if (strcmp(CMD_ARGV[1], "enable") == 0)
 167                         mxc_nf_info->flags.biswap_enabled = true;
 168                 else
 169                         mxc_nf_info->flags.biswap_enabled = false;
 170         }
 171         if (mxc_nf_info->flags.biswap_enabled)
 172                 command_print(CMD_CTX, "BI-swapping enabled on %s", nand->name);
 173         else
 174                 command_print(CMD_CTX, "BI-swapping disabled on %s", nand->name);
 175
 176         return ERROR_OK;
 177 }
 178
 179 static const struct command_registration mxc_sub_command_handlers[] = {
 180         {
 181                 .name = "biswap",
 182                 .mode = COMMAND_EXEC,
 183                 .handler = handle_mxc_biswap_command,
 184                 .help = "Turns on/off bad block information swaping from main area, "
 185                         "without parameter query status.",
 186                 .usage = "bank_id ['enable'|'disable']",
 187         },
 188         COMMAND_REGISTRATION_DONE
 189 };
 190
 191 static const struct command_registration mxc_nand_command_handler[] = {
 192         {
 193                 .name = "mxc",
 194                 .mode = COMMAND_ANY,
 195                 .help = "MXC NAND flash controller commands",
 196                 .chain = mxc_sub_command_handlers
 197         },
 198         COMMAND_REGISTRATION_DONE
 199 };
 200
 201 static int mxc_init(struct nand_device *nand)
 202 {
 203         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 204         struct target *target = nand->target;
 205
 206         int validate_target_result;
 207         uint16_t buffsize_register_content;
 208         uint32_t sreg_content;
 209         uint32_t SREG = MX2_FMCR;
 210         uint32_t SEL_16BIT = MX2_FMCR_NF_16BIT_SEL;
 211         uint32_t SEL_FMS = MX2_FMCR_NF_FMS;
 212         int retval;
 213         uint16_t nand_status_content;
 214         /*
 215          * validate target state
 216          */
 217         validate_target_result = validate_target_state(nand);
 218         if (validate_target_result != ERROR_OK)
 219                 return validate_target_result;
 220
 221         if (nfc_is_v1()) {
 222                 target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
 223                 mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
 224         } else
 225                 mxc_nf_info->flags.one_kb_sram = 0;
 226
 227         if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
 228                 SREG = MX3_PCSR;
 229                 SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
 230                 SEL_FMS = MX3_PCSR_NF_FMS;
 231         } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
 232                 SREG = MX25_RCSR;
 233                 SEL_16BIT = MX25_RCSR_NF_16BIT_SEL;
 234                 SEL_FMS = MX25_RCSR_NF_FMS;
 235         } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
 236                 SREG = MX35_RCSR;
 237                 SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
 238                 SEL_FMS = MX35_RCSR_NF_FMS;
 239         }
 240
 241         target_read_u32(target, SREG, &sreg_content);
 242         if (!nand->bus_width) {
 243                 /* bus_width not yet defined. Read it from MXC_FMCR */
 244                 nand->bus_width = (sreg_content & SEL_16BIT) ? 16 : 8;
 245         } else {
 246                 /* bus_width forced in soft. Sync it to MXC_FMCR */
 247                 sreg_content |= ((nand->bus_width == 16) ? SEL_16BIT : 0x00000000);
 248                 target_write_u32(target, SREG, sreg_content);
 249         }
 250         if (nand->bus_width == 16)
 251                 LOG_DEBUG("MXC_NF : bus is 16-bit width");
 252         else
 253                 LOG_DEBUG("MXC_NF : bus is 8-bit width");
 254
 255         if (!nand->page_size)
 256                 nand->page_size = (sreg_content & SEL_FMS) ? 2048 : 512;
 257         else {
 258                 sreg_content |= ((nand->page_size == 2048) ? SEL_FMS : 0x00000000);
 259                 target_write_u32(target, SREG, sreg_content);
 260         }
 261         if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
 262                 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
 263                         "pagesize 2048 is incompatible with it");
 264         } else
 265                 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
 266
 267         if (nfc_is_v2() && sreg_content & MX35_RCSR_NF_4K)
 268                 LOG_ERROR("MXC driver does not have support for 4k pagesize.");
 269
 270         initialize_nf_controller(nand);
 271
 272         retval = ERROR_OK;
 273         retval |= mxc_command(nand, NAND_CMD_STATUS);
 274         retval |= mxc_address(nand, 0x00);
 275         retval |= do_data_output(nand);
 276         if (retval != ERROR_OK) {
 277                 LOG_ERROR(get_status_register_err_msg);
 278                 return ERROR_FAIL;
 279         }
 280         target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
 281         if (!(nand_status_content & 0x0080)) {
 282                 LOG_INFO("NAND read-only");
 283                 mxc_nf_info->flags.nand_readonly = 1;
 284         } else
 285                 mxc_nf_info->flags.nand_readonly = 0;
 286         return ERROR_OK;
 287 }
 288
 289 static int mxc_read_data(struct nand_device *nand, void *data)
 290 {
 291         int validate_target_result;
 292         int try_data_output_from_nand_chip;
 293         /*
 294          * validate target state
 295          */
 296         validate_target_result = validate_target_state(nand);
 297         if (validate_target_result != ERROR_OK)
 298                 return validate_target_result;
 299
 300         /*
 301          * get data from nand chip
 302          */
 303         try_data_output_from_nand_chip = do_data_output(nand);
 304         if (try_data_output_from_nand_chip != ERROR_OK) {
 305                 LOG_ERROR("mxc_read_data : read data failed : '%x'",
 306                         try_data_output_from_nand_chip);
 307                 return try_data_output_from_nand_chip;
 308         }
 309
 310         if (nand->bus_width == 16)
 311                 get_next_halfword_from_sram_buffer(nand, data);
 312         else
 313                 get_next_byte_from_sram_buffer(nand, data);
 314
 315         return ERROR_OK;
 316 }
 317
 318 static int mxc_write_data(struct nand_device *nand, uint16_t data)
 319 {
 320         LOG_ERROR("write_data() not implemented");
 321         return ERROR_NAND_OPERATION_FAILED;
 322 }
 323
 324 static int mxc_reset(struct nand_device *nand)
 325 {
 326         /*
 327          * validate target state
 328          */
 329         int validate_target_result;
 330         validate_target_result = validate_target_state(nand);
 331         if (validate_target_result != ERROR_OK)
 332                 return validate_target_result;
 333         initialize_nf_controller(nand);
 334         return ERROR_OK;
 335 }
 336
 337 static int mxc_command(struct nand_device *nand, uint8_t command)
 338 {
 339         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 340         struct target *target = nand->target;
 341         int validate_target_result;
 342         int poll_result;
 343         /*
 344          * validate target state
 345          */
 346         validate_target_result = validate_target_state(nand);
 347         if (validate_target_result != ERROR_OK)
 348                 return validate_target_result;
 349
 350         switch (command) {
 351                 case NAND_CMD_READOOB:
 352                         command = NAND_CMD_READ0;
 353                         /* set read point for data_read() and read_block_data() to
 354                          * spare area in SRAM buffer
 355                          */
 356                         if (nfc_is_v1())
 357                                 in_sram_address = MXC_NF_V1_SPARE_BUFFER0;
 358                         else
 359                                 in_sram_address = MXC_NF_V2_SPARE_BUFFER0;
 360                         break;
 361                 case NAND_CMD_READ1:
 362                         command = NAND_CMD_READ0;
 363                         /*
 364                          * offset == one half of page size
 365                          */
 366                         in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
 367                         break;
 368                 default:
 369                         in_sram_address = MXC_NF_MAIN_BUFFER0;
 370                         break;
 371         }
 372
 373         target_write_u16(target, MXC_NF_FCMD, command);
 374         /*
 375          * start command input operation (set MXC_NF_BIT_OP_DONE==0)
 376          */
 377         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
 378         poll_result = poll_for_complete_op(nand, "command");
 379         if (poll_result != ERROR_OK)
 380                 return poll_result;
 381         /*
 382          * reset cursor to begin of the buffer
 383          */
 384         sign_of_sequental_byte_read = 0;
 385         /* Handle special read command and adjust NF_CFG2(FDO) */
 386         switch (command) {
 387                 case NAND_CMD_READID:
 388                         mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
 389                         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 390                         break;
 391                 case NAND_CMD_STATUS:
 392                         mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
 393                         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 394                         target_write_u16 (target, MXC_NF_BUFADDR, 0);
 395                         in_sram_address = 0;
 396                         break;
 397                 case NAND_CMD_READ0:
 398                         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 399                         mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 400                         break;
 401                 default:
 402                         /* Ohter command use the default 'One page data out' FDO */
 403                         mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 404                         break;
 405         }
 406         return ERROR_OK;
 407 }
 408
 409 static int mxc_address(struct nand_device *nand, uint8_t address)
 410 {
 411         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 412         struct target *target = nand->target;
 413         int validate_target_result;
 414         int poll_result;
 415         /*
 416          * validate target state
 417          */
 418         validate_target_result = validate_target_state(nand);
 419         if (validate_target_result != ERROR_OK)
 420                 return validate_target_result;
 421
 422         target_write_u16(target, MXC_NF_FADDR, address);
 423         /*
 424          * start address input operation (set MXC_NF_BIT_OP_DONE==0)
 425          */
 426         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
 427         poll_result = poll_for_complete_op(nand, "address");
 428         if (poll_result != ERROR_OK)
 429                 return poll_result;
 430
 431         return ERROR_OK;
 432 }
 433
 434 static int mxc_nand_ready(struct nand_device *nand, int tout)
 435 {
 436         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 437         struct target *target = nand->target;
 438         uint16_t poll_complete_status;
 439         int validate_target_result;
 440
 441         /*
 442          * validate target state
 443          */
 444         validate_target_result = validate_target_state(nand);
 445         if (validate_target_result != ERROR_OK)
 446                 return validate_target_result;
 447
 448         do {
 449                 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
 450                 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
 451                         return tout;
 452
 453                 alive_sleep(1);
 454         } while (tout-- > 0);
 455         return tout;
 456 }
 457
 458 static int mxc_write_page(struct nand_device *nand, uint32_t page,
 459         uint8_t *data, uint32_t data_size,
 460         uint8_t *oob, uint32_t oob_size)
 461 {
 462         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 463         struct target *target = nand->target;
 464         int retval;
 465         uint16_t nand_status_content;
 466         uint16_t swap1, swap2, new_swap1;
 467         uint8_t bufs;
 468         int poll_result;
 469
 470         if (data_size % 2) {
 471                 LOG_ERROR(data_block_size_err_msg, data_size);
 472                 return ERROR_NAND_OPERATION_FAILED;
 473         }
 474         if (oob_size % 2) {
 475                 LOG_ERROR(data_block_size_err_msg, oob_size);
 476                 return ERROR_NAND_OPERATION_FAILED;
 477         }
 478         if (!data) {
 479                 LOG_ERROR("nothing to program");
 480                 return ERROR_NAND_OPERATION_FAILED;
 481         }
 482
 483         /*
 484          * validate target state
 485          */
 486         retval = validate_target_state(nand);
 487         if (retval != ERROR_OK)
 488                 return retval;
 489
 490         in_sram_address = MXC_NF_MAIN_BUFFER0;
 491         sign_of_sequental_byte_read = 0;
 492         retval = ERROR_OK;
 493         retval |= mxc_command(nand, NAND_CMD_SEQIN);
 494         retval |= mxc_address(nand, 0); /* col */
 495         retval |= mxc_address(nand, 0); /* col */
 496         retval |= mxc_address(nand, page & 0xff);       /* page address */
 497         retval |= mxc_address(nand, (page >> 8) & 0xff);/* page address */
 498         retval |= mxc_address(nand, (page >> 16) & 0xff);       /* page address */
 499
 500         target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
 501         if (oob) {
 502                 if (mxc_nf_info->flags.hw_ecc_enabled) {
 503                         /*
 504                          * part of spare block will be overrided by hardware
 505                          * ECC generator
 506                          */
 507                         LOG_DEBUG("part of spare block will be overrided "
 508                                 "by hardware ECC generator");
 509                 }
 510                 if (nfc_is_v1())
 511                         target_write_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
 512                 else {
 513                         uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
 514                         while (oob_size > 0) {
 515                                 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
 516                                 target_write_buffer(target, addr, len, oob);
 517                                 addr = align_address_v2(nand, addr + len);
 518                                 oob += len;
 519                                 oob_size -= len;
 520                         }
 521                 }
 522         }
 523
 524         if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
 525                 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
 526                 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
 527                 if (oob) {
 528                         LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
 529                         return ERROR_NAND_OPERATION_FAILED;
 530                 }
 531                 swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
 532                 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 533                 swap2 = (swap1 << 8) | (swap2 & 0xFF);
 534                 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
 535                 if (nfc_is_v1())
 536                         target_write_u16(target, MXC_NF_V1_SPARE_BUFFER3 + 4, swap2);
 537                 else
 538                         target_write_u16(target, MXC_NF_V2_SPARE_BUFFER3, swap2);
 539         }
 540
 541         /*
 542          * start data input operation (set MXC_NF_BIT_OP_DONE==0)
 543          */
 544         if (nfc_is_v1() && nand->page_size > 512)
 545                 bufs = 4;
 546         else
 547                 bufs = 1;
 548
 549         for (uint8_t i = 0; i < bufs; ++i) {
 550                 target_write_u16(target, MXC_NF_BUFADDR, i);
 551                 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
 552                 poll_result = poll_for_complete_op(nand, "data input");
 553                 if (poll_result != ERROR_OK)
 554                         return poll_result;
 555         }
 556
 557         retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
 558         if (retval != ERROR_OK)
 559                 return retval;
 560
 561         /*
 562          * check status register
 563          */
 564         retval = ERROR_OK;
 565         retval |= mxc_command(nand, NAND_CMD_STATUS);
 566         target_write_u16 (target, MXC_NF_BUFADDR, 0);
 567         mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
 568         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 569         retval |= do_data_output(nand);
 570         if (retval != ERROR_OK) {
 571                 LOG_ERROR(get_status_register_err_msg);
 572                 return retval;
 573         }
 574         target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
 575         if (nand_status_content & 0x0001) {
 576                 /*
 577                  * page not correctly written
 578                  */
 579                 return ERROR_NAND_OPERATION_FAILED;
 580         }
 581 #ifdef _MXC_PRINT_STAT
 582         LOG_INFO("%d bytes newly written", data_size);
 583 #endif
 584         return ERROR_OK;
 585 }
 586
 587 static int mxc_read_page(struct nand_device *nand, uint32_t page,
 588         uint8_t *data, uint32_t data_size,
 589         uint8_t *oob, uint32_t oob_size)
 590 {
 591         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 592         struct target *target = nand->target;
 593         int retval;
 594         uint8_t bufs;
 595         uint16_t swap1, swap2, new_swap1;
 596
 597         if (data_size % 2) {
 598                 LOG_ERROR(data_block_size_err_msg, data_size);
 599                 return ERROR_NAND_OPERATION_FAILED;
 600         }
 601         if (oob_size % 2) {
 602                 LOG_ERROR(data_block_size_err_msg, oob_size);
 603                 return ERROR_NAND_OPERATION_FAILED;
 604         }
 605
 606         /*
 607          * validate target state
 608          */
 609         retval = validate_target_state(nand);
 610         if (retval != ERROR_OK)
 611                 return retval;
 612                                 /* Reset address_cycles before mxc_command ?? */
 613         retval = mxc_command(nand, NAND_CMD_READ0);
 614         if (retval != ERROR_OK)
 615                 return retval;
 616         retval = mxc_address(nand, 0);  /* col */
 617         if (retval != ERROR_OK)
 618                 return retval;
 619         retval = mxc_address(nand, 0);  /* col */
 620         if (retval != ERROR_OK)
 621                 return retval;
 622         retval = mxc_address(nand, page & 0xff);/* page address */
 623         if (retval != ERROR_OK)
 624                 return retval;
 625         retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
 626         if (retval != ERROR_OK)
 627                 return retval;
 628         retval = mxc_address(nand, (page >> 16) & 0xff);/* page address */
 629         if (retval != ERROR_OK)
 630                 return retval;
 631         retval = mxc_command(nand, NAND_CMD_READSTART);
 632         if (retval != ERROR_OK)
 633                 return retval;
 634
 635         if (nfc_is_v1() && nand->page_size > 512)
 636                 bufs = 4;
 637         else
 638                 bufs = 1;
 639
 640         for (uint8_t i = 0; i < bufs; ++i) {
 641                 target_write_u16(target, MXC_NF_BUFADDR, i);
 642                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 643                 retval = do_data_output(nand);
 644                 if (retval != ERROR_OK) {
 645                         LOG_ERROR("MXC_NF : Error reading page %d", i);
 646                         return retval;
 647                 }
 648         }
 649
 650         if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
 651                 uint32_t SPARE_BUFFER3;
 652                 /* BI-swap -  work-around of mxc NFC for NAND device with page == 2k */
 653                 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
 654                 if (nfc_is_v1())
 655                         SPARE_BUFFER3 = MXC_NF_V1_SPARE_BUFFER3 + 4;
 656                 else
 657                         SPARE_BUFFER3 = MXC_NF_V2_SPARE_BUFFER3;
 658                 target_read_u16(target, SPARE_BUFFER3, &swap2);
 659                 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 660                 swap2 = (swap1 << 8) | (swap2 & 0xFF);
 661                 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
 662                 target_write_u16(target, SPARE_BUFFER3, swap2);
 663         }
 664
 665         if (data)
 666                 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
 667         if (oob) {
 668                 if (nfc_is_v1())
 669                         target_read_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
 670                 else {
 671                         uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
 672                         while (oob_size > 0) {
 673                                 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
 674                                 target_read_buffer(target, addr, len, oob);
 675                                 addr = align_address_v2(nand, addr + len);
 676                                 oob += len;
 677                                 oob_size -= len;
 678                         }
 679                 }
 680         }
 681
 682 #ifdef _MXC_PRINT_STAT
 683         if (data_size > 0) {
 684                 /* When Operation Status is read (when page is erased),
 685                  * this function is used but data_size is null.
 686                  */
 687                 LOG_INFO("%d bytes newly read", data_size);
 688         }
 689 #endif
 690         return ERROR_OK;
 691 }
 692
 693 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr)
 694 {
 695         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 696         uint32_t ret = addr;
 697         if (addr > MXC_NF_V2_SPARE_BUFFER0 &&
 698                         (addr & 0x1F) == MXC_NF_SPARE_BUFFER_LEN)
 699                 ret += MXC_NF_SPARE_BUFFER_MAX - MXC_NF_SPARE_BUFFER_LEN;
 700         else if (addr >= (mxc_nf_info->mxc_base_addr + (uint32_t)nand->page_size))
 701                 ret = MXC_NF_V2_SPARE_BUFFER0;
 702         return ret;
 703 }
 704
 705 static int initialize_nf_controller(struct nand_device *nand)
 706 {
 707         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 708         struct target *target = nand->target;
 709         uint16_t work_mode = 0;
 710         uint16_t temp;
 711         /*
 712          * resets NAND flash controller in zero time ? I dont know.
 713          */
 714         target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
 715         if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
 716                 work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
 717
 718         if (target->endianness == TARGET_BIG_ENDIAN) {
 719                 LOG_DEBUG("MXC_NF : work in Big Endian mode");
 720                 work_mode |= MXC_NF_BIT_BE_EN;
 721         } else
 722                 LOG_DEBUG("MXC_NF : work in Little Endian mode");
 723         if (mxc_nf_info->flags.hw_ecc_enabled) {
 724                 LOG_DEBUG("MXC_NF : work with ECC mode");
 725                 work_mode |= MXC_NF_BIT_ECC_EN;
 726         } else
 727                 LOG_DEBUG("MXC_NF : work without ECC mode");
 728         if (nfc_is_v2()) {
 729                 target_write_u16(target, MXC_NF_V2_SPAS, OOB_SIZE / 2);
 730                 if (nand->page_size) {
 731                         uint16_t pages_per_block = nand->erase_size / nand->page_size;
 732                         work_mode |= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block) - 6);
 733                 }
 734                 work_mode |= MXC_NF_BIT_ECC_4BIT;
 735         }
 736         target_write_u16(target, MXC_NF_CFG1, work_mode);
 737
 738         /*
 739          * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
 740          */
 741         target_write_u16(target, MXC_NF_BUFCFG, 2);
 742         target_read_u16(target, MXC_NF_FWP, &temp);
 743         if ((temp & 0x0007) == 1) {
 744                 LOG_ERROR("NAND flash is tight-locked, reset needed");
 745                 return ERROR_FAIL;
 746         }
 747
 748         /*
 749          * unlock NAND flash for write
 750          */
 751         if (nfc_is_v1()) {
 752                 target_write_u16(target, MXC_NF_V1_UNLOCKSTART, 0x0000);
 753                 target_write_u16(target, MXC_NF_V1_UNLOCKEND, 0xFFFF);
 754         } else {
 755                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART0, 0x0000);
 756                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART1, 0x0000);
 757                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART2, 0x0000);
 758                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART3, 0x0000);
 759                 target_write_u16(target, MXC_NF_V2_UNLOCKEND0, 0xFFFF);
 760                 target_write_u16(target, MXC_NF_V2_UNLOCKEND1, 0xFFFF);
 761                 target_write_u16(target, MXC_NF_V2_UNLOCKEND2, 0xFFFF);
 762                 target_write_u16(target, MXC_NF_V2_UNLOCKEND3, 0xFFFF);
 763         }
 764         target_write_u16(target, MXC_NF_FWP, 4);
 765
 766         /*
 767          * 0x0000 means that first SRAM buffer @base_addr will be used
 768          */
 769         target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
 770         /*
 771          * address of SRAM buffer
 772          */
 773         in_sram_address = MXC_NF_MAIN_BUFFER0;
 774         sign_of_sequental_byte_read = 0;
 775         return ERROR_OK;
 776 }
 777
 778 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
 779 {
 780         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 781         struct target *target = nand->target;
 782         static uint8_t even_byte;
 783         uint16_t temp;
 784         /*
 785          * host-big_endian ??
 786          */
 787         if (sign_of_sequental_byte_read == 0)
 788                 even_byte = 0;
 789
 790         if (in_sram_address > (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
 791                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 792                 *value = 0;
 793                 sign_of_sequental_byte_read = 0;
 794                 even_byte = 0;
 795                 return ERROR_NAND_OPERATION_FAILED;
 796         } else {
 797                 if (nfc_is_v2())
 798                         in_sram_address = align_address_v2(nand, in_sram_address);
 799
 800                 target_read_u16(target, in_sram_address, &temp);
 801                 if (even_byte) {
 802                         *value = temp >> 8;
 803                         even_byte = 0;
 804                         in_sram_address += 2;
 805                 } else {
 806                         *value = temp & 0xff;
 807                         even_byte = 1;
 808                 }
 809         }
 810         sign_of_sequental_byte_read = 1;
 811         return ERROR_OK;
 812 }
 813
 814 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
 815 {
 816         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 817         struct target *target = nand->target;
 818
 819         if (in_sram_address > (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
 820                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 821                 *value = 0;
 822                 return ERROR_NAND_OPERATION_FAILED;
 823         } else {
 824                 if (nfc_is_v2())
 825                         in_sram_address = align_address_v2(nand, in_sram_address);
 826
 827                 target_read_u16(target, in_sram_address, value);
 828                 in_sram_address += 2;
 829         }
 830         return ERROR_OK;
 831 }
 832
 833 static int poll_for_complete_op(struct nand_device *nand, const char *text)
 834 {
 835         if (mxc_nand_ready(nand, 1000) == -1) {
 836                 LOG_ERROR("%s sending timeout", text);
 837                 return ERROR_NAND_OPERATION_FAILED;
 838         }
 839         return ERROR_OK;
 840 }
 841
 842 static int validate_target_state(struct nand_device *nand)
 843 {
 844         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 845         struct target *target = nand->target;
 846
 847         if (target->state != TARGET_HALTED) {
 848                 LOG_ERROR(target_not_halted_err_msg);
 849                 return ERROR_NAND_OPERATION_FAILED;
 850         }
 851
 852         if (mxc_nf_info->flags.target_little_endian !=
 853                         (target->endianness == TARGET_LITTLE_ENDIAN)) {
 854                 /*
 855                  * endianness changed after NAND controller probed
 856                  */
 857                 return ERROR_NAND_OPERATION_FAILED;
 858         }
 859         return ERROR_OK;
 860 }
 861
 862 int ecc_status_v1(struct nand_device *nand)
 863 {
 864         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 865         struct target *target = nand->target;
 866         uint16_t ecc_status;
 867
 868         target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
 869         switch (ecc_status & 0x000c) {
 870                 case 1 << 2:
 871                         LOG_INFO("main area read with 1 (correctable) error");
 872                         break;
 873                 case 2 << 2:
 874                         LOG_INFO("main area read with more than 1 (incorrectable) error");
 875                         return ERROR_NAND_OPERATION_FAILED;
 876                         break;
 877         }
 878         switch (ecc_status & 0x0003) {
 879                 case 1:
 880                         LOG_INFO("spare area read with 1 (correctable) error");
 881                         break;
 882                 case 2:
 883                         LOG_INFO("main area read with more than 1 (incorrectable) error");
 884                         return ERROR_NAND_OPERATION_FAILED;
 885                         break;
 886         }
 887         return ERROR_OK;
 888 }
 889
 890 int ecc_status_v2(struct nand_device *nand)
 891 {
 892         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 893         struct target *target = nand->target;
 894         uint16_t ecc_status;
 895         uint8_t no_subpages;
 896         uint8_t err;
 897
 898         no_subpages = nand->page_size >> 9;
 899
 900         target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
 901         do {
 902                 err = ecc_status & 0xF;
 903                 if (err > 4) {
 904                         LOG_INFO("UnCorrectable RS-ECC Error");
 905                         return ERROR_NAND_OPERATION_FAILED;
 906                 } else if (err > 0)
 907                         LOG_INFO("%d Symbol Correctable RS-ECC Error", err);
 908                 ecc_status >>= 4;
 909         } while (--no_subpages);
 910         return ERROR_OK;
 911 }
 912
 913 static int do_data_output(struct nand_device *nand)
 914 {
 915         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 916         struct target *target = nand->target;
 917         int poll_result;
 918         switch (mxc_nf_info->fin) {
 919                 case MXC_NF_FIN_DATAOUT:
 920                         /*
 921                          * start data output operation (set MXC_NF_BIT_OP_DONE==0)
 922                          */
 923                         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
 924                         poll_result = poll_for_complete_op(nand, "data output");
 925                         if (poll_result != ERROR_OK)
 926                                 return poll_result;
 927
 928                         mxc_nf_info->fin = MXC_NF_FIN_NONE;
 929                         /*
 930                          * ECC stuff
 931                          */
 932                         if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE && mxc_nf_info->flags.hw_ecc_enabled) {
 933                                 int ecc_status;
 934                                 if (nfc_is_v1())
 935                                         ecc_status = ecc_status_v1(nand);
 936                                 else
 937                                         ecc_status = ecc_status_v2(nand);
 938                                 if (ecc_status != ERROR_OK)
 939                                         return ecc_status;
 940                         }
 941                         break;
 942                 case MXC_NF_FIN_NONE:
 943                         break;
 944         }
 945         return ERROR_OK;
 946 }
 947
 948 struct nand_flash_controller mxc_nand_flash_controller = {
 949         .name = "mxc",
 950         .nand_device_command = &mxc_nand_device_command,
 951         .commands = mxc_nand_command_handler,
 952         .init = &mxc_init,
 953         .reset = &mxc_reset,
 954         .command = &mxc_command,
 955         .address = &mxc_address,
 956         .write_data = &mxc_write_data,
 957         .read_data = &mxc_read_data,
 958         .write_page = &mxc_write_page,
 959         .read_page = &mxc_read_page,
 960         .nand_ready = &mxc_nand_ready,
 961 };