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   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Alexei Babich                                   *
   3  *   Rezonans plc., Chelyabinsk, Russia                                    *
   4  *   impatt@mail.ru                                                        *
   5  *                                                                         *
   6  *   Copyright (C) 2010 by Gaetan CARLIER                                  *
   7  *   Trump s.a., Belgium                                                   *
   8  *                                                                         *
   9  *   Copyright (C) 2011 by Erik Ahlen                                      *
  10  *   Avalon Innovation, Sweden                                             *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program; if not, write to the                         *
  24  *   Free Software Foundation, Inc.,                                       *
  25  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  26  ***************************************************************************/
  27
  28 /*
  29  * Freescale iMX OpenOCD NAND Flash controller support.
  30  * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
  31  */
  32
  33 /*
  34  * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
  35  * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
  36  * "nand write # file 0", "nand verify"
  37  *
  38  * get_next_halfword_from_sram_buffer() not tested
  39  * !! all function only tested with 2k page nand device; mxc_write_page
  40  *    writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
  41  * !! oob must be be used due to NFS bug
  42  * !! oob must be 64 bytes per 2KiB page
  43 */
  44 #ifdef HAVE_CONFIG_H
  45 #include "config.h"
  46 #endif
  47
  48 #include "imp.h"
  49 #include "mxc.h"
  50 #include <target/target.h>
  51
  52 #define OOB_SIZE        64
  53
  54 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
  55                 mxc_nf_info->mxc_version == MXC_VERSION_MX31)
  56 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
  57                 mxc_nf_info->mxc_version == MXC_VERSION_MX35)
  58
  59 /* This permits to print (in LOG_INFO) how much bytes
  60  * has been written after a page read or write.
  61  * This is useful when OpenOCD is used with a graphical
  62  * front-end to estimate progression of the global read/write
  63  */
  64 #undef _MXC_PRINT_STAT
  65 /* #define _MXC_PRINT_STAT */
  66
  67 static const char target_not_halted_err_msg[] =
  68         "target must be halted to use mxc NAND flash controller";
  69 static const char data_block_size_err_msg[] =
  70         "minimal granularity is one half-word, %" PRId32 " is incorrect";
  71 static const char sram_buffer_bounds_err_msg[] =
  72         "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  73 static const char get_status_register_err_msg[] = "can't get NAND status";
  74 static uint32_t in_sram_address;
  75 static unsigned char sign_of_sequental_byte_read;
  76
  77 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr);
  78 static int initialize_nf_controller(struct nand_device *nand);
  79 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
  80 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
  81 static int poll_for_complete_op(struct nand_device *nand, const char *text);
  82 static int validate_target_state(struct nand_device *nand);
  83 static int do_data_output(struct nand_device *nand);
  84
  85 static int mxc_command(struct nand_device *nand, uint8_t command);
  86 static int mxc_address(struct nand_device *nand, uint8_t address);
  87
  88 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
  89 {
  90         struct mxc_nf_controller *mxc_nf_info;
  91         int hwecc_needed;
  92         int x;
  93
  94         mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
  95         if (mxc_nf_info == NULL) {
  96                 LOG_ERROR("no memory for nand controller");
  97                 return ERROR_FAIL;
  98         }
  99         nand->controller_priv = mxc_nf_info;
 100
 101         if (CMD_ARGC < 4) {
 102                 LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]\"");
 103                 return ERROR_FAIL;
 104         }
 105
 106         /*
 107          * check board type
 108          */
 109         if (strcmp(CMD_ARGV[2], "mx25") == 0) {
 110                 mxc_nf_info->mxc_version = MXC_VERSION_MX25;
 111                 mxc_nf_info->mxc_base_addr = 0xBB000000;
 112                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
 113         } else if (strcmp(CMD_ARGV[2], "mx27") == 0) {
 114                 mxc_nf_info->mxc_version = MXC_VERSION_MX27;
 115                 mxc_nf_info->mxc_base_addr = 0xD8000000;
 116                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
 117         } else if (strcmp(CMD_ARGV[2], "mx31") == 0) {
 118                 mxc_nf_info->mxc_version = MXC_VERSION_MX31;
 119                 mxc_nf_info->mxc_base_addr = 0xB8000000;
 120                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
 121         } else if (strcmp(CMD_ARGV[2], "mx35") == 0) {
 122                 mxc_nf_info->mxc_version = MXC_VERSION_MX35;
 123                 mxc_nf_info->mxc_base_addr = 0xBB000000;
 124                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
 125         }
 126
 127         /*
 128          * check hwecc requirements
 129          */
 130         hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
 131         if (hwecc_needed == 0)
 132                 mxc_nf_info->flags.hw_ecc_enabled = 1;
 133         else
 134                 mxc_nf_info->flags.hw_ecc_enabled = 0;
 135
 136         mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 137         mxc_nf_info->fin = MXC_NF_FIN_NONE;
 138         mxc_nf_info->flags.target_little_endian =
 139                 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
 140
 141         /*
 142          * should factory bad block indicator be swaped
 143          * as a workaround for how the nfc handles pages.
 144          */
 145         if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
 146                 LOG_DEBUG("BI-swap enabled");
 147                 mxc_nf_info->flags.biswap_enabled = 1;
 148         }
 149
 150         /*
 151          * testing host endianness
 152          */
 153         x = 1;
 154         if (*(char *) &x == 1)
 155                 mxc_nf_info->flags.host_little_endian = 1;
 156         else
 157                 mxc_nf_info->flags.host_little_endian = 0;
 158         return ERROR_OK;
 159 }
 160
 161 COMMAND_HANDLER(handle_mxc_biswap_command)
 162 {
 163         struct nand_device *nand = NULL;
 164         struct mxc_nf_controller *mxc_nf_info = NULL;
 165
 166         if (CMD_ARGC < 1 || CMD_ARGC > 2)
 167                 return ERROR_COMMAND_SYNTAX_ERROR;
 168
 169         int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
 170         if (retval != ERROR_OK) {
 171                 command_print(CMD_CTX, "invalid nand device number or name: %s", CMD_ARGV[0]);
 172                 return ERROR_COMMAND_ARGUMENT_INVALID;
 173         }
 174
 175         mxc_nf_info = nand->controller_priv;
 176         if (CMD_ARGC == 2) {
 177                 if (strcmp(CMD_ARGV[1], "enable") == 0)
 178                         mxc_nf_info->flags.biswap_enabled = true;
 179                 else
 180                         mxc_nf_info->flags.biswap_enabled = false;
 181         }
 182         if (mxc_nf_info->flags.biswap_enabled)
 183                 command_print(CMD_CTX, "BI-swapping enabled on %s", nand->name);
 184         else
 185                 command_print(CMD_CTX, "BI-swapping disabled on %s", nand->name);
 186
 187         return ERROR_OK;
 188 }
 189
 190 static const struct command_registration mxc_sub_command_handlers[] = {
 191         {
 192                 .name = "biswap",
 193                 .handler = handle_mxc_biswap_command,
 194                 .help = "Turns on/off bad block information swaping from main area, "
 195                         "without parameter query status.",
 196                 .usage = "bank_id ['enable'|'disable']",
 197         },
 198         COMMAND_REGISTRATION_DONE
 199 };
 200
 201 static const struct command_registration mxc_nand_command_handler[] = {
 202         {
 203                 .name = "mxc",
 204                 .mode = COMMAND_ANY,
 205                 .help = "MXC NAND flash controller commands",
 206                 .chain = mxc_sub_command_handlers
 207         },
 208         COMMAND_REGISTRATION_DONE
 209 };
 210
 211 static int mxc_init(struct nand_device *nand)
 212 {
 213         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 214         struct target *target = nand->target;
 215
 216         int validate_target_result;
 217         uint16_t buffsize_register_content;
 218         uint32_t sreg_content;
 219         uint32_t SREG = MX2_FMCR;
 220         uint32_t SEL_16BIT = MX2_FMCR_NF_16BIT_SEL;
 221         uint32_t SEL_FMS = MX2_FMCR_NF_FMS;
 222         int retval;
 223         uint16_t nand_status_content;
 224         /*
 225          * validate target state
 226          */
 227         validate_target_result = validate_target_state(nand);
 228         if (validate_target_result != ERROR_OK)
 229                 return validate_target_result;
 230
 231         if (nfc_is_v1()) {
 232                 target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
 233                 mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
 234         } else
 235                 mxc_nf_info->flags.one_kb_sram = 0;
 236
 237         if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
 238                 SREG = MX3_PCSR;
 239                 SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
 240                 SEL_FMS = MX3_PCSR_NF_FMS;
 241         } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
 242                 SREG = MX25_RCSR;
 243                 SEL_16BIT = MX25_RCSR_NF_16BIT_SEL;
 244                 SEL_FMS = MX25_RCSR_NF_FMS;
 245         } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
 246                 SREG = MX35_RCSR;
 247                 SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
 248                 SEL_FMS = MX35_RCSR_NF_FMS;
 249         }
 250
 251         target_read_u32(target, SREG, &sreg_content);
 252         if (!nand->bus_width) {
 253                 /* bus_width not yet defined. Read it from MXC_FMCR */
 254                 nand->bus_width = (sreg_content & SEL_16BIT) ? 16 : 8;
 255         } else {
 256                 /* bus_width forced in soft. Sync it to MXC_FMCR */
 257                 sreg_content |= ((nand->bus_width == 16) ? SEL_16BIT : 0x00000000);
 258                 target_write_u32(target, SREG, sreg_content);
 259         }
 260         if (nand->bus_width == 16)
 261                 LOG_DEBUG("MXC_NF : bus is 16-bit width");
 262         else
 263                 LOG_DEBUG("MXC_NF : bus is 8-bit width");
 264
 265         if (!nand->page_size)
 266                 nand->page_size = (sreg_content & SEL_FMS) ? 2048 : 512;
 267         else {
 268                 sreg_content |= ((nand->page_size == 2048) ? SEL_FMS : 0x00000000);
 269                 target_write_u32(target, SREG, sreg_content);
 270         }
 271         if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
 272                 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
 273                         "pagesize 2048 is incompatible with it");
 274         } else
 275                 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
 276
 277         if (nfc_is_v2() && sreg_content & MX35_RCSR_NF_4K)
 278                 LOG_ERROR("MXC driver does not have support for 4k pagesize.");
 279
 280         initialize_nf_controller(nand);
 281
 282         retval = ERROR_OK;
 283         retval |= mxc_command(nand, NAND_CMD_STATUS);
 284         retval |= mxc_address(nand, 0x00);
 285         retval |= do_data_output(nand);
 286         if (retval != ERROR_OK) {
 287                 LOG_ERROR(get_status_register_err_msg);
 288                 return ERROR_FAIL;
 289         }
 290         target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
 291         if (!(nand_status_content & 0x0080)) {
 292                 LOG_INFO("NAND read-only");
 293                 mxc_nf_info->flags.nand_readonly = 1;
 294         } else
 295                 mxc_nf_info->flags.nand_readonly = 0;
 296         return ERROR_OK;
 297 }
 298
 299 static int mxc_read_data(struct nand_device *nand, void *data)
 300 {
 301         int validate_target_result;
 302         int try_data_output_from_nand_chip;
 303         /*
 304          * validate target state
 305          */
 306         validate_target_result = validate_target_state(nand);
 307         if (validate_target_result != ERROR_OK)
 308                 return validate_target_result;
 309
 310         /*
 311          * get data from nand chip
 312          */
 313         try_data_output_from_nand_chip = do_data_output(nand);
 314         if (try_data_output_from_nand_chip != ERROR_OK) {
 315                 LOG_ERROR("mxc_read_data : read data failed : '%x'",
 316                         try_data_output_from_nand_chip);
 317                 return try_data_output_from_nand_chip;
 318         }
 319
 320         if (nand->bus_width == 16)
 321                 get_next_halfword_from_sram_buffer(nand, data);
 322         else
 323                 get_next_byte_from_sram_buffer(nand, data);
 324
 325         return ERROR_OK;
 326 }
 327
 328 static int mxc_write_data(struct nand_device *nand, uint16_t data)
 329 {
 330         LOG_ERROR("write_data() not implemented");
 331         return ERROR_NAND_OPERATION_FAILED;
 332 }
 333
 334 static int mxc_reset(struct nand_device *nand)
 335 {
 336         /*
 337          * validate target state
 338          */
 339         int validate_target_result;
 340         validate_target_result = validate_target_state(nand);
 341         if (validate_target_result != ERROR_OK)
 342                 return validate_target_result;
 343         initialize_nf_controller(nand);
 344         return ERROR_OK;
 345 }
 346
 347 static int mxc_command(struct nand_device *nand, uint8_t command)
 348 {
 349         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 350         struct target *target = nand->target;
 351         int validate_target_result;
 352         int poll_result;
 353         /*
 354          * validate target state
 355          */
 356         validate_target_result = validate_target_state(nand);
 357         if (validate_target_result != ERROR_OK)
 358                 return validate_target_result;
 359
 360         switch (command) {
 361                 case NAND_CMD_READOOB:
 362                         command = NAND_CMD_READ0;
 363                         /* set read point for data_read() and read_block_data() to
 364                          * spare area in SRAM buffer
 365                          */
 366                         if (nfc_is_v1())
 367                                 in_sram_address = MXC_NF_V1_SPARE_BUFFER0;
 368                         else
 369                                 in_sram_address = MXC_NF_V2_SPARE_BUFFER0;
 370                         break;
 371                 case NAND_CMD_READ1:
 372                         command = NAND_CMD_READ0;
 373                         /*
 374                          * offset == one half of page size
 375                          */
 376                         in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
 377                         break;
 378                 default:
 379                         in_sram_address = MXC_NF_MAIN_BUFFER0;
 380                         break;
 381         }
 382
 383         target_write_u16(target, MXC_NF_FCMD, command);
 384         /*
 385          * start command input operation (set MXC_NF_BIT_OP_DONE==0)
 386          */
 387         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
 388         poll_result = poll_for_complete_op(nand, "command");
 389         if (poll_result != ERROR_OK)
 390                 return poll_result;
 391         /*
 392          * reset cursor to begin of the buffer
 393          */
 394         sign_of_sequental_byte_read = 0;
 395         /* Handle special read command and adjust NF_CFG2(FDO) */
 396         switch (command) {
 397                 case NAND_CMD_READID:
 398                         mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
 399                         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 400                         break;
 401                 case NAND_CMD_STATUS:
 402                         mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
 403                         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 404                         target_write_u16 (target, MXC_NF_BUFADDR, 0);
 405                         in_sram_address = 0;
 406                         break;
 407                 case NAND_CMD_READ0:
 408                         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 409                         mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 410                         break;
 411                 default:
 412                         /* Ohter command use the default 'One page data out' FDO */
 413                         mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 414                         break;
 415         }
 416         return ERROR_OK;
 417 }
 418
 419 static int mxc_address(struct nand_device *nand, uint8_t address)
 420 {
 421         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 422         struct target *target = nand->target;
 423         int validate_target_result;
 424         int poll_result;
 425         /*
 426          * validate target state
 427          */
 428         validate_target_result = validate_target_state(nand);
 429         if (validate_target_result != ERROR_OK)
 430                 return validate_target_result;
 431
 432         target_write_u16(target, MXC_NF_FADDR, address);
 433         /*
 434          * start address input operation (set MXC_NF_BIT_OP_DONE==0)
 435          */
 436         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
 437         poll_result = poll_for_complete_op(nand, "address");
 438         if (poll_result != ERROR_OK)
 439                 return poll_result;
 440
 441         return ERROR_OK;
 442 }
 443
 444 static int mxc_nand_ready(struct nand_device *nand, int tout)
 445 {
 446         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 447         struct target *target = nand->target;
 448         uint16_t poll_complete_status;
 449         int validate_target_result;
 450
 451         /*
 452          * validate target state
 453          */
 454         validate_target_result = validate_target_state(nand);
 455         if (validate_target_result != ERROR_OK)
 456                 return validate_target_result;
 457
 458         do {
 459                 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
 460                 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
 461                         return tout;
 462
 463                 alive_sleep(1);
 464         } while (tout-- > 0);
 465         return tout;
 466 }
 467
 468 static int mxc_write_page(struct nand_device *nand, uint32_t page,
 469         uint8_t *data, uint32_t data_size,
 470         uint8_t *oob, uint32_t oob_size)
 471 {
 472         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 473         struct target *target = nand->target;
 474         int retval;
 475         uint16_t nand_status_content;
 476         uint16_t swap1, swap2, new_swap1;
 477         uint8_t bufs;
 478         int poll_result;
 479
 480         if (data_size % 2) {
 481                 LOG_ERROR(data_block_size_err_msg, data_size);
 482                 return ERROR_NAND_OPERATION_FAILED;
 483         }
 484         if (oob_size % 2) {
 485                 LOG_ERROR(data_block_size_err_msg, oob_size);
 486                 return ERROR_NAND_OPERATION_FAILED;
 487         }
 488         if (!data) {
 489                 LOG_ERROR("nothing to program");
 490                 return ERROR_NAND_OPERATION_FAILED;
 491         }
 492
 493         /*
 494          * validate target state
 495          */
 496         retval = validate_target_state(nand);
 497         if (retval != ERROR_OK)
 498                 return retval;
 499
 500         in_sram_address = MXC_NF_MAIN_BUFFER0;
 501         sign_of_sequental_byte_read = 0;
 502         retval = ERROR_OK;
 503         retval |= mxc_command(nand, NAND_CMD_SEQIN);
 504         retval |= mxc_address(nand, 0); /* col */
 505         retval |= mxc_address(nand, 0); /* col */
 506         retval |= mxc_address(nand, page & 0xff);       /* page address */
 507         retval |= mxc_address(nand, (page >> 8) & 0xff);/* page address */
 508         retval |= mxc_address(nand, (page >> 16) & 0xff);       /* page address */
 509
 510         target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
 511         if (oob) {
 512                 if (mxc_nf_info->flags.hw_ecc_enabled) {
 513                         /*
 514                          * part of spare block will be overrided by hardware
 515                          * ECC generator
 516                          */
 517                         LOG_DEBUG("part of spare block will be overrided "
 518                                 "by hardware ECC generator");
 519                 }
 520                 if (nfc_is_v1())
 521                         target_write_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
 522                 else {
 523                         uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
 524                         while (oob_size > 0) {
 525                                 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
 526                                 target_write_buffer(target, addr, len, oob);
 527                                 addr = align_address_v2(nand, addr + len);
 528                                 oob += len;
 529                                 oob_size -= len;
 530                         }
 531                 }
 532         }
 533
 534         if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
 535                 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
 536                 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
 537                 if (oob) {
 538                         LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
 539                         return ERROR_NAND_OPERATION_FAILED;
 540                 }
 541                 swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
 542                 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 543                 swap2 = (swap1 << 8) | (swap2 & 0xFF);
 544                 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
 545                 if (nfc_is_v1())
 546                         target_write_u16(target, MXC_NF_V1_SPARE_BUFFER3 + 4, swap2);
 547                 else
 548                         target_write_u16(target, MXC_NF_V2_SPARE_BUFFER3, swap2);
 549         }
 550
 551         /*
 552          * start data input operation (set MXC_NF_BIT_OP_DONE==0)
 553          */
 554         if (nfc_is_v1() && nand->page_size > 512)
 555                 bufs = 4;
 556         else
 557                 bufs = 1;
 558
 559         for (uint8_t i = 0; i < bufs; ++i) {
 560                 target_write_u16(target, MXC_NF_BUFADDR, i);
 561                 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
 562                 poll_result = poll_for_complete_op(nand, "data input");
 563                 if (poll_result != ERROR_OK)
 564                         return poll_result;
 565         }
 566
 567         retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
 568         if (retval != ERROR_OK)
 569                 return retval;
 570
 571         /*
 572          * check status register
 573          */
 574         retval = ERROR_OK;
 575         retval |= mxc_command(nand, NAND_CMD_STATUS);
 576         target_write_u16 (target, MXC_NF_BUFADDR, 0);
 577         mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
 578         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 579         retval |= do_data_output(nand);
 580         if (retval != ERROR_OK) {
 581                 LOG_ERROR(get_status_register_err_msg);
 582                 return retval;
 583         }
 584         target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
 585         if (nand_status_content & 0x0001) {
 586                 /*
 587                  * page not correctly written
 588                  */
 589                 return ERROR_NAND_OPERATION_FAILED;
 590         }
 591 #ifdef _MXC_PRINT_STAT
 592         LOG_INFO("%d bytes newly written", data_size);
 593 #endif
 594         return ERROR_OK;
 595 }
 596
 597 static int mxc_read_page(struct nand_device *nand, uint32_t page,
 598         uint8_t *data, uint32_t data_size,
 599         uint8_t *oob, uint32_t oob_size)
 600 {
 601         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 602         struct target *target = nand->target;
 603         int retval;
 604         uint8_t bufs;
 605         uint16_t swap1, swap2, new_swap1;
 606
 607         if (data_size % 2) {
 608                 LOG_ERROR(data_block_size_err_msg, data_size);
 609                 return ERROR_NAND_OPERATION_FAILED;
 610         }
 611         if (oob_size % 2) {
 612                 LOG_ERROR(data_block_size_err_msg, oob_size);
 613                 return ERROR_NAND_OPERATION_FAILED;
 614         }
 615
 616         /*
 617          * validate target state
 618          */
 619         retval = validate_target_state(nand);
 620         if (retval != ERROR_OK)
 621                 return retval;
 622                                 /* Reset address_cycles before mxc_command ?? */
 623         retval = mxc_command(nand, NAND_CMD_READ0);
 624         if (retval != ERROR_OK)
 625                 return retval;
 626         retval = mxc_address(nand, 0);  /* col */
 627         if (retval != ERROR_OK)
 628                 return retval;
 629         retval = mxc_address(nand, 0);  /* col */
 630         if (retval != ERROR_OK)
 631                 return retval;
 632         retval = mxc_address(nand, page & 0xff);/* page address */
 633         if (retval != ERROR_OK)
 634                 return retval;
 635         retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
 636         if (retval != ERROR_OK)
 637                 return retval;
 638         retval = mxc_address(nand, (page >> 16) & 0xff);/* page address */
 639         if (retval != ERROR_OK)
 640                 return retval;
 641         retval = mxc_command(nand, NAND_CMD_READSTART);
 642         if (retval != ERROR_OK)
 643                 return retval;
 644
 645         if (nfc_is_v1() && nand->page_size > 512)
 646                 bufs = 4;
 647         else
 648                 bufs = 1;
 649
 650         for (uint8_t i = 0; i < bufs; ++i) {
 651                 target_write_u16(target, MXC_NF_BUFADDR, i);
 652                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 653                 retval = do_data_output(nand);
 654                 if (retval != ERROR_OK) {
 655                         LOG_ERROR("MXC_NF : Error reading page %d", i);
 656                         return retval;
 657                 }
 658         }
 659
 660         if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
 661                 uint32_t SPARE_BUFFER3;
 662                 /* BI-swap -  work-around of mxc NFC for NAND device with page == 2k */
 663                 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
 664                 if (nfc_is_v1())
 665                         SPARE_BUFFER3 = MXC_NF_V1_SPARE_BUFFER3 + 4;
 666                 else
 667                         SPARE_BUFFER3 = MXC_NF_V2_SPARE_BUFFER3;
 668                 target_read_u16(target, SPARE_BUFFER3, &swap2);
 669                 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 670                 swap2 = (swap1 << 8) | (swap2 & 0xFF);
 671                 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
 672                 target_write_u16(target, SPARE_BUFFER3, swap2);
 673         }
 674
 675         if (data)
 676                 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
 677         if (oob) {
 678                 if (nfc_is_v1())
 679                         target_read_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
 680                 else {
 681                         uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
 682                         while (oob_size > 0) {
 683                                 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
 684                                 target_read_buffer(target, addr, len, oob);
 685                                 addr = align_address_v2(nand, addr + len);
 686                                 oob += len;
 687                                 oob_size -= len;
 688                         }
 689                 }
 690         }
 691
 692 #ifdef _MXC_PRINT_STAT
 693         if (data_size > 0) {
 694                 /* When Operation Status is read (when page is erased),
 695                  * this function is used but data_size is null.
 696                  */
 697                 LOG_INFO("%d bytes newly read", data_size);
 698         }
 699 #endif
 700         return ERROR_OK;
 701 }
 702
 703 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr)
 704 {
 705         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 706         uint32_t ret = addr;
 707         if (addr > MXC_NF_V2_SPARE_BUFFER0 &&
 708                         (addr & 0x1F) == MXC_NF_SPARE_BUFFER_LEN)
 709                 ret += MXC_NF_SPARE_BUFFER_MAX - MXC_NF_SPARE_BUFFER_LEN;
 710         else if (addr >= (mxc_nf_info->mxc_base_addr + (uint32_t)nand->page_size))
 711                 ret = MXC_NF_V2_SPARE_BUFFER0;
 712         return ret;
 713 }
 714
 715 static int initialize_nf_controller(struct nand_device *nand)
 716 {
 717         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 718         struct target *target = nand->target;
 719         uint16_t work_mode = 0;
 720         uint16_t temp;
 721         /*
 722          * resets NAND flash controller in zero time ? I dont know.
 723          */
 724         target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
 725         if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
 726                 work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
 727
 728         if (target->endianness == TARGET_BIG_ENDIAN) {
 729                 LOG_DEBUG("MXC_NF : work in Big Endian mode");
 730                 work_mode |= MXC_NF_BIT_BE_EN;
 731         } else
 732                 LOG_DEBUG("MXC_NF : work in Little Endian mode");
 733         if (mxc_nf_info->flags.hw_ecc_enabled) {
 734                 LOG_DEBUG("MXC_NF : work with ECC mode");
 735                 work_mode |= MXC_NF_BIT_ECC_EN;
 736         } else
 737                 LOG_DEBUG("MXC_NF : work without ECC mode");
 738         if (nfc_is_v2()) {
 739                 target_write_u16(target, MXC_NF_V2_SPAS, OOB_SIZE / 2);
 740                 if (nand->page_size) {
 741                         uint16_t pages_per_block = nand->erase_size / nand->page_size;
 742                         work_mode |= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block) - 6);
 743                 }
 744                 work_mode |= MXC_NF_BIT_ECC_4BIT;
 745         }
 746         target_write_u16(target, MXC_NF_CFG1, work_mode);
 747
 748         /*
 749          * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
 750          */
 751         target_write_u16(target, MXC_NF_BUFCFG, 2);
 752         target_read_u16(target, MXC_NF_FWP, &temp);
 753         if ((temp & 0x0007) == 1) {
 754                 LOG_ERROR("NAND flash is tight-locked, reset needed");
 755                 return ERROR_FAIL;
 756         }
 757
 758         /*
 759          * unlock NAND flash for write
 760          */
 761         if (nfc_is_v1()) {
 762                 target_write_u16(target, MXC_NF_V1_UNLOCKSTART, 0x0000);
 763                 target_write_u16(target, MXC_NF_V1_UNLOCKEND, 0xFFFF);
 764         } else {
 765                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART0, 0x0000);
 766                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART1, 0x0000);
 767                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART2, 0x0000);
 768                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART3, 0x0000);
 769                 target_write_u16(target, MXC_NF_V2_UNLOCKEND0, 0xFFFF);
 770                 target_write_u16(target, MXC_NF_V2_UNLOCKEND1, 0xFFFF);
 771                 target_write_u16(target, MXC_NF_V2_UNLOCKEND2, 0xFFFF);
 772                 target_write_u16(target, MXC_NF_V2_UNLOCKEND3, 0xFFFF);
 773         }
 774         target_write_u16(target, MXC_NF_FWP, 4);
 775
 776         /*
 777          * 0x0000 means that first SRAM buffer @base_addr will be used
 778          */
 779         target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
 780         /*
 781          * address of SRAM buffer
 782          */
 783         in_sram_address = MXC_NF_MAIN_BUFFER0;
 784         sign_of_sequental_byte_read = 0;
 785         return ERROR_OK;
 786 }
 787
 788 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
 789 {
 790         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 791         struct target *target = nand->target;
 792         static uint8_t even_byte;
 793         uint16_t temp;
 794         /*
 795          * host-big_endian ??
 796          */
 797         if (sign_of_sequental_byte_read == 0)
 798                 even_byte = 0;
 799
 800         if (in_sram_address > (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
 801                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 802                 *value = 0;
 803                 sign_of_sequental_byte_read = 0;
 804                 even_byte = 0;
 805                 return ERROR_NAND_OPERATION_FAILED;
 806         } else {
 807                 if (nfc_is_v2())
 808                         in_sram_address = align_address_v2(nand, in_sram_address);
 809
 810                 target_read_u16(target, in_sram_address, &temp);
 811                 if (even_byte) {
 812                         *value = temp >> 8;
 813                         even_byte = 0;
 814                         in_sram_address += 2;
 815                 } else {
 816                         *value = temp & 0xff;
 817                         even_byte = 1;
 818                 }
 819         }
 820         sign_of_sequental_byte_read = 1;
 821         return ERROR_OK;
 822 }
 823
 824 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
 825 {
 826         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 827         struct target *target = nand->target;
 828
 829         if (in_sram_address > (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
 830                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 831                 *value = 0;
 832                 return ERROR_NAND_OPERATION_FAILED;
 833         } else {
 834                 if (nfc_is_v2())
 835                         in_sram_address = align_address_v2(nand, in_sram_address);
 836
 837                 target_read_u16(target, in_sram_address, value);
 838                 in_sram_address += 2;
 839         }
 840         return ERROR_OK;
 841 }
 842
 843 static int poll_for_complete_op(struct nand_device *nand, const char *text)
 844 {
 845         if (mxc_nand_ready(nand, 1000) == -1) {
 846                 LOG_ERROR("%s sending timeout", text);
 847                 return ERROR_NAND_OPERATION_FAILED;
 848         }
 849         return ERROR_OK;
 850 }
 851
 852 static int validate_target_state(struct nand_device *nand)
 853 {
 854         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 855         struct target *target = nand->target;
 856
 857         if (target->state != TARGET_HALTED) {
 858                 LOG_ERROR(target_not_halted_err_msg);
 859                 return ERROR_NAND_OPERATION_FAILED;
 860         }
 861
 862         if (mxc_nf_info->flags.target_little_endian !=
 863                         (target->endianness == TARGET_LITTLE_ENDIAN)) {
 864                 /*
 865                  * endianness changed after NAND controller probed
 866                  */
 867                 return ERROR_NAND_OPERATION_FAILED;
 868         }
 869         return ERROR_OK;
 870 }
 871
 872 int ecc_status_v1(struct nand_device *nand)
 873 {
 874         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 875         struct target *target = nand->target;
 876         uint16_t ecc_status;
 877
 878         target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
 879         switch (ecc_status & 0x000c) {
 880                 case 1 << 2:
 881                         LOG_INFO("main area read with 1 (correctable) error");
 882                         break;
 883                 case 2 << 2:
 884                         LOG_INFO("main area read with more than 1 (incorrectable) error");
 885                         return ERROR_NAND_OPERATION_FAILED;
 886                         break;
 887         }
 888         switch (ecc_status & 0x0003) {
 889                 case 1:
 890                         LOG_INFO("spare area read with 1 (correctable) error");
 891                         break;
 892                 case 2:
 893                         LOG_INFO("main area read with more than 1 (incorrectable) error");
 894                         return ERROR_NAND_OPERATION_FAILED;
 895                         break;
 896         }
 897         return ERROR_OK;
 898 }
 899
 900 int ecc_status_v2(struct nand_device *nand)
 901 {
 902         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 903         struct target *target = nand->target;
 904         uint16_t ecc_status;
 905         uint8_t no_subpages;
 906         uint8_t err;
 907
 908         no_subpages = nand->page_size >> 9;
 909
 910         target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
 911         do {
 912                 err = ecc_status & 0xF;
 913                 if (err > 4) {
 914                         LOG_INFO("UnCorrectable RS-ECC Error");
 915                         return ERROR_NAND_OPERATION_FAILED;
 916                 } else if (err > 0)
 917                         LOG_INFO("%d Symbol Correctable RS-ECC Error", err);
 918                 ecc_status >>= 4;
 919         } while (--no_subpages);
 920         return ERROR_OK;
 921 }
 922
 923 static int do_data_output(struct nand_device *nand)
 924 {
 925         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 926         struct target *target = nand->target;
 927         int poll_result;
 928         switch (mxc_nf_info->fin) {
 929                 case MXC_NF_FIN_DATAOUT:
 930                         /*
 931                          * start data output operation (set MXC_NF_BIT_OP_DONE==0)
 932                          */
 933                         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
 934                         poll_result = poll_for_complete_op(nand, "data output");
 935                         if (poll_result != ERROR_OK)
 936                                 return poll_result;
 937
 938                         mxc_nf_info->fin = MXC_NF_FIN_NONE;
 939                         /*
 940                          * ECC stuff
 941                          */
 942                         if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE && mxc_nf_info->flags.hw_ecc_enabled) {
 943                                 int ecc_status;
 944                                 if (nfc_is_v1())
 945                                         ecc_status = ecc_status_v1(nand);
 946                                 else
 947                                         ecc_status = ecc_status_v2(nand);
 948                                 if (ecc_status != ERROR_OK)
 949                                         return ecc_status;
 950                         }
 951                         break;
 952                 case MXC_NF_FIN_NONE:
 953                         break;
 954         }
 955         return ERROR_OK;
 956 }
 957
 958 struct nand_flash_controller mxc_nand_flash_controller = {
 959         .name = "mxc",
 960         .nand_device_command = &mxc_nand_device_command,
 961         .commands = mxc_nand_command_handler,
 962         .init = &mxc_init,
 963         .reset = &mxc_reset,
 964         .command = &mxc_command,
 965         .address = &mxc_address,
 966         .write_data = &mxc_write_data,
 967         .read_data = &mxc_read_data,
 968         .write_page = &mxc_write_page,
 969         .read_page = &mxc_read_page,
 970         .nand_ready = &mxc_nand_ready,
 971 };