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   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Alexei Babich                                   *
   3  *   Rezonans plc., Chelyabinsk, Russia                                    *
   4  *   impatt@mail.ru                                                        *
   5  *                                                                         *
   6  *   Copyright (C) 2010 by Gaetan CARLIER                                  *
   7  *   Trump s.a., Belgium                                                   *
   8  *                                                                         *
   9  *   Copyright (C) 2011 by Erik Ahlen                                      *
  10  *   Avalon Innovation, Sweden                                             *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program; if not, write to the                         *
  24  *   Free Software Foundation, Inc.,                                       *
  25  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  26  ***************************************************************************/
  27
  28 /*
  29  * Freescale iMX OpenOCD NAND Flash controller support.
  30  * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
  31  */
  32
  33 /*
  34  * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
  35  * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
  36  * "nand write # file 0", "nand verify"
  37  *
  38  * get_next_halfword_from_sram_buffer() not tested
  39  * !! all function only tested with 2k page nand device; mxc_write_page
  40  *    writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
  41  * !! oob must be be used due to NFS bug
  42 */
  43 #ifdef HAVE_CONFIG_H
  44 #include "config.h"
  45 #endif
  46
  47 #include "imp.h"
  48 #include "mxc.h"
  49 #include <target/target.h>
  50
  51 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
  52                                         mxc_nf_info->mxc_version == MXC_VERSION_MX31)
  53 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
  54                                         mxc_nf_info->mxc_version == MXC_VERSION_MX35)
  55
  56 /* This permits to print (in LOG_INFO) how much bytes
  57  * has been written after a page read or write.
  58  * This is useful when OpenOCD is used with a graphical
  59  * front-end to estimate progression of the global read/write
  60  */
  61 #undef _MXC_PRINT_STAT
  62 /* #define _MXC_PRINT_STAT */
  63
  64 static const char target_not_halted_err_msg[] =
  65         "target must be halted to use mxc NAND flash controller";
  66 static const char data_block_size_err_msg[] =
  67         "minimal granularity is one half-word, %" PRId32 " is incorrect";
  68 static const char sram_buffer_bounds_err_msg[] =
  69         "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  70 static const char get_status_register_err_msg[] = "can't get NAND status";
  71 static uint32_t in_sram_address;
  72 static unsigned char sign_of_sequental_byte_read;
  73
  74 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr);
  75 static int initialize_nf_controller(struct nand_device *nand);
  76 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
  77 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
  78 static int poll_for_complete_op(struct nand_device *nand, const char *text);
  79 static int validate_target_state(struct nand_device *nand);
  80 static int do_data_output(struct nand_device *nand);
  81
  82 static int mxc_command(struct nand_device *nand, uint8_t command);
  83 static int mxc_address(struct nand_device *nand, uint8_t address);
  84
  85 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
  86 {
  87         struct mxc_nf_controller *mxc_nf_info;
  88         int hwecc_needed;
  89         int x;
  90
  91         mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
  92         if (mxc_nf_info == NULL) {
  93                 LOG_ERROR("no memory for nand controller");
  94                 return ERROR_FAIL;
  95         }
  96         nand->controller_priv = mxc_nf_info;
  97
  98         if (CMD_ARGC < 4) {
  99                 LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]\"");
 100                 return ERROR_FAIL;
 101         }
 102
 103         /*
 104          * check board type
 105          */
 106         if (strcmp(CMD_ARGV[2], "mx25") == 0) {
 107                 mxc_nf_info->mxc_version = MXC_VERSION_MX25;
 108                 mxc_nf_info->mxc_base_addr = 0xBB000000;
 109                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
 110         } else if (strcmp(CMD_ARGV[2], "mx27") == 0) {
 111                 mxc_nf_info->mxc_version = MXC_VERSION_MX27;
 112                 mxc_nf_info->mxc_base_addr = 0xD8000000;
 113                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
 114         } else if (strcmp(CMD_ARGV[2], "mx31") == 0) {
 115                 mxc_nf_info->mxc_version = MXC_VERSION_MX31;
 116                 mxc_nf_info->mxc_base_addr = 0xB8000000;
 117                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
 118         } else if (strcmp(CMD_ARGV[2], "mx35") == 0) {
 119                 mxc_nf_info->mxc_version = MXC_VERSION_MX35;
 120                 mxc_nf_info->mxc_base_addr = 0xBB000000;
 121                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
 122         }
 123
 124         /*
 125          * check hwecc requirements
 126          */
 127         hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
 128         if (hwecc_needed == 0)
 129                 mxc_nf_info->flags.hw_ecc_enabled = 1;
 130         else
 131                 mxc_nf_info->flags.hw_ecc_enabled = 0;
 132
 133         mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 134         mxc_nf_info->fin = MXC_NF_FIN_NONE;
 135         mxc_nf_info->flags.target_little_endian =
 136         (nand->target->endianness == TARGET_LITTLE_ENDIAN);
 137
 138         /*
 139          * should factory bad block indicator be swaped
 140          * as a workaround for how the nfc handles pages.
 141          */
 142         if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
 143                 LOG_DEBUG("BI-swap enabled");
 144                 mxc_nf_info->flags.biswap_enabled = 1;
 145         }
 146
 147         /*
 148          * testing host endianness
 149          */
 150         x = 1;
 151         if (*(char *) &x == 1)
 152                 mxc_nf_info->flags.host_little_endian = 1;
 153         else
 154                 mxc_nf_info->flags.host_little_endian = 0;
 155         return ERROR_OK;
 156 }
 157
 158 COMMAND_HANDLER(handle_mxc_biswap_command)
 159 {
 160         struct nand_device *nand = NULL;
 161         struct mxc_nf_controller *mxc_nf_info = NULL;
 162
 163         if (CMD_ARGC < 1 || CMD_ARGC > 2)
 164                 return ERROR_COMMAND_SYNTAX_ERROR;
 165
 166         int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
 167         if (retval != ERROR_OK) {
 168                 command_print(CMD_CTX, "invalid nand device number or name: %s", CMD_ARGV[0]);
 169                 return ERROR_COMMAND_ARGUMENT_INVALID;
 170         }
 171
 172         mxc_nf_info = nand->controller_priv;
 173         if (CMD_ARGC == 2) {
 174                 if (strcmp(CMD_ARGV[1], "enable") == 0)
 175                         mxc_nf_info->flags.biswap_enabled = true;
 176                 else
 177                         mxc_nf_info->flags.biswap_enabled = false;
 178         }
 179         if (mxc_nf_info->flags.biswap_enabled)
 180                 command_print(CMD_CTX, "BI-swapping enabled on %s", nand->name);
 181         else
 182                 command_print(CMD_CTX, "BI-swapping disabled on %s", nand->name);
 183
 184         return ERROR_OK;
 185 }
 186
 187 static const struct command_registration mxc_sub_command_handlers[] = {
 188         {
 189                 .name = "biswap",
 190                 .handler = handle_mxc_biswap_command ,
 191                 .help = "Turns on/off bad block information swaping from main area, "
 192                                 "without parameter query status.",
 193                 .usage = "bank_id ['enable'|'disable']",
 194         },
 195         COMMAND_REGISTRATION_DONE
 196 };
 197
 198 static const struct command_registration mxc_nand_command_handler[] = {
 199         {
 200                 .name = "mxc",
 201                 .mode = COMMAND_ANY,
 202                 .help = "MXC NAND flash controller commands",
 203                 .chain = mxc_sub_command_handlers
 204         },
 205         COMMAND_REGISTRATION_DONE
 206 };
 207
 208 static int mxc_init(struct nand_device *nand)
 209 {
 210         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 211         struct target *target = nand->target;
 212
 213         int validate_target_result;
 214         uint16_t buffsize_register_content;
 215         uint32_t sreg_content;
 216         uint32_t SREG = MX2_FMCR;
 217         uint32_t SEL_16BIT = MX2_FMCR_NF_16BIT_SEL;
 218         uint32_t SEL_FMS = MX2_FMCR_NF_FMS;
 219         int retval;
 220         uint16_t nand_status_content;
 221         /*
 222          * validate target state
 223          */
 224         validate_target_result = validate_target_state(nand);
 225         if (validate_target_result != ERROR_OK)
 226                 return validate_target_result;
 227
 228         if (nfc_is_v1()) {
 229                 target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
 230                 mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
 231         } else
 232                 mxc_nf_info->flags.one_kb_sram = 0;
 233
 234         if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
 235                 SREG = MX3_PCSR;
 236                 SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
 237                 SEL_FMS = MX3_PCSR_NF_FMS;
 238         } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
 239                 SREG = MX25_RCSR;
 240                 SEL_16BIT = MX25_RCSR_NF_16BIT_SEL;
 241                 SEL_FMS = MX25_RCSR_NF_FMS;
 242         } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
 243                 SREG = MX35_RCSR;
 244                 SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
 245                 SEL_FMS = MX35_RCSR_NF_FMS;
 246         }
 247
 248         target_read_u32(target, SREG, &sreg_content);
 249         if (!nand->bus_width) {
 250                 /* bus_width not yet defined. Read it from MXC_FMCR */
 251                 nand->bus_width = (sreg_content & SEL_16BIT) ? 16 : 8;
 252         } else {
 253                 /* bus_width forced in soft. Sync it to MXC_FMCR */
 254                 sreg_content |= ((nand->bus_width == 16) ? SEL_16BIT : 0x00000000);
 255                 target_write_u32(target, SREG, sreg_content);
 256         }
 257         if (nand->bus_width == 16)
 258                 LOG_DEBUG("MXC_NF : bus is 16-bit width");
 259         else
 260                 LOG_DEBUG("MXC_NF : bus is 8-bit width");
 261
 262         if (!nand->page_size) {
 263                 nand->page_size = (sreg_content & SEL_FMS) ? 2048 : 512;
 264         } else {
 265                 sreg_content |= ((nand->page_size == 2048) ? SEL_FMS : 0x00000000);
 266                 target_write_u32(target, SREG, sreg_content);
 267         }
 268         if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
 269                 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
 270                           "pagesize 2048 is incompatible with it");
 271         } else {
 272                 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
 273         }
 274
 275         if (nfc_is_v2() && sreg_content & MX35_RCSR_NF_4K)
 276                 LOG_ERROR("MXC driver does not have support for 4k pagesize.");
 277
 278         initialize_nf_controller(nand);
 279
 280         retval = ERROR_OK;
 281         retval |= mxc_command(nand, NAND_CMD_STATUS);
 282         retval |= mxc_address(nand, 0x00);
 283         retval |= do_data_output(nand);
 284         if (retval != ERROR_OK) {
 285                 LOG_ERROR(get_status_register_err_msg);
 286                 return ERROR_FAIL;
 287         }
 288         target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
 289         if (!(nand_status_content & 0x0080)) {
 290                 LOG_INFO("NAND read-only");
 291                 mxc_nf_info->flags.nand_readonly = 1;
 292         } else {
 293                 mxc_nf_info->flags.nand_readonly = 0;
 294         }
 295         return ERROR_OK;
 296 }
 297
 298 static int mxc_read_data(struct nand_device *nand, void *data)
 299 {
 300         int validate_target_result;
 301         int try_data_output_from_nand_chip;
 302         /*
 303          * validate target state
 304          */
 305         validate_target_result = validate_target_state(nand);
 306         if (validate_target_result != ERROR_OK)
 307                 return validate_target_result;
 308
 309         /*
 310          * get data from nand chip
 311          */
 312         try_data_output_from_nand_chip = do_data_output(nand);
 313         if (try_data_output_from_nand_chip != ERROR_OK) {
 314                 LOG_ERROR("mxc_read_data : read data failed : '%x'",
 315                                   try_data_output_from_nand_chip);
 316                 return try_data_output_from_nand_chip;
 317         }
 318
 319         if (nand->bus_width == 16)
 320                 get_next_halfword_from_sram_buffer(nand, data);
 321         else
 322                 get_next_byte_from_sram_buffer(nand, data);
 323
 324         return ERROR_OK;
 325 }
 326
 327 static int mxc_write_data(struct nand_device *nand, uint16_t data)
 328 {
 329         LOG_ERROR("write_data() not implemented");
 330         return ERROR_NAND_OPERATION_FAILED;
 331 }
 332
 333 static int mxc_reset(struct nand_device *nand)
 334 {
 335         /*
 336          * validate target state
 337          */
 338         int validate_target_result;
 339         validate_target_result = validate_target_state(nand);
 340         if (validate_target_result != ERROR_OK)
 341                 return validate_target_result;
 342         initialize_nf_controller(nand);
 343         return ERROR_OK;
 344 }
 345
 346 static int mxc_command(struct nand_device *nand, uint8_t command)
 347 {
 348         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 349         struct target *target = nand->target;
 350         int validate_target_result;
 351         int poll_result;
 352         /*
 353          * validate target state
 354          */
 355         validate_target_result = validate_target_state(nand);
 356         if (validate_target_result != ERROR_OK)
 357                 return validate_target_result;
 358
 359         switch (command) {
 360         case NAND_CMD_READOOB:
 361                 command = NAND_CMD_READ0;
 362                 /* set read point for data_read() and read_block_data() to
 363                  * spare area in SRAM buffer
 364                  */
 365                 if (nfc_is_v1())
 366                         in_sram_address = MXC_NF_V1_SPARE_BUFFER0;
 367                 else
 368                         in_sram_address = MXC_NF_V2_SPARE_BUFFER0;
 369                 break;
 370         case NAND_CMD_READ1:
 371                 command = NAND_CMD_READ0;
 372                 /*
 373                  * offset == one half of page size
 374                  */
 375                 in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
 376                 break;
 377         default:
 378                 in_sram_address = MXC_NF_MAIN_BUFFER0;
 379                 break;
 380         }
 381
 382         target_write_u16(target, MXC_NF_FCMD, command);
 383         /*
 384          * start command input operation (set MXC_NF_BIT_OP_DONE==0)
 385          */
 386         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
 387         poll_result = poll_for_complete_op(nand, "command");
 388         if (poll_result != ERROR_OK)
 389                 return poll_result;
 390         /*
 391          * reset cursor to begin of the buffer
 392          */
 393         sign_of_sequental_byte_read = 0;
 394         /* Handle special read command and adjust NF_CFG2(FDO) */
 395         switch (command) {
 396         case NAND_CMD_READID:
 397                 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
 398                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 399                 break;
 400         case NAND_CMD_STATUS:
 401                 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
 402                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 403                 target_write_u16 (target, MXC_NF_BUFADDR, 0);
 404                 in_sram_address = 0;
 405                 break;
 406         case NAND_CMD_READ0:
 407                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 408                 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 409                 break;
 410         default:
 411                 /* Ohter command use the default 'One page data out' FDO */
 412                 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 413                 break;
 414         }
 415         return ERROR_OK;
 416 }
 417
 418 static int mxc_address(struct nand_device *nand, uint8_t address)
 419 {
 420         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 421         struct target *target = nand->target;
 422         int validate_target_result;
 423         int poll_result;
 424         /*
 425          * validate target state
 426          */
 427         validate_target_result = validate_target_state(nand);
 428         if (validate_target_result != ERROR_OK)
 429                 return validate_target_result;
 430
 431         target_write_u16(target, MXC_NF_FADDR, address);
 432         /*
 433          * start address input operation (set MXC_NF_BIT_OP_DONE==0)
 434          */
 435         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
 436         poll_result = poll_for_complete_op(nand, "address");
 437         if (poll_result != ERROR_OK)
 438                 return poll_result;
 439
 440         return ERROR_OK;
 441 }
 442
 443 static int mxc_nand_ready(struct nand_device *nand, int tout)
 444 {
 445         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 446         struct target *target = nand->target;
 447         uint16_t poll_complete_status;
 448         int validate_target_result;
 449
 450         /*
 451          * validate target state
 452          */
 453         validate_target_result = validate_target_state(nand);
 454         if (validate_target_result != ERROR_OK)
 455                 return validate_target_result;
 456
 457         do {
 458                 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
 459                 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
 460                         return tout;
 461
 462                 alive_sleep(1);
 463         }
 464         while (tout-- > 0);
 465         return tout;
 466 }
 467
 468 static int mxc_write_page(struct nand_device *nand, uint32_t page,
 469                                                         uint8_t *data, uint32_t data_size,
 470                                                         uint8_t *oob, uint32_t oob_size)
 471 {
 472         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 473         struct target *target = nand->target;
 474         int retval;
 475         uint16_t nand_status_content;
 476         uint16_t swap1, swap2, new_swap1;
 477         uint8_t bufs;
 478         int poll_result;
 479
 480         if (data_size % 2) {
 481                 LOG_ERROR(data_block_size_err_msg, data_size);
 482                 return ERROR_NAND_OPERATION_FAILED;
 483         }
 484         if (oob_size % 2) {
 485                 LOG_ERROR(data_block_size_err_msg, oob_size);
 486                 return ERROR_NAND_OPERATION_FAILED;
 487         }
 488         if (!data) {
 489                 LOG_ERROR("nothing to program");
 490                 return ERROR_NAND_OPERATION_FAILED;
 491         }
 492
 493         /*
 494          * validate target state
 495          */
 496         retval = validate_target_state(nand);
 497         if (retval != ERROR_OK)
 498                 return retval;
 499
 500         in_sram_address = MXC_NF_MAIN_BUFFER0;
 501         sign_of_sequental_byte_read = 0;
 502         retval = ERROR_OK;
 503         retval |= mxc_command(nand, NAND_CMD_SEQIN);
 504         retval |= mxc_address(nand, 0); /* col */
 505         retval |= mxc_address(nand, 0); /* col */
 506         retval |= mxc_address(nand, page & 0xff); /* page address */
 507         retval |= mxc_address(nand, (page >> 8) & 0xff); /* page address */
 508         retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
 509
 510         target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
 511         if (oob) {
 512                 if (mxc_nf_info->flags.hw_ecc_enabled) {
 513                         /*
 514                          * part of spare block will be overrided by hardware
 515                          * ECC generator
 516                          */
 517                         LOG_DEBUG("part of spare block will be overrided "
 518                                   "by hardware ECC generator");
 519                 }
 520                 if (nfc_is_v1())
 521                         target_write_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
 522                 else {
 523                         uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
 524                         while (oob_size > 0) {
 525                                 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
 526                                 target_write_buffer(target, addr, len, oob);
 527                                 addr = align_address_v2(nand, addr + len);
 528                                 oob += len;
 529                                 oob_size -= len;
 530                         }
 531                 }
 532         }
 533
 534         if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
 535                 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
 536                 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
 537                 if (oob) {
 538                         LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
 539                         return ERROR_NAND_OPERATION_FAILED;
 540                 }
 541                 swap2 = 0xffff;  /* Spare buffer unused forced to 0xffff */
 542                 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 543                 swap2 = (swap1 << 8) | (swap2 & 0xFF);
 544                 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
 545                 if (nfc_is_v1())
 546                         target_write_u16(target, MXC_NF_V1_SPARE_BUFFER3, swap2);
 547                 else
 548                         target_write_u16(target, MXC_NF_V2_SPARE_BUFFER3, swap2);
 549         }
 550
 551         /*
 552          * start data input operation (set MXC_NF_BIT_OP_DONE==0)
 553          */
 554         if (nfc_is_v1() && nand->page_size > 512)
 555                 bufs = 4;
 556         else
 557                 bufs = 1;
 558
 559         for (uint8_t i = 0 ; i < bufs ; ++i) {
 560                 target_write_u16(target, MXC_NF_BUFADDR, i);
 561                 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
 562                 poll_result = poll_for_complete_op(nand, "data input");
 563                 if (poll_result != ERROR_OK)
 564                         return poll_result;
 565         }
 566
 567         retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
 568         if (retval != ERROR_OK)
 569                 return retval;
 570
 571         /*
 572          * check status register
 573          */
 574         retval = ERROR_OK;
 575         retval |= mxc_command(nand, NAND_CMD_STATUS);
 576         target_write_u16 (target, MXC_NF_BUFADDR, 0);
 577         mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
 578         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 579         retval |= do_data_output(nand);
 580         if (retval != ERROR_OK) {
 581                 LOG_ERROR(get_status_register_err_msg);
 582                 return retval;
 583         }
 584         target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
 585         if (nand_status_content & 0x0001) {
 586                 /*
 587                  * page not correctly written
 588                  */
 589                 return ERROR_NAND_OPERATION_FAILED;
 590         }
 591 #ifdef _MXC_PRINT_STAT
 592         LOG_INFO("%d bytes newly written", data_size);
 593 #endif
 594         return ERROR_OK;
 595 }
 596
 597 static int mxc_read_page(struct nand_device *nand, uint32_t page,
 598                                                    uint8_t *data, uint32_t data_size,
 599                                                    uint8_t *oob, uint32_t oob_size)
 600 {
 601         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 602         struct target *target = nand->target;
 603         int retval;
 604         uint8_t bufs;
 605         uint16_t swap1, swap2, new_swap1;
 606
 607         if (data_size % 2) {
 608                 LOG_ERROR(data_block_size_err_msg, data_size);
 609                 return ERROR_NAND_OPERATION_FAILED;
 610         }
 611         if (oob_size % 2) {
 612                 LOG_ERROR(data_block_size_err_msg, oob_size);
 613                 return ERROR_NAND_OPERATION_FAILED;
 614         }
 615
 616         /*
 617          * validate target state
 618          */
 619         retval = validate_target_state(nand);
 620         if (retval != ERROR_OK) {
 621                 return retval;
 622         }
 623         /* Reset address_cycles before mxc_command ?? */
 624         retval = mxc_command(nand, NAND_CMD_READ0);
 625         if (retval != ERROR_OK) return retval;
 626         retval = mxc_address(nand, 0); /* col */
 627         if (retval != ERROR_OK) return retval;
 628         retval = mxc_address(nand, 0); /* col */
 629         if (retval != ERROR_OK) return retval;
 630         retval = mxc_address(nand, page & 0xff); /* page address */
 631         if (retval != ERROR_OK) return retval;
 632         retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
 633         if (retval != ERROR_OK) return retval;
 634         retval = mxc_address(nand, (page >> 16) & 0xff); /* page address */
 635         if (retval != ERROR_OK) return retval;
 636         retval = mxc_command(nand, NAND_CMD_READSTART);
 637         if (retval != ERROR_OK) return retval;
 638
 639         if (nfc_is_v1() && nand->page_size > 512)
 640                 bufs = 4;
 641         else
 642                 bufs = 1;
 643
 644         for (uint8_t i = 0 ; i < bufs ; ++i) {
 645                 target_write_u16(target, MXC_NF_BUFADDR, i);
 646                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 647                 retval = do_data_output(nand);
 648                 if (retval != ERROR_OK) {
 649                         LOG_ERROR("MXC_NF : Error reading page %d", i);
 650                         return retval;
 651                 }
 652         }
 653
 654         if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
 655                 uint32_t SPARE_BUFFER3;
 656                 /* BI-swap -  work-around of mxc NFC for NAND device with page == 2k */
 657                 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
 658                 if (nfc_is_v1())
 659                         SPARE_BUFFER3 = MXC_NF_V1_SPARE_BUFFER3;
 660                 else
 661                         SPARE_BUFFER3 = MXC_NF_V2_SPARE_BUFFER3;
 662                 target_read_u16(target, SPARE_BUFFER3, &swap2);
 663                 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 664                 swap2 = (swap1 << 8) | (swap2 & 0xFF);
 665                 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
 666                 target_write_u16(target, SPARE_BUFFER3, swap2);
 667         }
 668
 669         if (data)
 670                 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
 671         if (oob) {
 672                 if (nfc_is_v1())
 673                         target_read_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
 674                 else {
 675                         uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
 676                         while (oob_size > 0) {
 677                                 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
 678                                 target_read_buffer(target, addr, len, oob);
 679                                 addr = align_address_v2(nand, addr + len);
 680                                 oob += len;
 681                                 oob_size -= len;
 682                         }
 683                 }
 684         }
 685
 686 #ifdef _MXC_PRINT_STAT
 687         if (data_size > 0) {
 688                 /* When Operation Status is read (when page is erased),
 689                  * this function is used but data_size is null.
 690                  */
 691                 LOG_INFO("%d bytes newly read", data_size);
 692         }
 693 #endif
 694         return ERROR_OK;
 695 }
 696
 697 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr)
 698 {
 699         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 700         uint32_t ret = addr;
 701         if (addr > MXC_NF_V2_SPARE_BUFFER0 &&
 702            (addr & 0x1F) == MXC_NF_SPARE_BUFFER_LEN) {
 703                 ret += MXC_NF_SPARE_BUFFER_MAX - MXC_NF_SPARE_BUFFER_LEN;
 704         } else if (addr >= (mxc_nf_info->mxc_base_addr + (uint32_t)nand->page_size))
 705                 ret = MXC_NF_V2_SPARE_BUFFER0;
 706         return ret;
 707 }
 708
 709 static int initialize_nf_controller(struct nand_device *nand)
 710 {
 711         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 712         struct target *target = nand->target;
 713         uint16_t work_mode = 0;
 714         uint16_t temp;
 715         /*
 716          * resets NAND flash controller in zero time ? I dont know.
 717          */
 718         target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
 719         if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
 720                 work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
 721
 722         if (target->endianness == TARGET_BIG_ENDIAN) {
 723                 LOG_DEBUG("MXC_NF : work in Big Endian mode");
 724                 work_mode |= MXC_NF_BIT_BE_EN;
 725         } else {
 726                 LOG_DEBUG("MXC_NF : work in Little Endian mode");
 727         }
 728         if (mxc_nf_info->flags.hw_ecc_enabled) {
 729                 LOG_DEBUG("MXC_NF : work with ECC mode");
 730                 work_mode |= MXC_NF_BIT_ECC_EN;
 731         } else {
 732                 LOG_DEBUG("MXC_NF : work without ECC mode");
 733         }
 734         if (nfc_is_v2()) {
 735                 if (nand->page_size) {
 736                         uint16_t pages_per_block = nand->erase_size / nand->page_size;
 737                         work_mode |= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block) - 6);
 738                 }
 739                 work_mode |= MXC_NF_BIT_ECC_4BIT;
 740         }
 741         target_write_u16(target, MXC_NF_CFG1, work_mode);
 742
 743         /*
 744          * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
 745          */
 746         target_write_u16(target, MXC_NF_BUFCFG, 2);
 747         target_read_u16(target, MXC_NF_FWP, &temp);
 748         if ((temp & 0x0007) == 1) {
 749                 LOG_ERROR("NAND flash is tight-locked, reset needed");
 750                 return ERROR_FAIL;
 751         }
 752
 753         /*
 754          * unlock NAND flash for write
 755          */
 756         if (nfc_is_v1()) {
 757                 target_write_u16(target, MXC_NF_V1_UNLOCKSTART, 0x0000);
 758                 target_write_u16(target, MXC_NF_V1_UNLOCKEND, 0xFFFF);
 759         } else {
 760                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART0, 0x0000);
 761                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART1, 0x0000);
 762                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART2, 0x0000);
 763                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART3, 0x0000);
 764                 target_write_u16(target, MXC_NF_V2_UNLOCKEND0, 0xFFFF);
 765                 target_write_u16(target, MXC_NF_V2_UNLOCKEND1, 0xFFFF);
 766                 target_write_u16(target, MXC_NF_V2_UNLOCKEND2, 0xFFFF);
 767                 target_write_u16(target, MXC_NF_V2_UNLOCKEND3, 0xFFFF);
 768         }
 769         target_write_u16(target, MXC_NF_FWP, 4);
 770
 771         /*
 772          * 0x0000 means that first SRAM buffer @base_addr will be used
 773          */
 774         target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
 775         /*
 776          * address of SRAM buffer
 777          */
 778         in_sram_address = MXC_NF_MAIN_BUFFER0;
 779         sign_of_sequental_byte_read = 0;
 780         return ERROR_OK;
 781 }
 782
 783 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
 784 {
 785         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 786         struct target *target = nand->target;
 787         static uint8_t even_byte = 0;
 788         uint16_t temp;
 789         /*
 790          * host-big_endian ??
 791          */
 792         if (sign_of_sequental_byte_read == 0)
 793                 even_byte = 0;
 794
 795         if (in_sram_address >
 796                 (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
 797                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 798                 *value = 0;
 799                 sign_of_sequental_byte_read = 0;
 800                 even_byte = 0;
 801                 return ERROR_NAND_OPERATION_FAILED;
 802         } else {
 803                 if (nfc_is_v2())
 804                         in_sram_address = align_address_v2(nand, in_sram_address);
 805
 806                 target_read_u16(target, in_sram_address, &temp);
 807                 if (even_byte) {
 808                         *value = temp >> 8;
 809                         even_byte = 0;
 810                         in_sram_address += 2;
 811                 } else {
 812                         *value = temp & 0xff;
 813                         even_byte = 1;
 814                 }
 815         }
 816         sign_of_sequental_byte_read = 1;
 817         return ERROR_OK;
 818 }
 819
 820 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
 821 {
 822         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 823         struct target *target = nand->target;
 824
 825         if (in_sram_address >
 826                 (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
 827                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 828                 *value = 0;
 829                 return ERROR_NAND_OPERATION_FAILED;
 830         } else {
 831                 if (nfc_is_v2())
 832                         in_sram_address = align_address_v2(nand, in_sram_address);
 833
 834                 target_read_u16(target, in_sram_address, value);
 835                 in_sram_address += 2;
 836         }
 837         return ERROR_OK;
 838 }
 839
 840 static int poll_for_complete_op(struct nand_device *nand, const char *text)
 841 {
 842         if (mxc_nand_ready(nand, 1000) == -1) {
 843                 LOG_ERROR("%s sending timeout", text);
 844                 return ERROR_NAND_OPERATION_FAILED;
 845         }
 846         return ERROR_OK;
 847 }
 848
 849 static int validate_target_state(struct nand_device *nand)
 850 {
 851         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 852         struct target *target = nand->target;
 853
 854         if (target->state != TARGET_HALTED) {
 855                 LOG_ERROR(target_not_halted_err_msg);
 856                 return ERROR_NAND_OPERATION_FAILED;
 857         }
 858
 859         if (mxc_nf_info->flags.target_little_endian !=
 860             (target->endianness == TARGET_LITTLE_ENDIAN)) {
 861                 /*
 862                  * endianness changed after NAND controller probed
 863                  */
 864                 return ERROR_NAND_OPERATION_FAILED;
 865         }
 866         return ERROR_OK;
 867 }
 868
 869 int ecc_status_v1(struct nand_device *nand)
 870 {
 871         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 872         struct target *target = nand->target;
 873         uint16_t ecc_status;
 874
 875         target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
 876         switch (ecc_status & 0x000c) {
 877         case 1 << 2:
 878                 LOG_INFO("main area read with 1 (correctable) error");
 879                 break;
 880         case 2 << 2:
 881                 LOG_INFO("main area read with more than 1 (incorrectable) error");
 882                 return ERROR_NAND_OPERATION_FAILED;
 883                 break;
 884         }
 885         switch (ecc_status & 0x0003) {
 886         case 1:
 887                 LOG_INFO("spare area read with 1 (correctable) error");
 888                 break;
 889         case 2:
 890                 LOG_INFO("main area read with more than 1 (incorrectable) error");
 891                 return ERROR_NAND_OPERATION_FAILED;
 892                 break;
 893         }
 894         return ERROR_OK;
 895 }
 896
 897 int ecc_status_v2(struct nand_device *nand)
 898 {
 899         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 900         struct target *target = nand->target;
 901         uint16_t ecc_status;
 902         uint8_t no_subpages;
 903         uint8_t err;
 904
 905         no_subpages = nand->page_size >> 9;
 906
 907         target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
 908         do {
 909                 err = ecc_status & 0xF;
 910                 if (err > 4) {
 911                         LOG_INFO("UnCorrectable RS-ECC Error");
 912                         return ERROR_NAND_OPERATION_FAILED;
 913                 } else if (err > 0)
 914                         LOG_INFO("%d Symbol Correctable RS-ECC Error", err);
 915                 ecc_status >>= 4;
 916         } while (--no_subpages);
 917         return ERROR_OK;
 918 }
 919
 920 static int do_data_output(struct nand_device *nand)
 921 {
 922         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 923         struct target *target = nand->target;
 924         int poll_result;
 925         switch (mxc_nf_info->fin) {
 926         case MXC_NF_FIN_DATAOUT:
 927                 /*
 928                  * start data output operation (set MXC_NF_BIT_OP_DONE==0)
 929                  */
 930                 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
 931                 poll_result = poll_for_complete_op(nand, "data output");
 932                 if (poll_result != ERROR_OK)
 933                         return poll_result;
 934
 935                 mxc_nf_info->fin = MXC_NF_FIN_NONE;
 936                 /*
 937                  * ECC stuff
 938                  */
 939                 if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE &&
 940                         mxc_nf_info->flags.hw_ecc_enabled) {
 941                         int ecc_status;
 942                         if (nfc_is_v1())
 943                                 ecc_status = ecc_status_v1(nand);
 944                         else
 945                                 ecc_status = ecc_status_v2(nand);
 946                         if (ecc_status != ERROR_OK)
 947                                 return ecc_status;
 948                 }
 949                 break;
 950         case MXC_NF_FIN_NONE:
 951                 break;
 952         }
 953         return ERROR_OK;
 954 }
 955
 956 struct nand_flash_controller mxc_nand_flash_controller = {
 957         .name                                   = "mxc",
 958         .nand_device_command    = &mxc_nand_device_command,
 959         .commands                               = mxc_nand_command_handler,
 960         .init                                   = &mxc_init,
 961         .reset                                  = &mxc_reset,
 962         .command                                = &mxc_command,
 963         .address                                = &mxc_address,
 964         .write_data                             = &mxc_write_data,
 965         .read_data                              = &mxc_read_data,
 966         .write_page                             = &mxc_write_page,
 967         .read_page                              = &mxc_read_page,
 968         .nand_ready                             = &mxc_nand_ready,
 969 };