1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
9 * Copyright (C) 2011 by Erik Ahlen *
10 * Avalon Innovation, Sweden *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
24 ***************************************************************************/
27 * Freescale iMX OpenOCD NAND Flash controller support.
28 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
32 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
33 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
34 * "nand write # file 0", "nand verify"
36 * get_next_halfword_from_sram_buffer() not tested
37 * !! all function only tested with 2k page nand device; mxc_write_page
38 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
39 * !! oob must be be used due to NFS bug
40 * !! oob must be 64 bytes per 2KiB page
48 #include <target/target.h>
52 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
53 mxc_nf_info->mxc_version == MXC_VERSION_MX31)
54 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
55 mxc_nf_info->mxc_version == MXC_VERSION_MX35)
57 /* This permits to print (in LOG_INFO) how much bytes
58 * has been written after a page read or write.
59 * This is useful when OpenOCD is used with a graphical
60 * front-end to estimate progression of the global read/write
62 #undef _MXC_PRINT_STAT
63 /* #define _MXC_PRINT_STAT */
65 static const char target_not_halted_err_msg[] =
66 "target must be halted to use mxc NAND flash controller";
67 static const char data_block_size_err_msg[] =
68 "minimal granularity is one half-word, %" PRIu32 " is incorrect";
69 static const char sram_buffer_bounds_err_msg[] =
70 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
71 static const char get_status_register_err_msg[] = "can't get NAND status";
72 static uint32_t in_sram_address;
73 static unsigned char sign_of_sequental_byte_read;
75 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr);
76 static int initialize_nf_controller(struct nand_device *nand);
77 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
78 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
79 static int poll_for_complete_op(struct nand_device *nand, const char *text);
80 static int validate_target_state(struct nand_device *nand);
81 static int do_data_output(struct nand_device *nand);
83 static int mxc_command(struct nand_device *nand, uint8_t command);
84 static int mxc_address(struct nand_device *nand, uint8_t address);
86 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
88 struct mxc_nf_controller *mxc_nf_info;
91 mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
93 LOG_ERROR("no memory for nand controller");
96 nand->controller_priv = mxc_nf_info;
99 LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]\"");
106 if (strcmp(CMD_ARGV[2], "mx25") == 0) {
107 mxc_nf_info->mxc_version = MXC_VERSION_MX25;
108 mxc_nf_info->mxc_base_addr = 0xBB000000;
109 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
110 } else if (strcmp(CMD_ARGV[2], "mx27") == 0) {
111 mxc_nf_info->mxc_version = MXC_VERSION_MX27;
112 mxc_nf_info->mxc_base_addr = 0xD8000000;
113 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
114 } else if (strcmp(CMD_ARGV[2], "mx31") == 0) {
115 mxc_nf_info->mxc_version = MXC_VERSION_MX31;
116 mxc_nf_info->mxc_base_addr = 0xB8000000;
117 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
118 } else if (strcmp(CMD_ARGV[2], "mx35") == 0) {
119 mxc_nf_info->mxc_version = MXC_VERSION_MX35;
120 mxc_nf_info->mxc_base_addr = 0xBB000000;
121 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
125 * check hwecc requirements
127 hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
128 if (hwecc_needed == 0)
129 mxc_nf_info->flags.hw_ecc_enabled = 1;
131 mxc_nf_info->flags.hw_ecc_enabled = 0;
133 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
134 mxc_nf_info->fin = MXC_NF_FIN_NONE;
135 mxc_nf_info->flags.target_little_endian =
136 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
139 * should factory bad block indicator be swapped
140 * as a workaround for how the nfc handles pages.
142 if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
143 LOG_DEBUG("BI-swap enabled");
144 mxc_nf_info->flags.biswap_enabled = 1;
150 COMMAND_HANDLER(handle_mxc_biswap_command)
152 struct nand_device *nand = NULL;
153 struct mxc_nf_controller *mxc_nf_info = NULL;
155 if (CMD_ARGC < 1 || CMD_ARGC > 2)
156 return ERROR_COMMAND_SYNTAX_ERROR;
158 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
159 if (retval != ERROR_OK) {
160 command_print(CMD, "invalid nand device number or name: %s", CMD_ARGV[0]);
161 return ERROR_COMMAND_ARGUMENT_INVALID;
164 mxc_nf_info = nand->controller_priv;
166 if (strcmp(CMD_ARGV[1], "enable") == 0)
167 mxc_nf_info->flags.biswap_enabled = true;
169 mxc_nf_info->flags.biswap_enabled = false;
171 if (mxc_nf_info->flags.biswap_enabled)
172 command_print(CMD, "BI-swapping enabled on %s", nand->name);
174 command_print(CMD, "BI-swapping disabled on %s", nand->name);
179 static const struct command_registration mxc_sub_command_handlers[] = {
182 .mode = COMMAND_EXEC,
183 .handler = handle_mxc_biswap_command,
184 .help = "Turns on/off bad block information swapping from main area, "
185 "without parameter query status.",
186 .usage = "bank_id ['enable'|'disable']",
188 COMMAND_REGISTRATION_DONE
191 static const struct command_registration mxc_nand_command_handler[] = {
195 .help = "MXC NAND flash controller commands",
196 .chain = mxc_sub_command_handlers,
199 COMMAND_REGISTRATION_DONE
202 static int mxc_init(struct nand_device *nand)
204 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
205 struct target *target = nand->target;
207 int validate_target_result;
208 uint16_t buffsize_register_content;
209 uint32_t sreg_content;
210 uint32_t sreg = MX2_FMCR;
211 uint32_t sel_16bit = MX2_FMCR_NF_16BIT_SEL;
212 uint32_t sel_fms = MX2_FMCR_NF_FMS;
214 uint16_t nand_status_content;
216 * validate target state
218 validate_target_result = validate_target_state(nand);
219 if (validate_target_result != ERROR_OK)
220 return validate_target_result;
223 target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
224 mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
226 mxc_nf_info->flags.one_kb_sram = 0;
228 if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
230 sel_16bit = MX3_PCSR_NF_16BIT_SEL;
231 sel_fms = MX3_PCSR_NF_FMS;
232 } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
234 sel_16bit = MX25_RCSR_NF_16BIT_SEL;
235 sel_fms = MX25_RCSR_NF_FMS;
236 } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
238 sel_16bit = MX35_RCSR_NF_16BIT_SEL;
239 sel_fms = MX35_RCSR_NF_FMS;
242 target_read_u32(target, sreg, &sreg_content);
243 if (!nand->bus_width) {
244 /* bus_width not yet defined. Read it from MXC_FMCR */
245 nand->bus_width = (sreg_content & sel_16bit) ? 16 : 8;
247 /* bus_width forced in soft. Sync it to MXC_FMCR */
248 sreg_content |= ((nand->bus_width == 16) ? sel_16bit : 0x00000000);
249 target_write_u32(target, sreg, sreg_content);
251 if (nand->bus_width == 16)
252 LOG_DEBUG("MXC_NF : bus is 16-bit width");
254 LOG_DEBUG("MXC_NF : bus is 8-bit width");
256 if (!nand->page_size)
257 nand->page_size = (sreg_content & sel_fms) ? 2048 : 512;
259 sreg_content |= ((nand->page_size == 2048) ? sel_fms : 0x00000000);
260 target_write_u32(target, sreg, sreg_content);
262 if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
263 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
264 "pagesize 2048 is incompatible with it");
266 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
268 if (nfc_is_v2() && sreg_content & MX35_RCSR_NF_4K)
269 LOG_ERROR("MXC driver does not have support for 4k pagesize.");
271 initialize_nf_controller(nand);
274 retval |= mxc_command(nand, NAND_CMD_STATUS);
275 retval |= mxc_address(nand, 0x00);
276 retval |= do_data_output(nand);
277 if (retval != ERROR_OK) {
278 LOG_ERROR(get_status_register_err_msg);
281 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
282 if (!(nand_status_content & 0x0080)) {
283 LOG_INFO("NAND read-only");
284 mxc_nf_info->flags.nand_readonly = 1;
286 mxc_nf_info->flags.nand_readonly = 0;
290 static int mxc_read_data(struct nand_device *nand, void *data)
292 int validate_target_result;
293 int try_data_output_from_nand_chip;
295 * validate target state
297 validate_target_result = validate_target_state(nand);
298 if (validate_target_result != ERROR_OK)
299 return validate_target_result;
302 * get data from nand chip
304 try_data_output_from_nand_chip = do_data_output(nand);
305 if (try_data_output_from_nand_chip != ERROR_OK) {
306 LOG_ERROR("mxc_read_data : read data failed : '%x'",
307 try_data_output_from_nand_chip);
308 return try_data_output_from_nand_chip;
311 if (nand->bus_width == 16)
312 get_next_halfword_from_sram_buffer(nand, data);
314 get_next_byte_from_sram_buffer(nand, data);
319 static int mxc_write_data(struct nand_device *nand, uint16_t data)
321 LOG_ERROR("write_data() not implemented");
322 return ERROR_NAND_OPERATION_FAILED;
325 static int mxc_reset(struct nand_device *nand)
328 * validate target state
330 int validate_target_result;
331 validate_target_result = validate_target_state(nand);
332 if (validate_target_result != ERROR_OK)
333 return validate_target_result;
334 initialize_nf_controller(nand);
338 static int mxc_command(struct nand_device *nand, uint8_t command)
340 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
341 struct target *target = nand->target;
342 int validate_target_result;
345 * validate target state
347 validate_target_result = validate_target_state(nand);
348 if (validate_target_result != ERROR_OK)
349 return validate_target_result;
352 case NAND_CMD_READOOB:
353 command = NAND_CMD_READ0;
354 /* set read point for data_read() and read_block_data() to
355 * spare area in SRAM buffer
358 in_sram_address = MXC_NF_V1_SPARE_BUFFER0;
360 in_sram_address = MXC_NF_V2_SPARE_BUFFER0;
363 command = NAND_CMD_READ0;
365 * offset == one half of page size
367 in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
370 in_sram_address = MXC_NF_MAIN_BUFFER0;
374 target_write_u16(target, MXC_NF_FCMD, command);
376 * start command input operation (set MXC_NF_BIT_OP_DONE==0)
378 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
379 poll_result = poll_for_complete_op(nand, "command");
380 if (poll_result != ERROR_OK)
383 * reset cursor to begin of the buffer
385 sign_of_sequental_byte_read = 0;
386 /* Handle special read command and adjust NF_CFG2(FDO) */
388 case NAND_CMD_READID:
389 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
390 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
392 case NAND_CMD_STATUS:
393 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
394 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
395 target_write_u16 (target, MXC_NF_BUFADDR, 0);
399 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
400 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
403 /* Other command use the default 'One page data out' FDO */
404 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
410 static int mxc_address(struct nand_device *nand, uint8_t address)
412 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
413 struct target *target = nand->target;
414 int validate_target_result;
417 * validate target state
419 validate_target_result = validate_target_state(nand);
420 if (validate_target_result != ERROR_OK)
421 return validate_target_result;
423 target_write_u16(target, MXC_NF_FADDR, address);
425 * start address input operation (set MXC_NF_BIT_OP_DONE==0)
427 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
428 poll_result = poll_for_complete_op(nand, "address");
429 if (poll_result != ERROR_OK)
435 static int mxc_nand_ready(struct nand_device *nand, int tout)
437 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
438 struct target *target = nand->target;
439 uint16_t poll_complete_status;
440 int validate_target_result;
443 * validate target state
445 validate_target_result = validate_target_state(nand);
446 if (validate_target_result != ERROR_OK)
447 return validate_target_result;
450 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
451 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
455 } while (tout-- > 0);
459 static int mxc_write_page(struct nand_device *nand, uint32_t page,
460 uint8_t *data, uint32_t data_size,
461 uint8_t *oob, uint32_t oob_size)
463 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
464 struct target *target = nand->target;
466 uint16_t nand_status_content;
467 uint16_t swap1, swap2, new_swap1;
472 LOG_ERROR(data_block_size_err_msg, data_size);
473 return ERROR_NAND_OPERATION_FAILED;
476 LOG_ERROR(data_block_size_err_msg, oob_size);
477 return ERROR_NAND_OPERATION_FAILED;
480 LOG_ERROR("nothing to program");
481 return ERROR_NAND_OPERATION_FAILED;
485 * validate target state
487 retval = validate_target_state(nand);
488 if (retval != ERROR_OK)
491 in_sram_address = MXC_NF_MAIN_BUFFER0;
492 sign_of_sequental_byte_read = 0;
494 retval |= mxc_command(nand, NAND_CMD_SEQIN);
495 retval |= mxc_address(nand, 0); /* col */
496 retval |= mxc_address(nand, 0); /* col */
497 retval |= mxc_address(nand, page & 0xff); /* page address */
498 retval |= mxc_address(nand, (page >> 8) & 0xff);/* page address */
499 retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
501 target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
503 if (mxc_nf_info->flags.hw_ecc_enabled) {
505 * part of spare block will be overridden by hardware
508 LOG_DEBUG("part of spare block will be overridden "
509 "by hardware ECC generator");
512 target_write_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
514 uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
515 while (oob_size > 0) {
516 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
517 target_write_buffer(target, addr, len, oob);
518 addr = align_address_v2(nand, addr + len);
525 if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
526 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
527 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
529 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
530 return ERROR_NAND_OPERATION_FAILED;
532 swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
533 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
534 swap2 = (swap1 << 8) | (swap2 & 0xFF);
535 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
537 target_write_u16(target, MXC_NF_V1_SPARE_BUFFER3 + 4, swap2);
539 target_write_u16(target, MXC_NF_V2_SPARE_BUFFER3, swap2);
543 * start data input operation (set MXC_NF_BIT_OP_DONE==0)
545 if (nfc_is_v1() && nand->page_size > 512)
550 for (uint8_t i = 0; i < bufs; ++i) {
551 target_write_u16(target, MXC_NF_BUFADDR, i);
552 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
553 poll_result = poll_for_complete_op(nand, "data input");
554 if (poll_result != ERROR_OK)
558 retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
559 if (retval != ERROR_OK)
563 * check status register
566 retval |= mxc_command(nand, NAND_CMD_STATUS);
567 target_write_u16 (target, MXC_NF_BUFADDR, 0);
568 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
569 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
570 retval |= do_data_output(nand);
571 if (retval != ERROR_OK) {
572 LOG_ERROR(get_status_register_err_msg);
575 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
576 if (nand_status_content & 0x0001) {
578 * page not correctly written
580 return ERROR_NAND_OPERATION_FAILED;
582 #ifdef _MXC_PRINT_STAT
583 LOG_INFO("%d bytes newly written", data_size);
588 static int mxc_read_page(struct nand_device *nand, uint32_t page,
589 uint8_t *data, uint32_t data_size,
590 uint8_t *oob, uint32_t oob_size)
592 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
593 struct target *target = nand->target;
596 uint16_t swap1, swap2, new_swap1;
599 LOG_ERROR(data_block_size_err_msg, data_size);
600 return ERROR_NAND_OPERATION_FAILED;
603 LOG_ERROR(data_block_size_err_msg, oob_size);
604 return ERROR_NAND_OPERATION_FAILED;
608 * validate target state
610 retval = validate_target_state(nand);
611 if (retval != ERROR_OK)
613 /* Reset address_cycles before mxc_command ?? */
614 retval = mxc_command(nand, NAND_CMD_READ0);
615 if (retval != ERROR_OK)
617 retval = mxc_address(nand, 0); /* col */
618 if (retval != ERROR_OK)
620 retval = mxc_address(nand, 0); /* col */
621 if (retval != ERROR_OK)
623 retval = mxc_address(nand, page & 0xff);/* page address */
624 if (retval != ERROR_OK)
626 retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
627 if (retval != ERROR_OK)
629 retval = mxc_address(nand, (page >> 16) & 0xff);/* page address */
630 if (retval != ERROR_OK)
632 retval = mxc_command(nand, NAND_CMD_READSTART);
633 if (retval != ERROR_OK)
636 if (nfc_is_v1() && nand->page_size > 512)
641 for (uint8_t i = 0; i < bufs; ++i) {
642 target_write_u16(target, MXC_NF_BUFADDR, i);
643 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
644 retval = do_data_output(nand);
645 if (retval != ERROR_OK) {
646 LOG_ERROR("MXC_NF : Error reading page %d", i);
651 if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
652 uint32_t spare_buffer3;
653 /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
654 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
656 spare_buffer3 = MXC_NF_V1_SPARE_BUFFER3 + 4;
658 spare_buffer3 = MXC_NF_V2_SPARE_BUFFER3;
659 target_read_u16(target, spare_buffer3, &swap2);
660 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
661 swap2 = (swap1 << 8) | (swap2 & 0xFF);
662 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
663 target_write_u16(target, spare_buffer3, swap2);
667 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
670 target_read_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
672 uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
673 while (oob_size > 0) {
674 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
675 target_read_buffer(target, addr, len, oob);
676 addr = align_address_v2(nand, addr + len);
683 #ifdef _MXC_PRINT_STAT
685 /* When Operation Status is read (when page is erased),
686 * this function is used but data_size is null.
688 LOG_INFO("%d bytes newly read", data_size);
694 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr)
696 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
698 if (addr > MXC_NF_V2_SPARE_BUFFER0 &&
699 (addr & 0x1F) == MXC_NF_SPARE_BUFFER_LEN)
700 ret += MXC_NF_SPARE_BUFFER_MAX - MXC_NF_SPARE_BUFFER_LEN;
701 else if (addr >= (mxc_nf_info->mxc_base_addr + (uint32_t)nand->page_size))
702 ret = MXC_NF_V2_SPARE_BUFFER0;
706 static int initialize_nf_controller(struct nand_device *nand)
708 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
709 struct target *target = nand->target;
710 uint16_t work_mode = 0;
713 * resets NAND flash controller in zero time ? I don't know.
715 target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
716 if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
717 work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
719 if (target->endianness == TARGET_BIG_ENDIAN) {
720 LOG_DEBUG("MXC_NF : work in Big Endian mode");
721 work_mode |= MXC_NF_BIT_BE_EN;
723 LOG_DEBUG("MXC_NF : work in Little Endian mode");
724 if (mxc_nf_info->flags.hw_ecc_enabled) {
725 LOG_DEBUG("MXC_NF : work with ECC mode");
726 work_mode |= MXC_NF_BIT_ECC_EN;
728 LOG_DEBUG("MXC_NF : work without ECC mode");
730 target_write_u16(target, MXC_NF_V2_SPAS, OOB_SIZE / 2);
731 if (nand->page_size) {
732 uint16_t pages_per_block = nand->erase_size / nand->page_size;
733 work_mode |= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block) - 6);
735 work_mode |= MXC_NF_BIT_ECC_4BIT;
737 target_write_u16(target, MXC_NF_CFG1, work_mode);
740 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
742 target_write_u16(target, MXC_NF_BUFCFG, 2);
743 target_read_u16(target, MXC_NF_FWP, &temp);
744 if ((temp & 0x0007) == 1) {
745 LOG_ERROR("NAND flash is tight-locked, reset needed");
750 * unlock NAND flash for write
753 target_write_u16(target, MXC_NF_V1_UNLOCKSTART, 0x0000);
754 target_write_u16(target, MXC_NF_V1_UNLOCKEND, 0xFFFF);
756 target_write_u16(target, MXC_NF_V2_UNLOCKSTART0, 0x0000);
757 target_write_u16(target, MXC_NF_V2_UNLOCKSTART1, 0x0000);
758 target_write_u16(target, MXC_NF_V2_UNLOCKSTART2, 0x0000);
759 target_write_u16(target, MXC_NF_V2_UNLOCKSTART3, 0x0000);
760 target_write_u16(target, MXC_NF_V2_UNLOCKEND0, 0xFFFF);
761 target_write_u16(target, MXC_NF_V2_UNLOCKEND1, 0xFFFF);
762 target_write_u16(target, MXC_NF_V2_UNLOCKEND2, 0xFFFF);
763 target_write_u16(target, MXC_NF_V2_UNLOCKEND3, 0xFFFF);
765 target_write_u16(target, MXC_NF_FWP, 4);
768 * 0x0000 means that first SRAM buffer @base_addr will be used
770 target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
772 * address of SRAM buffer
774 in_sram_address = MXC_NF_MAIN_BUFFER0;
775 sign_of_sequental_byte_read = 0;
779 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
781 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
782 struct target *target = nand->target;
783 static uint8_t even_byte;
788 if (sign_of_sequental_byte_read == 0)
791 if (in_sram_address > (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
792 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
794 sign_of_sequental_byte_read = 0;
796 return ERROR_NAND_OPERATION_FAILED;
799 in_sram_address = align_address_v2(nand, in_sram_address);
801 target_read_u16(target, in_sram_address, &temp);
805 in_sram_address += 2;
807 *value = temp & 0xff;
811 sign_of_sequental_byte_read = 1;
815 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
817 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
818 struct target *target = nand->target;
820 if (in_sram_address > (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
821 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
823 return ERROR_NAND_OPERATION_FAILED;
826 in_sram_address = align_address_v2(nand, in_sram_address);
828 target_read_u16(target, in_sram_address, value);
829 in_sram_address += 2;
834 static int poll_for_complete_op(struct nand_device *nand, const char *text)
836 if (mxc_nand_ready(nand, 1000) == -1) {
837 LOG_ERROR("%s sending timeout", text);
838 return ERROR_NAND_OPERATION_FAILED;
843 static int validate_target_state(struct nand_device *nand)
845 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
846 struct target *target = nand->target;
848 if (target->state != TARGET_HALTED) {
849 LOG_ERROR(target_not_halted_err_msg);
850 return ERROR_NAND_OPERATION_FAILED;
853 if (mxc_nf_info->flags.target_little_endian !=
854 (target->endianness == TARGET_LITTLE_ENDIAN)) {
856 * endianness changed after NAND controller probed
858 return ERROR_NAND_OPERATION_FAILED;
863 static int ecc_status_v1(struct nand_device *nand)
865 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
866 struct target *target = nand->target;
869 target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
870 switch (ecc_status & 0x000c) {
872 LOG_INFO("main area read with 1 (correctable) error");
875 LOG_INFO("main area read with more than 1 (incorrectable) error");
876 return ERROR_NAND_OPERATION_FAILED;
878 switch (ecc_status & 0x0003) {
880 LOG_INFO("spare area read with 1 (correctable) error");
883 LOG_INFO("main area read with more than 1 (incorrectable) error");
884 return ERROR_NAND_OPERATION_FAILED;
889 static int ecc_status_v2(struct nand_device *nand)
891 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
892 struct target *target = nand->target;
897 no_subpages = nand->page_size >> 9;
899 target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
901 err = ecc_status & 0xF;
903 LOG_INFO("UnCorrectable RS-ECC Error");
904 return ERROR_NAND_OPERATION_FAILED;
906 LOG_INFO("%d Symbol Correctable RS-ECC Error", err);
908 } while (--no_subpages);
912 static int do_data_output(struct nand_device *nand)
914 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
915 struct target *target = nand->target;
917 switch (mxc_nf_info->fin) {
918 case MXC_NF_FIN_DATAOUT:
920 * start data output operation (set MXC_NF_BIT_OP_DONE==0)
922 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
923 poll_result = poll_for_complete_op(nand, "data output");
924 if (poll_result != ERROR_OK)
927 mxc_nf_info->fin = MXC_NF_FIN_NONE;
931 if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE && mxc_nf_info->flags.hw_ecc_enabled) {
934 ecc_status = ecc_status_v1(nand);
936 ecc_status = ecc_status_v2(nand);
937 if (ecc_status != ERROR_OK)
941 case MXC_NF_FIN_NONE:
947 struct nand_flash_controller mxc_nand_flash_controller = {
949 .nand_device_command = &mxc_nand_device_command,
950 .commands = mxc_nand_command_handler,
953 .command = &mxc_command,
954 .address = &mxc_address,
955 .write_data = &mxc_write_data,
956 .read_data = &mxc_read_data,
957 .write_page = &mxc_write_page,
958 .read_page = &mxc_read_page,
959 .nand_ready = &mxc_nand_ready,