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   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Alexei Babich                                   *
   3  *   Rezonans plc., Chelyabinsk, Russia                                    *
   4  *   impatt@mail.ru                                                        *
   5  *                                                                         *
   6  *   Copyright (C) 2010 by Gaetan CARLIER                                  *
   7  *   Trump s.a., Belgium                                                   *
   8  *                                                                         *
   9  *   Copyright (C) 2011 by Erik Ahlen                                      *
  10  *   Avalon Innovation, Sweden                                             *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program; if not, write to the                         *
  24  *   Free Software Foundation, Inc.,                                       *
  25  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  26  ***************************************************************************/
  27
  28 /*
  29  * Freescale iMX OpenOCD NAND Flash controller support.
  30  * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
  31  */
  32
  33 /*
  34  * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
  35  * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
  36  * "nand write # file 0", "nand verify"
  37  *
  38  * get_next_halfword_from_sram_buffer() not tested
  39  * !! all function only tested with 2k page nand device; mxc_write_page
  40  *    writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
  41  * !! oob must be be used due to NFS bug
  42  * !! oob must be 64 bytes per 2KiB page
  43 */
  44 #ifdef HAVE_CONFIG_H
  45 #include "config.h"
  46 #endif
  47
  48 #include "imp.h"
  49 #include "mxc.h"
  50 #include <target/target.h>
  51
  52 #define OOB_SIZE        64
  53
  54 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
  55                                         mxc_nf_info->mxc_version == MXC_VERSION_MX31)
  56 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
  57                                         mxc_nf_info->mxc_version == MXC_VERSION_MX35)
  58
  59 /* This permits to print (in LOG_INFO) how much bytes
  60  * has been written after a page read or write.
  61  * This is useful when OpenOCD is used with a graphical
  62  * front-end to estimate progression of the global read/write
  63  */
  64 #undef _MXC_PRINT_STAT
  65 /* #define _MXC_PRINT_STAT */
  66
  67 static const char target_not_halted_err_msg[] =
  68         "target must be halted to use mxc NAND flash controller";
  69 static const char data_block_size_err_msg[] =
  70         "minimal granularity is one half-word, %" PRId32 " is incorrect";
  71 static const char sram_buffer_bounds_err_msg[] =
  72         "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  73 static const char get_status_register_err_msg[] = "can't get NAND status";
  74 static uint32_t in_sram_address;
  75 static unsigned char sign_of_sequental_byte_read;
  76
  77 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr);
  78 static int initialize_nf_controller(struct nand_device *nand);
  79 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
  80 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
  81 static int poll_for_complete_op(struct nand_device *nand, const char *text);
  82 static int validate_target_state(struct nand_device *nand);
  83 static int do_data_output(struct nand_device *nand);
  84
  85 static int mxc_command(struct nand_device *nand, uint8_t command);
  86 static int mxc_address(struct nand_device *nand, uint8_t address);
  87
  88 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
  89 {
  90         struct mxc_nf_controller *mxc_nf_info;
  91         int hwecc_needed;
  92         int x;
  93
  94         mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
  95         if (mxc_nf_info == NULL) {
  96                 LOG_ERROR("no memory for nand controller");
  97                 return ERROR_FAIL;
  98         }
  99         nand->controller_priv = mxc_nf_info;
 100
 101         if (CMD_ARGC < 4) {
 102                 LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]\"");
 103                 return ERROR_FAIL;
 104         }
 105
 106         /*
 107          * check board type
 108          */
 109         if (strcmp(CMD_ARGV[2], "mx25") == 0) {
 110                 mxc_nf_info->mxc_version = MXC_VERSION_MX25;
 111                 mxc_nf_info->mxc_base_addr = 0xBB000000;
 112                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
 113         } else if (strcmp(CMD_ARGV[2], "mx27") == 0) {
 114                 mxc_nf_info->mxc_version = MXC_VERSION_MX27;
 115                 mxc_nf_info->mxc_base_addr = 0xD8000000;
 116                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
 117         } else if (strcmp(CMD_ARGV[2], "mx31") == 0) {
 118                 mxc_nf_info->mxc_version = MXC_VERSION_MX31;
 119                 mxc_nf_info->mxc_base_addr = 0xB8000000;
 120                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
 121         } else if (strcmp(CMD_ARGV[2], "mx35") == 0) {
 122                 mxc_nf_info->mxc_version = MXC_VERSION_MX35;
 123                 mxc_nf_info->mxc_base_addr = 0xBB000000;
 124                 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
 125         }
 126
 127         /*
 128          * check hwecc requirements
 129          */
 130         hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
 131         if (hwecc_needed == 0)
 132                 mxc_nf_info->flags.hw_ecc_enabled = 1;
 133         else
 134                 mxc_nf_info->flags.hw_ecc_enabled = 0;
 135
 136         mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 137         mxc_nf_info->fin = MXC_NF_FIN_NONE;
 138         mxc_nf_info->flags.target_little_endian =
 139         (nand->target->endianness == TARGET_LITTLE_ENDIAN);
 140
 141         /*
 142          * should factory bad block indicator be swaped
 143          * as a workaround for how the nfc handles pages.
 144          */
 145         if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
 146                 LOG_DEBUG("BI-swap enabled");
 147                 mxc_nf_info->flags.biswap_enabled = 1;
 148         }
 149
 150         /*
 151          * testing host endianness
 152          */
 153         x = 1;
 154         if (*(char *) &x == 1)
 155                 mxc_nf_info->flags.host_little_endian = 1;
 156         else
 157                 mxc_nf_info->flags.host_little_endian = 0;
 158         return ERROR_OK;
 159 }
 160
 161 COMMAND_HANDLER(handle_mxc_biswap_command)
 162 {
 163         struct nand_device *nand = NULL;
 164         struct mxc_nf_controller *mxc_nf_info = NULL;
 165
 166         if (CMD_ARGC < 1 || CMD_ARGC > 2)
 167                 return ERROR_COMMAND_SYNTAX_ERROR;
 168
 169         int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
 170         if (retval != ERROR_OK) {
 171                 command_print(CMD_CTX, "invalid nand device number or name: %s", CMD_ARGV[0]);
 172                 return ERROR_COMMAND_ARGUMENT_INVALID;
 173         }
 174
 175         mxc_nf_info = nand->controller_priv;
 176         if (CMD_ARGC == 2) {
 177                 if (strcmp(CMD_ARGV[1], "enable") == 0)
 178                         mxc_nf_info->flags.biswap_enabled = true;
 179                 else
 180                         mxc_nf_info->flags.biswap_enabled = false;
 181         }
 182         if (mxc_nf_info->flags.biswap_enabled)
 183                 command_print(CMD_CTX, "BI-swapping enabled on %s", nand->name);
 184         else
 185                 command_print(CMD_CTX, "BI-swapping disabled on %s", nand->name);
 186
 187         return ERROR_OK;
 188 }
 189
 190 static const struct command_registration mxc_sub_command_handlers[] = {
 191         {
 192                 .name = "biswap",
 193                 .handler = handle_mxc_biswap_command ,
 194                 .help = "Turns on/off bad block information swaping from main area, "
 195                                 "without parameter query status.",
 196                 .usage = "bank_id ['enable'|'disable']",
 197         },
 198         COMMAND_REGISTRATION_DONE
 199 };
 200
 201 static const struct command_registration mxc_nand_command_handler[] = {
 202         {
 203                 .name = "mxc",
 204                 .mode = COMMAND_ANY,
 205                 .help = "MXC NAND flash controller commands",
 206                 .chain = mxc_sub_command_handlers
 207         },
 208         COMMAND_REGISTRATION_DONE
 209 };
 210
 211 static int mxc_init(struct nand_device *nand)
 212 {
 213         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 214         struct target *target = nand->target;
 215
 216         int validate_target_result;
 217         uint16_t buffsize_register_content;
 218         uint32_t sreg_content;
 219         uint32_t SREG = MX2_FMCR;
 220         uint32_t SEL_16BIT = MX2_FMCR_NF_16BIT_SEL;
 221         uint32_t SEL_FMS = MX2_FMCR_NF_FMS;
 222         int retval;
 223         uint16_t nand_status_content;
 224         /*
 225          * validate target state
 226          */
 227         validate_target_result = validate_target_state(nand);
 228         if (validate_target_result != ERROR_OK)
 229                 return validate_target_result;
 230
 231         if (nfc_is_v1()) {
 232                 target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
 233                 mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
 234         } else
 235                 mxc_nf_info->flags.one_kb_sram = 0;
 236
 237         if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
 238                 SREG = MX3_PCSR;
 239                 SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
 240                 SEL_FMS = MX3_PCSR_NF_FMS;
 241         } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
 242                 SREG = MX25_RCSR;
 243                 SEL_16BIT = MX25_RCSR_NF_16BIT_SEL;
 244                 SEL_FMS = MX25_RCSR_NF_FMS;
 245         } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
 246                 SREG = MX35_RCSR;
 247                 SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
 248                 SEL_FMS = MX35_RCSR_NF_FMS;
 249         }
 250
 251         target_read_u32(target, SREG, &sreg_content);
 252         if (!nand->bus_width) {
 253                 /* bus_width not yet defined. Read it from MXC_FMCR */
 254                 nand->bus_width = (sreg_content & SEL_16BIT) ? 16 : 8;
 255         } else {
 256                 /* bus_width forced in soft. Sync it to MXC_FMCR */
 257                 sreg_content |= ((nand->bus_width == 16) ? SEL_16BIT : 0x00000000);
 258                 target_write_u32(target, SREG, sreg_content);
 259         }
 260         if (nand->bus_width == 16)
 261                 LOG_DEBUG("MXC_NF : bus is 16-bit width");
 262         else
 263                 LOG_DEBUG("MXC_NF : bus is 8-bit width");
 264
 265         if (!nand->page_size) {
 266                 nand->page_size = (sreg_content & SEL_FMS) ? 2048 : 512;
 267         } else {
 268                 sreg_content |= ((nand->page_size == 2048) ? SEL_FMS : 0x00000000);
 269                 target_write_u32(target, SREG, sreg_content);
 270         }
 271         if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
 272                 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
 273                           "pagesize 2048 is incompatible with it");
 274         } else {
 275                 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
 276         }
 277
 278         if (nfc_is_v2() && sreg_content & MX35_RCSR_NF_4K)
 279                 LOG_ERROR("MXC driver does not have support for 4k pagesize.");
 280
 281         initialize_nf_controller(nand);
 282
 283         retval = ERROR_OK;
 284         retval |= mxc_command(nand, NAND_CMD_STATUS);
 285         retval |= mxc_address(nand, 0x00);
 286         retval |= do_data_output(nand);
 287         if (retval != ERROR_OK) {
 288                 LOG_ERROR(get_status_register_err_msg);
 289                 return ERROR_FAIL;
 290         }
 291         target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
 292         if (!(nand_status_content & 0x0080)) {
 293                 LOG_INFO("NAND read-only");
 294                 mxc_nf_info->flags.nand_readonly = 1;
 295         } else {
 296                 mxc_nf_info->flags.nand_readonly = 0;
 297         }
 298         return ERROR_OK;
 299 }
 300
 301 static int mxc_read_data(struct nand_device *nand, void *data)
 302 {
 303         int validate_target_result;
 304         int try_data_output_from_nand_chip;
 305         /*
 306          * validate target state
 307          */
 308         validate_target_result = validate_target_state(nand);
 309         if (validate_target_result != ERROR_OK)
 310                 return validate_target_result;
 311
 312         /*
 313          * get data from nand chip
 314          */
 315         try_data_output_from_nand_chip = do_data_output(nand);
 316         if (try_data_output_from_nand_chip != ERROR_OK) {
 317                 LOG_ERROR("mxc_read_data : read data failed : '%x'",
 318                                   try_data_output_from_nand_chip);
 319                 return try_data_output_from_nand_chip;
 320         }
 321
 322         if (nand->bus_width == 16)
 323                 get_next_halfword_from_sram_buffer(nand, data);
 324         else
 325                 get_next_byte_from_sram_buffer(nand, data);
 326
 327         return ERROR_OK;
 328 }
 329
 330 static int mxc_write_data(struct nand_device *nand, uint16_t data)
 331 {
 332         LOG_ERROR("write_data() not implemented");
 333         return ERROR_NAND_OPERATION_FAILED;
 334 }
 335
 336 static int mxc_reset(struct nand_device *nand)
 337 {
 338         /*
 339          * validate target state
 340          */
 341         int validate_target_result;
 342         validate_target_result = validate_target_state(nand);
 343         if (validate_target_result != ERROR_OK)
 344                 return validate_target_result;
 345         initialize_nf_controller(nand);
 346         return ERROR_OK;
 347 }
 348
 349 static int mxc_command(struct nand_device *nand, uint8_t command)
 350 {
 351         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 352         struct target *target = nand->target;
 353         int validate_target_result;
 354         int poll_result;
 355         /*
 356          * validate target state
 357          */
 358         validate_target_result = validate_target_state(nand);
 359         if (validate_target_result != ERROR_OK)
 360                 return validate_target_result;
 361
 362         switch (command) {
 363         case NAND_CMD_READOOB:
 364                 command = NAND_CMD_READ0;
 365                 /* set read point for data_read() and read_block_data() to
 366                  * spare area in SRAM buffer
 367                  */
 368                 if (nfc_is_v1())
 369                         in_sram_address = MXC_NF_V1_SPARE_BUFFER0;
 370                 else
 371                         in_sram_address = MXC_NF_V2_SPARE_BUFFER0;
 372                 break;
 373         case NAND_CMD_READ1:
 374                 command = NAND_CMD_READ0;
 375                 /*
 376                  * offset == one half of page size
 377                  */
 378                 in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
 379                 break;
 380         default:
 381                 in_sram_address = MXC_NF_MAIN_BUFFER0;
 382                 break;
 383         }
 384
 385         target_write_u16(target, MXC_NF_FCMD, command);
 386         /*
 387          * start command input operation (set MXC_NF_BIT_OP_DONE==0)
 388          */
 389         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
 390         poll_result = poll_for_complete_op(nand, "command");
 391         if (poll_result != ERROR_OK)
 392                 return poll_result;
 393         /*
 394          * reset cursor to begin of the buffer
 395          */
 396         sign_of_sequental_byte_read = 0;
 397         /* Handle special read command and adjust NF_CFG2(FDO) */
 398         switch (command) {
 399         case NAND_CMD_READID:
 400                 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
 401                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 402                 break;
 403         case NAND_CMD_STATUS:
 404                 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
 405                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 406                 target_write_u16 (target, MXC_NF_BUFADDR, 0);
 407                 in_sram_address = 0;
 408                 break;
 409         case NAND_CMD_READ0:
 410                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 411                 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 412                 break;
 413         default:
 414                 /* Ohter command use the default 'One page data out' FDO */
 415                 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 416                 break;
 417         }
 418         return ERROR_OK;
 419 }
 420
 421 static int mxc_address(struct nand_device *nand, uint8_t address)
 422 {
 423         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 424         struct target *target = nand->target;
 425         int validate_target_result;
 426         int poll_result;
 427         /*
 428          * validate target state
 429          */
 430         validate_target_result = validate_target_state(nand);
 431         if (validate_target_result != ERROR_OK)
 432                 return validate_target_result;
 433
 434         target_write_u16(target, MXC_NF_FADDR, address);
 435         /*
 436          * start address input operation (set MXC_NF_BIT_OP_DONE==0)
 437          */
 438         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
 439         poll_result = poll_for_complete_op(nand, "address");
 440         if (poll_result != ERROR_OK)
 441                 return poll_result;
 442
 443         return ERROR_OK;
 444 }
 445
 446 static int mxc_nand_ready(struct nand_device *nand, int tout)
 447 {
 448         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 449         struct target *target = nand->target;
 450         uint16_t poll_complete_status;
 451         int validate_target_result;
 452
 453         /*
 454          * validate target state
 455          */
 456         validate_target_result = validate_target_state(nand);
 457         if (validate_target_result != ERROR_OK)
 458                 return validate_target_result;
 459
 460         do {
 461                 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
 462                 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
 463                         return tout;
 464
 465                 alive_sleep(1);
 466         }
 467         while (tout-- > 0);
 468         return tout;
 469 }
 470
 471 static int mxc_write_page(struct nand_device *nand, uint32_t page,
 472                                                         uint8_t *data, uint32_t data_size,
 473                                                         uint8_t *oob, uint32_t oob_size)
 474 {
 475         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 476         struct target *target = nand->target;
 477         int retval;
 478         uint16_t nand_status_content;
 479         uint16_t swap1, swap2, new_swap1;
 480         uint8_t bufs;
 481         int poll_result;
 482
 483         if (data_size % 2) {
 484                 LOG_ERROR(data_block_size_err_msg, data_size);
 485                 return ERROR_NAND_OPERATION_FAILED;
 486         }
 487         if (oob_size % 2) {
 488                 LOG_ERROR(data_block_size_err_msg, oob_size);
 489                 return ERROR_NAND_OPERATION_FAILED;
 490         }
 491         if (!data) {
 492                 LOG_ERROR("nothing to program");
 493                 return ERROR_NAND_OPERATION_FAILED;
 494         }
 495
 496         /*
 497          * validate target state
 498          */
 499         retval = validate_target_state(nand);
 500         if (retval != ERROR_OK)
 501                 return retval;
 502
 503         in_sram_address = MXC_NF_MAIN_BUFFER0;
 504         sign_of_sequental_byte_read = 0;
 505         retval = ERROR_OK;
 506         retval |= mxc_command(nand, NAND_CMD_SEQIN);
 507         retval |= mxc_address(nand, 0); /* col */
 508         retval |= mxc_address(nand, 0); /* col */
 509         retval |= mxc_address(nand, page & 0xff); /* page address */
 510         retval |= mxc_address(nand, (page >> 8) & 0xff); /* page address */
 511         retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
 512
 513         target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
 514         if (oob) {
 515                 if (mxc_nf_info->flags.hw_ecc_enabled) {
 516                         /*
 517                          * part of spare block will be overrided by hardware
 518                          * ECC generator
 519                          */
 520                         LOG_DEBUG("part of spare block will be overrided "
 521                                   "by hardware ECC generator");
 522                 }
 523                 if (nfc_is_v1())
 524                         target_write_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
 525                 else {
 526                         uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
 527                         while (oob_size > 0) {
 528                                 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
 529                                 target_write_buffer(target, addr, len, oob);
 530                                 addr = align_address_v2(nand, addr + len);
 531                                 oob += len;
 532                                 oob_size -= len;
 533                         }
 534                 }
 535         }
 536
 537         if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
 538                 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
 539                 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
 540                 if (oob) {
 541                         LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
 542                         return ERROR_NAND_OPERATION_FAILED;
 543                 }
 544                 swap2 = 0xffff;  /* Spare buffer unused forced to 0xffff */
 545                 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 546                 swap2 = (swap1 << 8) | (swap2 & 0xFF);
 547                 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
 548                 if (nfc_is_v1())
 549                         target_write_u16(target, MXC_NF_V1_SPARE_BUFFER3, swap2);
 550                 else
 551                         target_write_u16(target, MXC_NF_V2_SPARE_BUFFER3, swap2);
 552         }
 553
 554         /*
 555          * start data input operation (set MXC_NF_BIT_OP_DONE==0)
 556          */
 557         if (nfc_is_v1() && nand->page_size > 512)
 558                 bufs = 4;
 559         else
 560                 bufs = 1;
 561
 562         for (uint8_t i = 0 ; i < bufs ; ++i) {
 563                 target_write_u16(target, MXC_NF_BUFADDR, i);
 564                 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
 565                 poll_result = poll_for_complete_op(nand, "data input");
 566                 if (poll_result != ERROR_OK)
 567                         return poll_result;
 568         }
 569
 570         retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
 571         if (retval != ERROR_OK)
 572                 return retval;
 573
 574         /*
 575          * check status register
 576          */
 577         retval = ERROR_OK;
 578         retval |= mxc_command(nand, NAND_CMD_STATUS);
 579         target_write_u16 (target, MXC_NF_BUFADDR, 0);
 580         mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
 581         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 582         retval |= do_data_output(nand);
 583         if (retval != ERROR_OK) {
 584                 LOG_ERROR(get_status_register_err_msg);
 585                 return retval;
 586         }
 587         target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
 588         if (nand_status_content & 0x0001) {
 589                 /*
 590                  * page not correctly written
 591                  */
 592                 return ERROR_NAND_OPERATION_FAILED;
 593         }
 594 #ifdef _MXC_PRINT_STAT
 595         LOG_INFO("%d bytes newly written", data_size);
 596 #endif
 597         return ERROR_OK;
 598 }
 599
 600 static int mxc_read_page(struct nand_device *nand, uint32_t page,
 601                                                    uint8_t *data, uint32_t data_size,
 602                                                    uint8_t *oob, uint32_t oob_size)
 603 {
 604         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 605         struct target *target = nand->target;
 606         int retval;
 607         uint8_t bufs;
 608         uint16_t swap1, swap2, new_swap1;
 609
 610         if (data_size % 2) {
 611                 LOG_ERROR(data_block_size_err_msg, data_size);
 612                 return ERROR_NAND_OPERATION_FAILED;
 613         }
 614         if (oob_size % 2) {
 615                 LOG_ERROR(data_block_size_err_msg, oob_size);
 616                 return ERROR_NAND_OPERATION_FAILED;
 617         }
 618
 619         /*
 620          * validate target state
 621          */
 622         retval = validate_target_state(nand);
 623         if (retval != ERROR_OK) {
 624                 return retval;
 625         }
 626         /* Reset address_cycles before mxc_command ?? */
 627         retval = mxc_command(nand, NAND_CMD_READ0);
 628         if (retval != ERROR_OK) return retval;
 629         retval = mxc_address(nand, 0); /* col */
 630         if (retval != ERROR_OK) return retval;
 631         retval = mxc_address(nand, 0); /* col */
 632         if (retval != ERROR_OK) return retval;
 633         retval = mxc_address(nand, page & 0xff); /* page address */
 634         if (retval != ERROR_OK) return retval;
 635         retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
 636         if (retval != ERROR_OK) return retval;
 637         retval = mxc_address(nand, (page >> 16) & 0xff); /* page address */
 638         if (retval != ERROR_OK) return retval;
 639         retval = mxc_command(nand, NAND_CMD_READSTART);
 640         if (retval != ERROR_OK) return retval;
 641
 642         if (nfc_is_v1() && nand->page_size > 512)
 643                 bufs = 4;
 644         else
 645                 bufs = 1;
 646
 647         for (uint8_t i = 0 ; i < bufs ; ++i) {
 648                 target_write_u16(target, MXC_NF_BUFADDR, i);
 649                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 650                 retval = do_data_output(nand);
 651                 if (retval != ERROR_OK) {
 652                         LOG_ERROR("MXC_NF : Error reading page %d", i);
 653                         return retval;
 654                 }
 655         }
 656
 657         if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
 658                 uint32_t SPARE_BUFFER3;
 659                 /* BI-swap -  work-around of mxc NFC for NAND device with page == 2k */
 660                 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
 661                 if (nfc_is_v1())
 662                         SPARE_BUFFER3 = MXC_NF_V1_SPARE_BUFFER3;
 663                 else
 664                         SPARE_BUFFER3 = MXC_NF_V2_SPARE_BUFFER3;
 665                 target_read_u16(target, SPARE_BUFFER3, &swap2);
 666                 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 667                 swap2 = (swap1 << 8) | (swap2 & 0xFF);
 668                 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
 669                 target_write_u16(target, SPARE_BUFFER3, swap2);
 670         }
 671
 672         if (data)
 673                 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
 674         if (oob) {
 675                 if (nfc_is_v1())
 676                         target_read_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
 677                 else {
 678                         uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
 679                         while (oob_size > 0) {
 680                                 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
 681                                 target_read_buffer(target, addr, len, oob);
 682                                 addr = align_address_v2(nand, addr + len);
 683                                 oob += len;
 684                                 oob_size -= len;
 685                         }
 686                 }
 687         }
 688
 689 #ifdef _MXC_PRINT_STAT
 690         if (data_size > 0) {
 691                 /* When Operation Status is read (when page is erased),
 692                  * this function is used but data_size is null.
 693                  */
 694                 LOG_INFO("%d bytes newly read", data_size);
 695         }
 696 #endif
 697         return ERROR_OK;
 698 }
 699
 700 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr)
 701 {
 702         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 703         uint32_t ret = addr;
 704         if (addr > MXC_NF_V2_SPARE_BUFFER0 &&
 705            (addr & 0x1F) == MXC_NF_SPARE_BUFFER_LEN) {
 706                 ret += MXC_NF_SPARE_BUFFER_MAX - MXC_NF_SPARE_BUFFER_LEN;
 707         } else if (addr >= (mxc_nf_info->mxc_base_addr + (uint32_t)nand->page_size))
 708                 ret = MXC_NF_V2_SPARE_BUFFER0;
 709         return ret;
 710 }
 711
 712 static int initialize_nf_controller(struct nand_device *nand)
 713 {
 714         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 715         struct target *target = nand->target;
 716         uint16_t work_mode = 0;
 717         uint16_t temp;
 718         /*
 719          * resets NAND flash controller in zero time ? I dont know.
 720          */
 721         target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
 722         if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
 723                 work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
 724
 725         if (target->endianness == TARGET_BIG_ENDIAN) {
 726                 LOG_DEBUG("MXC_NF : work in Big Endian mode");
 727                 work_mode |= MXC_NF_BIT_BE_EN;
 728         } else {
 729                 LOG_DEBUG("MXC_NF : work in Little Endian mode");
 730         }
 731         if (mxc_nf_info->flags.hw_ecc_enabled) {
 732                 LOG_DEBUG("MXC_NF : work with ECC mode");
 733                 work_mode |= MXC_NF_BIT_ECC_EN;
 734         } else {
 735                 LOG_DEBUG("MXC_NF : work without ECC mode");
 736         }
 737         if (nfc_is_v2()) {
 738                 target_write_u16(target, MXC_NF_V2_SPAS, OOB_SIZE / 2);
 739                 if (nand->page_size) {
 740                         uint16_t pages_per_block = nand->erase_size / nand->page_size;
 741                         work_mode |= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block) - 6);
 742                 }
 743                 work_mode |= MXC_NF_BIT_ECC_4BIT;
 744         }
 745         target_write_u16(target, MXC_NF_CFG1, work_mode);
 746
 747         /*
 748          * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
 749          */
 750         target_write_u16(target, MXC_NF_BUFCFG, 2);
 751         target_read_u16(target, MXC_NF_FWP, &temp);
 752         if ((temp & 0x0007) == 1) {
 753                 LOG_ERROR("NAND flash is tight-locked, reset needed");
 754                 return ERROR_FAIL;
 755         }
 756
 757         /*
 758          * unlock NAND flash for write
 759          */
 760         if (nfc_is_v1()) {
 761                 target_write_u16(target, MXC_NF_V1_UNLOCKSTART, 0x0000);
 762                 target_write_u16(target, MXC_NF_V1_UNLOCKEND, 0xFFFF);
 763         } else {
 764                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART0, 0x0000);
 765                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART1, 0x0000);
 766                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART2, 0x0000);
 767                 target_write_u16(target, MXC_NF_V2_UNLOCKSTART3, 0x0000);
 768                 target_write_u16(target, MXC_NF_V2_UNLOCKEND0, 0xFFFF);
 769                 target_write_u16(target, MXC_NF_V2_UNLOCKEND1, 0xFFFF);
 770                 target_write_u16(target, MXC_NF_V2_UNLOCKEND2, 0xFFFF);
 771                 target_write_u16(target, MXC_NF_V2_UNLOCKEND3, 0xFFFF);
 772         }
 773         target_write_u16(target, MXC_NF_FWP, 4);
 774
 775         /*
 776          * 0x0000 means that first SRAM buffer @base_addr will be used
 777          */
 778         target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
 779         /*
 780          * address of SRAM buffer
 781          */
 782         in_sram_address = MXC_NF_MAIN_BUFFER0;
 783         sign_of_sequental_byte_read = 0;
 784         return ERROR_OK;
 785 }
 786
 787 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
 788 {
 789         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 790         struct target *target = nand->target;
 791         static uint8_t even_byte = 0;
 792         uint16_t temp;
 793         /*
 794          * host-big_endian ??
 795          */
 796         if (sign_of_sequental_byte_read == 0)
 797                 even_byte = 0;
 798
 799         if (in_sram_address >
 800                 (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
 801                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 802                 *value = 0;
 803                 sign_of_sequental_byte_read = 0;
 804                 even_byte = 0;
 805                 return ERROR_NAND_OPERATION_FAILED;
 806         } else {
 807                 if (nfc_is_v2())
 808                         in_sram_address = align_address_v2(nand, in_sram_address);
 809
 810                 target_read_u16(target, in_sram_address, &temp);
 811                 if (even_byte) {
 812                         *value = temp >> 8;
 813                         even_byte = 0;
 814                         in_sram_address += 2;
 815                 } else {
 816                         *value = temp & 0xff;
 817                         even_byte = 1;
 818                 }
 819         }
 820         sign_of_sequental_byte_read = 1;
 821         return ERROR_OK;
 822 }
 823
 824 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
 825 {
 826         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 827         struct target *target = nand->target;
 828
 829         if (in_sram_address >
 830                 (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
 831                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 832                 *value = 0;
 833                 return ERROR_NAND_OPERATION_FAILED;
 834         } else {
 835                 if (nfc_is_v2())
 836                         in_sram_address = align_address_v2(nand, in_sram_address);
 837
 838                 target_read_u16(target, in_sram_address, value);
 839                 in_sram_address += 2;
 840         }
 841         return ERROR_OK;
 842 }
 843
 844 static int poll_for_complete_op(struct nand_device *nand, const char *text)
 845 {
 846         if (mxc_nand_ready(nand, 1000) == -1) {
 847                 LOG_ERROR("%s sending timeout", text);
 848                 return ERROR_NAND_OPERATION_FAILED;
 849         }
 850         return ERROR_OK;
 851 }
 852
 853 static int validate_target_state(struct nand_device *nand)
 854 {
 855         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 856         struct target *target = nand->target;
 857
 858         if (target->state != TARGET_HALTED) {
 859                 LOG_ERROR(target_not_halted_err_msg);
 860                 return ERROR_NAND_OPERATION_FAILED;
 861         }
 862
 863         if (mxc_nf_info->flags.target_little_endian !=
 864             (target->endianness == TARGET_LITTLE_ENDIAN)) {
 865                 /*
 866                  * endianness changed after NAND controller probed
 867                  */
 868                 return ERROR_NAND_OPERATION_FAILED;
 869         }
 870         return ERROR_OK;
 871 }
 872
 873 int ecc_status_v1(struct nand_device *nand)
 874 {
 875         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 876         struct target *target = nand->target;
 877         uint16_t ecc_status;
 878
 879         target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
 880         switch (ecc_status & 0x000c) {
 881         case 1 << 2:
 882                 LOG_INFO("main area read with 1 (correctable) error");
 883                 break;
 884         case 2 << 2:
 885                 LOG_INFO("main area read with more than 1 (incorrectable) error");
 886                 return ERROR_NAND_OPERATION_FAILED;
 887                 break;
 888         }
 889         switch (ecc_status & 0x0003) {
 890         case 1:
 891                 LOG_INFO("spare area read with 1 (correctable) error");
 892                 break;
 893         case 2:
 894                 LOG_INFO("main area read with more than 1 (incorrectable) error");
 895                 return ERROR_NAND_OPERATION_FAILED;
 896                 break;
 897         }
 898         return ERROR_OK;
 899 }
 900
 901 int ecc_status_v2(struct nand_device *nand)
 902 {
 903         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 904         struct target *target = nand->target;
 905         uint16_t ecc_status;
 906         uint8_t no_subpages;
 907         uint8_t err;
 908
 909         no_subpages = nand->page_size >> 9;
 910
 911         target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
 912         do {
 913                 err = ecc_status & 0xF;
 914                 if (err > 4) {
 915                         LOG_INFO("UnCorrectable RS-ECC Error");
 916                         return ERROR_NAND_OPERATION_FAILED;
 917                 } else if (err > 0)
 918                         LOG_INFO("%d Symbol Correctable RS-ECC Error", err);
 919                 ecc_status >>= 4;
 920         } while (--no_subpages);
 921         return ERROR_OK;
 922 }
 923
 924 static int do_data_output(struct nand_device *nand)
 925 {
 926         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 927         struct target *target = nand->target;
 928         int poll_result;
 929         switch (mxc_nf_info->fin) {
 930         case MXC_NF_FIN_DATAOUT:
 931                 /*
 932                  * start data output operation (set MXC_NF_BIT_OP_DONE==0)
 933                  */
 934                 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
 935                 poll_result = poll_for_complete_op(nand, "data output");
 936                 if (poll_result != ERROR_OK)
 937                         return poll_result;
 938
 939                 mxc_nf_info->fin = MXC_NF_FIN_NONE;
 940                 /*
 941                  * ECC stuff
 942                  */
 943                 if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE &&
 944                         mxc_nf_info->flags.hw_ecc_enabled) {
 945                         int ecc_status;
 946                         if (nfc_is_v1())
 947                                 ecc_status = ecc_status_v1(nand);
 948                         else
 949                                 ecc_status = ecc_status_v2(nand);
 950                         if (ecc_status != ERROR_OK)
 951                                 return ecc_status;
 952                 }
 953                 break;
 954         case MXC_NF_FIN_NONE:
 955                 break;
 956         }
 957         return ERROR_OK;
 958 }
 959
 960 struct nand_flash_controller mxc_nand_flash_controller = {
 961         .name                                   = "mxc",
 962         .nand_device_command    = &mxc_nand_device_command,
 963         .commands                               = mxc_nand_command_handler,
 964         .init                                   = &mxc_init,
 965         .reset                                  = &mxc_reset,
 966         .command                                = &mxc_command,
 967         .address                                = &mxc_address,
 968         .write_data                             = &mxc_write_data,
 969         .read_data                              = &mxc_read_data,
 970         .write_page                             = &mxc_write_page,
 971         .read_page                              = &mxc_read_page,
 972         .nand_ready                             = &mxc_nand_ready,
 973 };