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   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2011 Bjarne Steinsbo <bsteinsbo@gmail.com>              *
   6  *   Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com>                *
   7  *   Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com>            *
   8  *                                                                         *
   9  *   Based on a combination of the lpc3180 driver and code from            *
  10  *   uboot-2009.03-lpc32xx by Kevin Wells.                                 *
  11  *   Any bugs are mine. --BSt                                              *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  25  ***************************************************************************/
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "imp.h"
  32 #include "lpc32xx.h"
  33 #include <target/target.h>
  34
  35 static int lpc32xx_reset(struct nand_device *nand);
  36 static int lpc32xx_controller_ready(struct nand_device *nand, int timeout);
  37 static int lpc32xx_tc_ready(struct nand_device *nand, int timeout);
  38 extern int nand_correct_data(struct nand_device *nand, u_char *dat,
  39                 u_char *read_ecc, u_char *calc_ecc);
  40
  41 /* These are offset with the working area in IRAM when using DMA to
  42  * read/write data to the SLC controller.
  43  * - DMA descriptors will be put at start of working area,
  44  * - Hardware generated ECC will be stored at ECC_OFFS
  45  * - OOB wil be read/written from/to SPARE_OFFS
  46  * - Actual page data will be read from/to DATA_OFFS
  47  * There are unused holes between the used areas.
  48  */
  49 #define ECC_OFFS   0x120
  50 #define SPARE_OFFS 0x140
  51 #define DATA_OFFS  0x200
  52
  53 static const int sp_ooblayout[] = {
  54         10, 11, 12, 13, 14, 15
  55 };
  56 static const int lp_ooblayout[] = {
  57         40, 41, 42, 43, 44, 45,
  58         46, 47, 48, 49, 50, 51,
  59         52, 53, 54, 55, 56, 57,
  60         58, 59, 60, 61, 62, 63
  61 };
  62
  63 typedef struct {
  64         volatile uint32_t dma_src;
  65         volatile uint32_t dma_dest;
  66         volatile uint32_t next_lli;
  67         volatile uint32_t next_ctrl;
  68 } dmac_ll_t;
  69
  70 static dmac_ll_t dmalist[(2048/256) * 2 + 1];
  71
  72 /* nand device lpc32xx <target#> <oscillator_frequency>
  73  */
  74 NAND_DEVICE_COMMAND_HANDLER(lpc32xx_nand_device_command)
  75 {
  76         if (CMD_ARGC < 3)
  77                 return ERROR_COMMAND_SYNTAX_ERROR;
  78
  79         uint32_t osc_freq;
  80         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
  81
  82         struct lpc32xx_nand_controller *lpc32xx_info;
  83         lpc32xx_info = malloc(sizeof(struct lpc32xx_nand_controller));
  84         nand->controller_priv = lpc32xx_info;
  85
  86         lpc32xx_info->osc_freq = osc_freq;
  87
  88         if ((lpc32xx_info->osc_freq < 1000) || (lpc32xx_info->osc_freq > 20000))
  89                 LOG_WARNING("LPC32xx oscillator frequency should be between "
  90                         "1000 and 20000 kHz, was %i",
  91                         lpc32xx_info->osc_freq);
  92
  93         lpc32xx_info->selected_controller = LPC32xx_NO_CONTROLLER;
  94         lpc32xx_info->sw_write_protection = 0;
  95         lpc32xx_info->sw_wp_lower_bound = 0x0;
  96         lpc32xx_info->sw_wp_upper_bound = 0x0;
  97
  98         return ERROR_OK;
  99 }
 100
 101 static int lpc32xx_pll(int fclkin, uint32_t pll_ctrl)
 102 {
 103         int bypass = (pll_ctrl & 0x8000) >> 15;
 104         int direct = (pll_ctrl & 0x4000) >> 14;
 105         int feedback = (pll_ctrl & 0x2000) >> 13;
 106         int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
 107         int n = ((pll_ctrl & 0x0600) >> 9) + 1;
 108         int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
 109         int lock = (pll_ctrl & 0x1);
 110
 111         if (!lock)
 112                 LOG_WARNING("PLL is not locked");
 113
 114         if (!bypass && direct)  /* direct mode */
 115                 return (m * fclkin) / n;
 116
 117         if (bypass && !direct)  /* bypass mode */
 118                 return fclkin / (2 * p);
 119
 120         if (bypass & direct)    /* direct bypass mode */
 121                 return fclkin;
 122
 123         if (feedback)   /* integer mode */
 124                 return m * (fclkin / n);
 125         else    /* non-integer mode */
 126                 return (m / (2 * p)) * (fclkin / n);
 127 }
 128
 129 static float lpc32xx_cycle_time(struct nand_device *nand)
 130 {
 131         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 132         struct target *target = nand->target;
 133         uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
 134         int sysclk;
 135         int hclk;
 136         int hclk_pll;
 137         float cycle;
 138         int retval;
 139
 140         /* calculate timings */
 141
 142         /* determine current SYSCLK (13'MHz or main oscillator) */
 143         retval = target_read_u32(target, 0x40004050, &sysclk_ctrl);
 144         if (ERROR_OK != retval) {
 145                 LOG_ERROR("could not read SYSCLK_CTRL");
 146                 return ERROR_NAND_OPERATION_FAILED;
 147         }
 148
 149         if ((sysclk_ctrl & 1) == 0)
 150                 sysclk = lpc32xx_info->osc_freq;
 151         else
 152                 sysclk = 13000;
 153
 154         /* determine selected HCLK source */
 155         retval = target_read_u32(target, 0x40004044, &pwr_ctrl);
 156         if (ERROR_OK != retval) {
 157                 LOG_ERROR("could not read HCLK_CTRL");
 158                 return ERROR_NAND_OPERATION_FAILED;
 159         }
 160
 161         if ((pwr_ctrl & (1 << 2)) == 0)         /* DIRECT RUN mode */
 162                 hclk = sysclk;
 163         else {
 164                 retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
 165                 if (ERROR_OK != retval) {
 166                         LOG_ERROR("could not read HCLKPLL_CTRL");
 167                         return ERROR_NAND_OPERATION_FAILED;
 168                 }
 169                 hclk_pll = lpc32xx_pll(sysclk, hclkpll_ctrl);
 170
 171                 retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
 172                 if (ERROR_OK != retval) {
 173                         LOG_ERROR("could not read CLKDIV_CTRL");
 174                         return ERROR_NAND_OPERATION_FAILED;
 175                 }
 176
 177                 if (pwr_ctrl & (1 << 10))       /* ARM_CLK and HCLK use PERIPH_CLK */
 178                         hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
 179                 else    /* HCLK uses HCLK_PLL */
 180                         hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
 181         }
 182
 183         LOG_DEBUG("LPC32xx HCLK currently clocked at %i kHz", hclk);
 184
 185         cycle = (1.0 / hclk) * 1000000.0;
 186
 187         return cycle;
 188 }
 189
 190 static int lpc32xx_init(struct nand_device *nand)
 191 {
 192         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 193         struct target *target = nand->target;
 194         int bus_width = nand->bus_width ? : 8;
 195         int address_cycles = nand->address_cycles ? : 3;
 196         int page_size = nand->page_size ? : 512;
 197         int retval;
 198
 199         if (target->state != TARGET_HALTED) {
 200                 LOG_ERROR("target must be halted to use LPC32xx "
 201                         "NAND flash controller");
 202                 return ERROR_NAND_OPERATION_FAILED;
 203         }
 204
 205         /* sanitize arguments */
 206         if (bus_width != 8) {
 207                 LOG_ERROR("LPC32xx doesn't support %i", bus_width);
 208                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 209         }
 210
 211         /* inform calling code about selected bus width */
 212         nand->bus_width = bus_width;
 213
 214         if ((address_cycles < 3) || (address_cycles > 5)) {
 215                 LOG_ERROR("LPC32xx driver doesn't support %i address cycles", address_cycles);
 216                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 217         }
 218
 219         if ((page_size != 512) && (page_size != 2048)) {
 220                 LOG_ERROR("LPC32xx doesn't support page size %i", page_size);
 221                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 222         }
 223
 224         /* select MLC controller if none is currently selected */
 225         if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
 226                 LOG_DEBUG("no LPC32xx NAND flash controller selected, "
 227                         "using default 'slc'");
 228                 lpc32xx_info->selected_controller = LPC32xx_SLC_CONTROLLER;
 229         }
 230
 231         if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
 232                 uint32_t mlc_icr_value = 0x0;
 233                 float cycle;
 234                 int twp, twh, trp, treh, trhz, trbwb, tcea;
 235
 236                 /* FLASHCLK_CTRL = 0x22 (enable clk for MLC) */
 237                 retval = target_write_u32(target, 0x400040c8, 0x22);
 238                 if (ERROR_OK != retval) {
 239                         LOG_ERROR("could not set FLASHCLK_CTRL");
 240                         return ERROR_NAND_OPERATION_FAILED;
 241                 }
 242
 243                 /* MLC_CEH = 0x0 (Force nCE assert) */
 244                 retval = target_write_u32(target, 0x200b804c, 0x0);
 245                 if (ERROR_OK != retval) {
 246                         LOG_ERROR("could not set MLC_CEH");
 247                         return ERROR_NAND_OPERATION_FAILED;
 248                 }
 249
 250                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 251                 retval = target_write_u32(target, 0x200b8044, 0xa25e);
 252                 if (ERROR_OK != retval) {
 253                         LOG_ERROR("could not set MLC_LOCK");
 254                         return ERROR_NAND_OPERATION_FAILED;
 255                 }
 256
 257                 /* MLC_ICR = configuration */
 258                 if (lpc32xx_info->sw_write_protection)
 259                         mlc_icr_value |= 0x8;
 260                 if (page_size == 2048)
 261                         mlc_icr_value |= 0x4;
 262                 if (address_cycles == 4)
 263                         mlc_icr_value |= 0x2;
 264                 if (bus_width == 16)
 265                         mlc_icr_value |= 0x1;
 266                 retval = target_write_u32(target, 0x200b8030, mlc_icr_value);
 267                 if (ERROR_OK != retval) {
 268                         LOG_ERROR("could not set MLC_ICR");
 269                         return ERROR_NAND_OPERATION_FAILED;
 270                 }
 271
 272                 /* calculate NAND controller timings */
 273                 cycle = lpc32xx_cycle_time(nand);
 274
 275                 twp = ((40 / cycle) + 1);
 276                 twh = ((20 / cycle) + 1);
 277                 trp = ((30 / cycle) + 1);
 278                 treh = ((15 / cycle) + 1);
 279                 trhz = ((30 / cycle) + 1);
 280                 trbwb = ((100 / cycle) + 1);
 281                 tcea = ((45 / cycle) + 1);
 282
 283                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 284                 retval = target_write_u32(target, 0x200b8044, 0xa25e);
 285                 if (ERROR_OK != retval) {
 286                         LOG_ERROR("could not set MLC_LOCK");
 287                         return ERROR_NAND_OPERATION_FAILED;
 288                 }
 289
 290                 /* MLC_TIME_REG */
 291                 retval = target_write_u32(target, 0x200b8034,
 292                                 (twp & 0xf)
 293                                 | ((twh & 0xf) << 4)
 294                                 | ((trp & 0xf) << 8)
 295                                 | ((treh & 0xf) << 12)
 296                                 | ((trhz & 0x7) << 16)
 297                                 | ((trbwb & 0x1f) << 19)
 298                                 | ((tcea & 0x3) << 24));
 299                 if (ERROR_OK != retval) {
 300                         LOG_ERROR("could not set MLC_TIME_REG");
 301                         return ERROR_NAND_OPERATION_FAILED;
 302                 }
 303
 304                 retval = lpc32xx_reset(nand);
 305                 if (ERROR_OK != retval)
 306                         return ERROR_NAND_OPERATION_FAILED;
 307         } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
 308                 float cycle;
 309                 int r_setup, r_hold, r_width, r_rdy;
 310                 int w_setup, w_hold, w_width, w_rdy;
 311
 312                 /* FLASHCLK_CTRL = 0x05 (enable clk for SLC) */
 313                 retval = target_write_u32(target, 0x400040c8, 0x05);
 314                 if (ERROR_OK != retval) {
 315                         LOG_ERROR("could not set FLASHCLK_CTRL");
 316                         return ERROR_NAND_OPERATION_FAILED;
 317                 }
 318
 319                 /* after reset set other registers of SLC,
 320                  * so reset calling is here at the begining
 321                  */
 322                 retval = lpc32xx_reset(nand);
 323                 if (ERROR_OK != retval)
 324                         return ERROR_NAND_OPERATION_FAILED;
 325
 326                 /* SLC_CFG =
 327                         Force nCE assert,
 328                         DMA ECC enabled,
 329                         ECC enabled,
 330                         DMA burst enabled,
 331                         DMA read from SLC,
 332                         WIDTH = bus_width)
 333                 */
 334                 retval = target_write_u32(target, 0x20020014,
 335                                 0x3e | (bus_width == 16) ? 1 : 0);
 336                 if (ERROR_OK != retval) {
 337                         LOG_ERROR("could not set SLC_CFG");
 338                         return ERROR_NAND_OPERATION_FAILED;
 339                 }
 340
 341                 /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
 342                 retval = target_write_u32(target, 0x20020020, 0x03);
 343                 if (ERROR_OK != retval) {
 344                         LOG_ERROR("could not set SLC_IEN");
 345                         return ERROR_NAND_OPERATION_FAILED;
 346                 }
 347
 348                 /* DMA configuration */
 349
 350                 /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
 351                 retval = target_write_u32(target, 0x400040e8, 0x01);
 352                 if (ERROR_OK != retval) {
 353                         LOG_ERROR("could not set DMACLK_CTRL");
 354                         return ERROR_NAND_OPERATION_FAILED;
 355                 }
 356
 357                 /* DMACConfig = DMA enabled*/
 358                 retval = target_write_u32(target, 0x31000030, 0x01);
 359                 if (ERROR_OK != retval) {
 360                         LOG_ERROR("could not set DMACConfig");
 361                         return ERROR_NAND_OPERATION_FAILED;
 362                 }
 363
 364                 /* calculate NAND controller timings */
 365                 cycle = lpc32xx_cycle_time(nand);
 366
 367                 r_setup = w_setup = 0;
 368                 r_hold = w_hold = 10 / cycle;
 369                 r_width = 30 / cycle;
 370                 w_width = 40 / cycle;
 371                 r_rdy = w_rdy = 100 / cycle;
 372
 373                 /* SLC_TAC: SLC timing arcs register */
 374                 retval = target_write_u32(target, 0x2002002c,
 375                                 (r_setup & 0xf)
 376                                 | ((r_hold & 0xf) << 4)
 377                                 | ((r_width & 0xf) << 8)
 378                                 | ((r_rdy & 0xf) << 12)
 379                                 | ((w_setup & 0xf) << 16)
 380                                 | ((w_hold & 0xf) << 20)
 381                                 | ((w_width & 0xf) << 24)
 382                                 | ((w_rdy & 0xf) << 28));
 383                 if (ERROR_OK != retval) {
 384                         LOG_ERROR("could not set SLC_TAC");
 385                         return ERROR_NAND_OPERATION_FAILED;
 386                 }
 387         }
 388
 389         return ERROR_OK;
 390 }
 391
 392 static int lpc32xx_reset(struct nand_device *nand)
 393 {
 394         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 395         struct target *target = nand->target;
 396         int retval;
 397
 398         if (target->state != TARGET_HALTED) {
 399                 LOG_ERROR("target must be halted to use "
 400                         "LPC32xx NAND flash controller");
 401                 return ERROR_NAND_OPERATION_FAILED;
 402         }
 403
 404         if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
 405                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
 406                 return ERROR_NAND_OPERATION_FAILED;
 407         } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
 408                 /* MLC_CMD = 0xff (reset controller and NAND device) */
 409                 retval = target_write_u32(target, 0x200b8000, 0xff);
 410                 if (ERROR_OK != retval) {
 411                         LOG_ERROR("could not set MLC_CMD");
 412                         return ERROR_NAND_OPERATION_FAILED;
 413                 }
 414
 415                 if (!lpc32xx_controller_ready(nand, 100)) {
 416                         LOG_ERROR("LPC32xx MLC NAND controller timed out "
 417                                 "after reset");
 418                         return ERROR_NAND_OPERATION_TIMEOUT;
 419                 }
 420         } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
 421                 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
 422                 retval = target_write_u32(target, 0x20020010, 0x6);
 423                 if (ERROR_OK != retval) {
 424                         LOG_ERROR("could not set SLC_CTRL");
 425                         return ERROR_NAND_OPERATION_FAILED;
 426                 }
 427
 428                 if (!lpc32xx_controller_ready(nand, 100)) {
 429                         LOG_ERROR("LPC32xx SLC NAND controller timed out "
 430                                 "after reset");
 431                         return ERROR_NAND_OPERATION_TIMEOUT;
 432                 }
 433         }
 434
 435         return ERROR_OK;
 436 }
 437
 438 static int lpc32xx_command(struct nand_device *nand, uint8_t command)
 439 {
 440         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 441         struct target *target = nand->target;
 442         int retval;
 443
 444         if (target->state != TARGET_HALTED) {
 445                 LOG_ERROR("target must be halted to use "
 446                         "LPC32xx NAND flash controller");
 447                 return ERROR_NAND_OPERATION_FAILED;
 448         }
 449
 450         if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
 451                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
 452                 return ERROR_NAND_OPERATION_FAILED;
 453         } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
 454                 /* MLC_CMD = command */
 455                 retval = target_write_u32(target, 0x200b8000, command);
 456                 if (ERROR_OK != retval) {
 457                         LOG_ERROR("could not set MLC_CMD");
 458                         return ERROR_NAND_OPERATION_FAILED;
 459                 }
 460         } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
 461                 /* SLC_CMD = command */
 462                 retval = target_write_u32(target, 0x20020008, command);
 463                 if (ERROR_OK != retval) {
 464                         LOG_ERROR("could not set SLC_CMD");
 465                         return ERROR_NAND_OPERATION_FAILED;
 466                 }
 467         }
 468
 469         return ERROR_OK;
 470 }
 471
 472 static int lpc32xx_address(struct nand_device *nand, uint8_t address)
 473 {
 474         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 475         struct target *target = nand->target;
 476         int retval;
 477
 478         if (target->state != TARGET_HALTED) {
 479                 LOG_ERROR("target must be halted to use "
 480                         "LPC32xx NAND flash controller");
 481                 return ERROR_NAND_OPERATION_FAILED;
 482         }
 483
 484         if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
 485                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
 486                 return ERROR_NAND_OPERATION_FAILED;
 487         } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
 488                 /* MLC_ADDR = address */
 489                 retval = target_write_u32(target, 0x200b8004, address);
 490                 if (ERROR_OK != retval) {
 491                         LOG_ERROR("could not set MLC_ADDR");
 492                         return ERROR_NAND_OPERATION_FAILED;
 493                 }
 494         } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
 495                 /* SLC_ADDR = address */
 496                 retval = target_write_u32(target, 0x20020004, address);
 497                 if (ERROR_OK != retval) {
 498                         LOG_ERROR("could not set SLC_ADDR");
 499                         return ERROR_NAND_OPERATION_FAILED;
 500                 }
 501         }
 502
 503         return ERROR_OK;
 504 }
 505
 506 static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
 507 {
 508         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 509         struct target *target = nand->target;
 510         int retval;
 511
 512         if (target->state != TARGET_HALTED) {
 513                 LOG_ERROR("target must be halted to use "
 514                         "LPC32xx NAND flash controller");
 515                 return ERROR_NAND_OPERATION_FAILED;
 516         }
 517
 518         if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
 519                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
 520                 return ERROR_NAND_OPERATION_FAILED;
 521         } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
 522                 /* MLC_DATA = data */
 523                 retval = target_write_u32(target, 0x200b0000, data);
 524                 if (ERROR_OK != retval) {
 525                         LOG_ERROR("could not set MLC_DATA");
 526                         return ERROR_NAND_OPERATION_FAILED;
 527                 }
 528         } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
 529                 /* SLC_DATA = data */
 530                 retval = target_write_u32(target, 0x20020000, data);
 531                 if (ERROR_OK != retval) {
 532                         LOG_ERROR("could not set SLC_DATA");
 533                         return ERROR_NAND_OPERATION_FAILED;
 534                 }
 535         }
 536
 537         return ERROR_OK;
 538 }
 539
 540 static int lpc32xx_read_data(struct nand_device *nand, void *data)
 541 {
 542         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
 543         struct target *target = nand->target;
 544         int retval;
 545
 546         if (target->state != TARGET_HALTED) {
 547                 LOG_ERROR("target must be halted to use LPC32xx "
 548                         "NAND flash controller");
 549                 return ERROR_NAND_OPERATION_FAILED;
 550         }
 551
 552         if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
 553                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
 554                 return ERROR_NAND_OPERATION_FAILED;
 555         } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
 556                 /* data = MLC_DATA, use sized access */
 557                 if (nand->bus_width == 8) {
 558                         uint8_t *data8 = data;
 559                         retval = target_read_u8(target, 0x200b0000, data8);
 560                 } else {
 561                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 562                         return ERROR_NAND_OPERATION_FAILED;
 563                 }
 564                 if (ERROR_OK != retval) {
 565                         LOG_ERROR("could not read MLC_DATA");
 566                         return ERROR_NAND_OPERATION_FAILED;
 567                 }
 568         } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
 569                 uint32_t data32;
 570
 571                 /* data = SLC_DATA, must use 32-bit access */
 572                 retval = target_read_u32(target, 0x20020000, &data32);
 573                 if (ERROR_OK != retval) {
 574                         LOG_ERROR("could not read SLC_DATA");
 575                         return ERROR_NAND_OPERATION_FAILED;
 576                 }
 577
 578                 if (nand->bus_width == 8) {
 579                         uint8_t *data8 = data;
 580                         *data8 = data32 & 0xff;
 581                 } else {
 582                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 583                         return ERROR_NAND_OPERATION_FAILED;
 584                 }
 585         }
 586
 587         return ERROR_OK;
 588 }
 589
 590 static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
 591         uint8_t *data, uint32_t data_size,
 592         uint8_t *oob, uint32_t oob_size)
 593 {
 594         struct target *target = nand->target;
 595         int retval;
 596         uint8_t status;
 597         static uint8_t page_buffer[512];
 598         static uint8_t oob_buffer[6];
 599         int quarter, num_quarters;
 600
 601         /* MLC_CMD = sequential input */
 602         retval = target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
 603         if (ERROR_OK != retval) {
 604                 LOG_ERROR("could not set MLC_CMD");
 605                 return ERROR_NAND_OPERATION_FAILED;
 606         }
 607
 608         if (nand->page_size == 512) {
 609                 /* MLC_ADDR = 0x0 (one column cycle) */
 610                 retval = target_write_u32(target, 0x200b8004, 0x0);
 611                 if (ERROR_OK != retval) {
 612                         LOG_ERROR("could not set MLC_ADDR");
 613                         return ERROR_NAND_OPERATION_FAILED;
 614                 }
 615
 616                 /* MLC_ADDR = row */
 617                 retval = target_write_u32(target, 0x200b8004, page & 0xff);
 618                 if (ERROR_OK != retval) {
 619                         LOG_ERROR("could not set MLC_ADDR");
 620                         return ERROR_NAND_OPERATION_FAILED;
 621                 }
 622                 retval = target_write_u32(target, 0x200b8004,
 623                                 (page >> 8) & 0xff);
 624                 if (ERROR_OK != retval) {
 625                         LOG_ERROR("could not set MLC_ADDR");
 626                         return ERROR_NAND_OPERATION_FAILED;
 627                 }
 628
 629                 if (nand->address_cycles == 4) {
 630                         retval = target_write_u32(target, 0x200b8004,
 631                                         (page >> 16) & 0xff);
 632                         if (ERROR_OK != retval) {
 633                                 LOG_ERROR("could not set MLC_ADDR");
 634                                 return ERROR_NAND_OPERATION_FAILED;
 635                         }
 636                 }
 637         } else {
 638                 /* MLC_ADDR = 0x0 (two column cycles) */
 639                 retval = target_write_u32(target, 0x200b8004, 0x0);
 640                 if (ERROR_OK != retval) {
 641                         LOG_ERROR("could not set MLC_ADDR");
 642                         return ERROR_NAND_OPERATION_FAILED;
 643                 }
 644                 retval = target_write_u32(target, 0x200b8004, 0x0);
 645                 if (ERROR_OK != retval) {
 646                         LOG_ERROR("could not set MLC_ADDR");
 647                         return ERROR_NAND_OPERATION_FAILED;
 648                 }
 649
 650                 /* MLC_ADDR = row */
 651                 retval = target_write_u32(target, 0x200b8004, page & 0xff);
 652                 if (ERROR_OK != retval) {
 653                         LOG_ERROR("could not set MLC_ADDR");
 654                         return ERROR_NAND_OPERATION_FAILED;
 655                 }
 656                 retval = target_write_u32(target, 0x200b8004,
 657                                 (page >> 8) & 0xff);
 658                 if (ERROR_OK != retval) {
 659                         LOG_ERROR("could not set MLC_ADDR");
 660                         return ERROR_NAND_OPERATION_FAILED;
 661                 }
 662         }
 663
 664         /* when using the MLC controller, we have to treat a large page device
 665          * as being made out of four quarters, each the size of a small page
 666          * device
 667          */
 668         num_quarters = (nand->page_size == 2048) ? 4 : 1;
 669
 670         for (quarter = 0; quarter < num_quarters; quarter++) {
 671                 int thisrun_data_size = (data_size > 512) ? 512 : data_size;
 672                 int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
 673
 674                 memset(page_buffer, 0xff, 512);
 675                 if (data) {
 676                         memcpy(page_buffer, data, thisrun_data_size);
 677                         data_size -= thisrun_data_size;
 678                         data += thisrun_data_size;
 679                 }
 680
 681                 memset(oob_buffer, 0xff, 6);
 682                 if (oob) {
 683                         memcpy(oob_buffer, oob, thisrun_oob_size);
 684                         oob_size -= thisrun_oob_size;
 685                         oob += thisrun_oob_size;
 686                 }
 687
 688                 /* write MLC_ECC_ENC_REG to start encode cycle */
 689                 retval = target_write_u32(target, 0x200b8008, 0x0);
 690                 if (ERROR_OK != retval) {
 691                         LOG_ERROR("could not set MLC_ECC_ENC_REG");
 692                         return ERROR_NAND_OPERATION_FAILED;
 693                 }
 694
 695                 retval = target_write_memory(target, 0x200a8000,
 696                                 4, 128, page_buffer);
 697                 if (ERROR_OK != retval) {
 698                         LOG_ERROR("could not set MLC_BUF (data)");
 699                         return ERROR_NAND_OPERATION_FAILED;
 700                 }
 701                 retval = target_write_memory(target, 0x200a8000,
 702                                 1, 6, oob_buffer);
 703                 if (ERROR_OK != retval) {
 704                         LOG_ERROR("could not set MLC_BUF (oob)");
 705                         return ERROR_NAND_OPERATION_FAILED;
 706                 }
 707
 708                 /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
 709                 retval = target_write_u32(target, 0x200b8010, 0x0);
 710                 if (ERROR_OK != retval) {
 711                         LOG_ERROR("could not set MLC_ECC_AUTO_ENC_REG");
 712                         return ERROR_NAND_OPERATION_FAILED;
 713                 }
 714
 715                 if (!lpc32xx_controller_ready(nand, 1000)) {
 716                         LOG_ERROR("timeout while waiting for "
 717                                 "completion of auto encode cycle");
 718                         return ERROR_NAND_OPERATION_FAILED;
 719                 }
 720         }
 721
 722         /* MLC_CMD = auto program command */
 723         retval = target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
 724         if (ERROR_OK != retval) {
 725                 LOG_ERROR("could not set MLC_CMD");
 726                 return ERROR_NAND_OPERATION_FAILED;
 727         }
 728
 729         retval = nand_read_status(nand, &status);
 730         if (retval != ERROR_OK) {
 731                 LOG_ERROR("couldn't read status");
 732                 return ERROR_NAND_OPERATION_FAILED;
 733         }
 734
 735         if (status & NAND_STATUS_FAIL) {
 736                 LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
 737                         status);
 738                 return ERROR_NAND_OPERATION_FAILED;
 739         }
 740
 741         return ERROR_OK;
 742 }
 743
 744 /* SLC controller in !raw mode will use target cpu to read/write nand from/to
 745  * target internal memory.  The transfer to/from flash is done by DMA.  This
 746  * function sets up the dma linked list in host memory for later transfer to
 747  * target.
 748  */
 749 static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 750         int do_read)
 751 {
 752         uint32_t i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
 753
 754         /* DMACCxControl =
 755                 TransferSize =64,
 756                 Source burst size =16,
 757                 Destination burst size = 16,
 758                 Source transfer width = 32 bit,
 759                 Destination transfer width = 32 bit,
 760                 Source AHB master select = M0,
 761                 Destination AHB master select = M0,
 762                 Source increment = 0, // set later
 763                 Destination increment = 0, // set later
 764                 Terminal count interrupt enable bit = 0 // set on last
 765         */                      /*
 766          * Write Operation Sequence for Small Block NAND
 767          * ----------------------------------------------------------
 768          * 1. X'fer 256 bytes of data from Memory to Flash.
 769          * 2. Copy generated ECC data from Register to Spare Area
 770          * 3. X'fer next 256 bytes of data from Memory to Flash.
 771          * 4. Copy generated ECC data from Register to Spare Area.
 772          * 5. X'fer 16 byets of Spare area from Memory to Flash.
 773          * Read Operation Sequence for Small Block NAND
 774          * ----------------------------------------------------------
 775          * 1. X'fer 256 bytes of data from Flash to Memory.
 776          * 2. Copy generated ECC data from Register to ECC calc Buffer.
 777          * 3. X'fer next 256 bytes of data from Flash to Memory.
 778          * 4. Copy generated ECC data from Register to ECC calc Buffer.
 779          * 5. X'fer 16 bytes of Spare area from Flash to Memory.
 780          * Write Operation Sequence for Large Block NAND
 781          * ----------------------------------------------------------
 782          * 1. Steps(1-4) of Write Operations repeate for four times
 783          * which generates 16 DMA descriptors to X'fer 2048 bytes of
 784          * data & 32 bytes of ECC data.
 785          * 2. X'fer 64 bytes of Spare area from Memory to Flash.
 786          * Read Operation Sequence for Large Block NAND
 787          * ----------------------------------------------------------
 788          * 1. Steps(1-4) of Read Operations repeate for four times
 789          * which generates 16 DMA descriptors to X'fer 2048 bytes of
 790          * data & 32 bytes of ECC data.
 791          * 2. X'fer 64 bytes of Spare area from Flash to Memory.
 792          */
 793
 794         ctrl = (0x40 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
 795                 | 0 << 25 | 0 << 26 | 0 << 27 | 0 << 31);
 796
 797         /* DMACCxControl =
 798                 TransferSize =1,
 799                 Source burst size =4,
 800                 Destination burst size = 4,
 801                 Source transfer width = 32 bit,
 802                 Destination transfer width = 32 bit,
 803                 Source AHB master select = M0,
 804                 Destination AHB master select = M0,
 805                 Source increment = 0,
 806                 Destination increment = 1,
 807                 Terminal count interrupt enable bit = 0
 808          */
 809         ecc_ctrl = 0x01 | 1 << 12 | 1 << 15 | 2 << 18 | 2 << 21 | 0 << 24
 810                 | 0 << 25 | 0 << 26 | 1 << 27 | 0 << 31;
 811
 812         /* DMACCxControl =
 813                 TransferSize =16 for lp or 4 for sp,
 814                 Source burst size =16,
 815                 Destination burst size = 16,
 816                 Source transfer width = 32 bit,
 817                 Destination transfer width = 32 bit,
 818                 Source AHB master select = M0,
 819                 Destination AHB master select = M0,
 820                 Source increment = 0, // set later
 821                 Destination increment = 0, // set later
 822                 Terminal count interrupt enable bit = 1 // set on last
 823          */
 824         oob_ctrl = (page_size == 2048 ? 0x10 : 0x04)
 825                 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
 826                 | 0 << 25 | 0 << 26 | 0 << 27 | 1 << 31;
 827         if (do_read) {
 828                 ctrl |= 1 << 27;/* Destination increment = 1 */
 829                 oob_ctrl |= 1 << 27;    /* Destination increment = 1 */
 830                 dmasrc = 0x20020038;    /* SLC_DMA_DATA */
 831                 dmadst = target_mem_base + DATA_OFFS;
 832         } else {
 833                 ctrl |= 1 << 26;/* Source increment = 1 */
 834                 oob_ctrl |= 1 << 26;    /* Source increment = 1 */
 835                 dmasrc = target_mem_base + DATA_OFFS;
 836                 dmadst = 0x20020038;    /* SLC_DMA_DATA */
 837         }
 838         /*
 839          * Write Operation Sequence for Small Block NAND
 840          * ----------------------------------------------------------
 841          * 1. X'fer 256 bytes of data from Memory to Flash.
 842          * 2. Copy generated ECC data from Register to Spare Area
 843          * 3. X'fer next 256 bytes of data from Memory to Flash.
 844          * 4. Copy generated ECC data from Register to Spare Area.
 845          * 5. X'fer 16 byets of Spare area from Memory to Flash.
 846          * Read Operation Sequence for Small Block NAND
 847          * ----------------------------------------------------------
 848          * 1. X'fer 256 bytes of data from Flash to Memory.
 849          * 2. Copy generated ECC data from Register to ECC calc Buffer.
 850          * 3. X'fer next 256 bytes of data from Flash to Memory.
 851          * 4. Copy generated ECC data from Register to ECC calc Buffer.
 852          * 5. X'fer 16 bytes of Spare area from Flash to Memory.
 853          * Write Operation Sequence for Large Block NAND
 854          * ----------------------------------------------------------
 855          * 1. Steps(1-4) of Write Operations repeate for four times
 856          * which generates 16 DMA descriptors to X'fer 2048 bytes of
 857          * data & 32 bytes of ECC data.
 858          * 2. X'fer 64 bytes of Spare area from Memory to Flash.
 859          * Read Operation Sequence for Large Block NAND
 860          * ----------------------------------------------------------
 861          * 1. Steps(1-4) of Read Operations repeate for four times
 862          * which generates 16 DMA descriptors to X'fer 2048 bytes of
 863          * data & 32 bytes of ECC data.
 864          * 2. X'fer 64 bytes of Spare area from Flash to Memory.
 865          */
 866         for (i = 0; i < page_size/0x100; i++) {
 867                 dmalist[i*2].dma_src = (do_read ? dmasrc : (dmasrc + i * 256));
 868                 dmalist[i*2].dma_dest = (do_read ? (dmadst + i * 256) : dmadst);
 869                 dmalist[i*2].next_lli =
 870                         target_mem_base + (i*2 + 1) * sizeof(dmac_ll_t);
 871                 dmalist[i*2].next_ctrl = ctrl;
 872
 873                 dmalist[(i*2) + 1].dma_src = 0x20020034;/* SLC_ECC */
 874                 dmalist[(i*2) + 1].dma_dest =
 875                         target_mem_base + ECC_OFFS + i * 4;
 876                 dmalist[(i*2) + 1].next_lli =
 877                         target_mem_base + (i*2 + 2) * sizeof(dmac_ll_t);
 878                 dmalist[(i*2) + 1].next_ctrl = ecc_ctrl;
 879
 880         }
 881         if (do_read)
 882                 dmadst = target_mem_base + SPARE_OFFS;
 883         else {
 884                 dmasrc = target_mem_base + SPARE_OFFS;
 885                 dmalist[(i*2) - 1].next_lli = 0;/* last link = null on write */
 886                 dmalist[(i*2) - 1].next_ctrl |= (1 << 31);      /* Set TC enable */
 887         }
 888         dmalist[i*2].dma_src = dmasrc;
 889         dmalist[i*2].dma_dest = dmadst;
 890         dmalist[i*2].next_lli = 0;
 891         dmalist[i*2].next_ctrl = oob_ctrl;
 892
 893         return i * 2 + 1;       /* Number of descriptors */
 894 }
 895
 896 static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count,
 897         int do_wait)
 898 {
 899         struct target *target = nand->target;
 900         int retval;
 901
 902         /* DMACIntTCClear = ch0 */
 903         retval = target_write_u32(target, 0x31000008, 1);
 904         if (ERROR_OK != retval) {
 905                 LOG_ERROR("Could not set DMACIntTCClear");
 906                 return retval;
 907         }
 908
 909         /* DMACIntErrClear = ch0 */
 910         retval = target_write_u32(target, 0x31000010, 1);
 911         if (ERROR_OK != retval) {
 912                 LOG_ERROR("Could not set DMACIntErrClear");
 913                 return retval;
 914         }
 915
 916         /* DMACCxConfig=
 917                 E=1,
 918                 SrcPeripheral = 1 (SLC),
 919                 DestPeripheral = 1 (SLC),
 920                 FlowCntrl = 2 (Pher -> Mem, DMA),
 921                 IE = 0,
 922                 ITC = 0,
 923                 L= 0,
 924                 H=0
 925         */
 926         retval = target_write_u32(target, 0x31000110,
 927                         1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
 928                         | 0<<15 | 0<<16 | 0<<18);
 929         if (ERROR_OK != retval) {
 930                 LOG_ERROR("Could not set DMACC0Config");
 931                 return retval;
 932         }
 933
 934         /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
 935         retval = target_write_u32(target, 0x20020010, 0x3);
 936         if (ERROR_OK != retval) {
 937                 LOG_ERROR("Could not set SLC_CTRL");
 938                 return retval;
 939         }
 940
 941         /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
 942         retval = target_write_u32(target, 0x20020028, 2);
 943         if (ERROR_OK != retval) {
 944                 LOG_ERROR("Could not set SLC_ICR");
 945                 return retval;
 946         }
 947
 948         /* SLC_TC */
 949         retval = target_write_u32(target, 0x20020030, count);
 950         if (ERROR_OK != retval) {
 951                 LOG_ERROR("lpc32xx_start_slc_dma: Could not set SLC_TC");
 952                 return retval;
 953         }
 954
 955         /* Wait finish */
 956         if (do_wait && !lpc32xx_tc_ready(nand, 100)) {
 957                 LOG_ERROR("timeout while waiting for completion of DMA");
 958                 return ERROR_NAND_OPERATION_FAILED;
 959         }
 960
 961         return retval;
 962 }
 963
 964 static int lpc32xx_dma_ready(struct nand_device *nand, int timeout)
 965 {
 966         struct target *target = nand->target;
 967
 968         LOG_DEBUG("lpc32xx_dma_ready count start=%d", timeout);
 969
 970         do {
 971                 uint32_t tc_stat;
 972                 uint32_t err_stat;
 973                 int retval;
 974
 975                 /* Read DMACRawIntTCStat */
 976                 retval = target_read_u32(target, 0x31000014, &tc_stat);
 977                 if (ERROR_OK != retval) {
 978                         LOG_ERROR("Could not read DMACRawIntTCStat");
 979                         return 0;
 980                 }
 981                 /* Read DMACRawIntErrStat */
 982                 retval = target_read_u32(target, 0x31000018, &err_stat);
 983                 if (ERROR_OK != retval) {
 984                         LOG_ERROR("Could not read DMACRawIntErrStat");
 985                         return 0;
 986                 }
 987                 if ((tc_stat | err_stat) & 1) {
 988                         LOG_DEBUG("lpc32xx_dma_ready count=%d",
 989                                 timeout);
 990                         if (err_stat & 1) {
 991                                 LOG_ERROR("lpc32xx_dma_ready "
 992                                         "DMA error, aborted");
 993                                 return 0;
 994                         } else
 995                                 return 1;
 996                 }
 997
 998                 alive_sleep(1);
 999         } while (timeout-- > 0);
1000
1001         return 0;
1002 }
1003
1004 static uint32_t slc_ecc_copy_to_buffer(uint8_t *spare,
1005         const uint32_t *ecc, int count)
1006 {
1007         int i;
1008         for (i = 0; i < (count * 3); i += 3) {
1009                 uint32_t ce = ecc[i/3];
1010                 ce = ~(ce << 2) & 0xFFFFFF;
1011                 spare[i+2] = (uint8_t)(ce & 0xFF); ce >>= 8;
1012                 spare[i+1] = (uint8_t)(ce & 0xFF); ce >>= 8;
1013                 spare[i]   = (uint8_t)(ce & 0xFF);
1014         }
1015         return 0;
1016 }
1017
1018 static void lpc32xx_dump_oob(uint8_t *oob, uint32_t oob_size)
1019 {
1020         int addr = 0;
1021         while (oob_size > 0) {
1022                 LOG_DEBUG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x", addr,
1023                         oob[0], oob[1], oob[2], oob[3],
1024                         oob[4], oob[5], oob[6], oob[7]);
1025                 oob += 8;
1026                 addr += 8;
1027                 oob_size -= 8;
1028         }
1029 }
1030
1031 static int lpc32xx_write_page_slc(struct nand_device *nand,
1032         struct working_area *pworking_area,
1033         uint32_t page, uint8_t *data,
1034         uint32_t data_size, uint8_t *oob,
1035         uint32_t oob_size)
1036 {
1037         struct target *target = nand->target;
1038         int retval;
1039         uint32_t target_mem_base;
1040
1041         LOG_DEBUG("SLC write page %" PRIx32 " data=%d, oob=%d, "
1042                 "data_size=%" PRIu32 ", oob_size=%" PRIu32,
1043                 page, data != 0, oob != 0, data_size, oob_size);
1044
1045         target_mem_base = pworking_area->address;
1046         /*
1047          * Skip writting page which has all 0xFF data as this will
1048          * generate 0x0 value.
1049          */
1050         if (data && !oob) {
1051                 uint32_t i, all_ff = 1;
1052                 for (i = 0; i < data_size; i++)
1053                         if (data[i] != 0xFF) {
1054                                 all_ff = 0;
1055                                 break;
1056                         }
1057                 if (all_ff)
1058                         return ERROR_OK;
1059         }
1060         /* Make the dma descriptors in local memory */
1061         int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 0);
1062         /* Write them to target.
1063            XXX: Assumes host and target have same byte sex.
1064         */
1065         retval = target_write_memory(target, target_mem_base, 4,
1066                         nll * sizeof(dmac_ll_t) / 4,
1067                         (uint8_t *)dmalist);
1068         if (ERROR_OK != retval) {
1069                 LOG_ERROR("Could not write DMA descriptors to IRAM");
1070                 return retval;
1071         }
1072
1073         retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
1074         if (ERROR_OK != retval) {
1075                 LOG_ERROR("NAND_CMD_SEQIN failed");
1076                 return retval;
1077         }
1078
1079         /* SLC_CFG =
1080                Force nCE assert,
1081                DMA ECC enabled,
1082                ECC enabled,
1083                DMA burst enabled,
1084                DMA write to SLC,
1085                WIDTH = bus_width
1086         */
1087         retval = target_write_u32(target, 0x20020014, 0x3c);
1088         if (ERROR_OK != retval) {
1089                 LOG_ERROR("Could not set SLC_CFG");
1090                 return retval;
1091         }
1092         if (data) {
1093                 /* Write data to target */
1094                 static uint8_t fdata[2048];
1095                 memset(fdata, 0xFF, nand->page_size);
1096                 memcpy(fdata, data, data_size);
1097                 retval = target_write_memory(target,
1098                                 target_mem_base + DATA_OFFS,
1099                                 4, nand->page_size/4, fdata);
1100                 if (ERROR_OK != retval) {
1101                         LOG_ERROR("Could not write data to IRAM");
1102                         return retval;
1103                 }
1104
1105                 /* Write first decriptor to DMA controller */
1106                 retval = target_write_memory(target, 0x31000100, 4,
1107                                 sizeof(dmac_ll_t) / 4,
1108                                 (uint8_t *)dmalist);
1109                 if (ERROR_OK != retval) {
1110                         LOG_ERROR("Could not write DMA descriptor to DMAC");
1111                         return retval;
1112                 }
1113
1114                 /* Start xfer of data from iram to flash using DMA */
1115                 int tot_size = nand->page_size;
1116                 tot_size += tot_size == 2048 ? 64 : 16;
1117                 retval = lpc32xx_start_slc_dma(nand, tot_size, 0);
1118                 if (ERROR_OK != retval) {
1119                         LOG_ERROR("DMA failed");
1120                         return retval;
1121                 }
1122
1123                 /* Wait for DMA to finish.  SLC is not finished at this stage */
1124                 if (!lpc32xx_dma_ready(nand, 100)) {
1125                         LOG_ERROR("Data DMA failed during write");
1126                         return ERROR_FLASH_OPERATION_FAILED;
1127                 }
1128         }       /* data xfer */
1129
1130         /* Copy OOB to iram */
1131         static uint8_t foob[64];
1132         int foob_size = nand->page_size == 2048 ? 64 : 16;
1133         memset(foob, 0xFF, foob_size);
1134         if (oob)        /* Raw mode */
1135                 memcpy(foob, oob, oob_size);
1136         else {
1137                 /* Get HW generated ECC, made while writing data */
1138                 int ecc_count = nand->page_size == 2048 ? 8 : 2;
1139                 static uint32_t hw_ecc[8];
1140                 retval = target_read_memory(target, target_mem_base + ECC_OFFS,
1141                                 4, ecc_count, (uint8_t *)hw_ecc);
1142                 if (ERROR_OK != retval) {
1143                         LOG_ERROR("Reading hw generated ECC from IRAM failed");
1144                         return retval;
1145                 }
1146                 /* Copy to oob, at correct offsets */
1147                 static uint8_t ecc[24];
1148                 slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
1149                 const int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
1150                 int i;
1151                 for (i = 0; i < ecc_count * 3; i++)
1152                         foob[layout[i]] = ecc[i];
1153                 lpc32xx_dump_oob(foob, foob_size);
1154         }
1155         retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4,
1156                         foob_size / 4, foob);
1157         if (ERROR_OK != retval) {
1158                 LOG_ERROR("Writing OOB to IRAM failed");
1159                 return retval;
1160         }
1161
1162         /* Write OOB decriptor to DMA controller */
1163         retval = target_write_memory(target, 0x31000100, 4,
1164                         sizeof(dmac_ll_t) / 4,
1165                         (uint8_t *)(&dmalist[nll-1]));
1166         if (ERROR_OK != retval) {
1167                 LOG_ERROR("Could not write OOB DMA descriptor to DMAC");
1168                 return retval;
1169         }
1170         if (data) {
1171                 /* Only restart DMA with last descriptor,
1172                  * don't setup SLC again */
1173
1174                 /* DMACIntTCClear = ch0 */
1175                 retval = target_write_u32(target, 0x31000008, 1);
1176                 if (ERROR_OK != retval) {
1177                         LOG_ERROR("Could not set DMACIntTCClear");
1178                         return retval;
1179                 }
1180                 /* DMACCxConfig=
1181                  * E=1,
1182                  * SrcPeripheral = 1 (SLC),
1183                  * DestPeripheral = 1 (SLC),
1184                  * FlowCntrl = 2 (Pher -> Mem, DMA),
1185                  * IE = 0,
1186                  * ITC = 0,
1187                  * L= 0,
1188                  * H=0
1189                 */
1190                 retval = target_write_u32(target, 0x31000110,
1191                                 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
1192                                 | 0<<15 | 0<<16 | 0<<18);
1193                 if (ERROR_OK != retval) {
1194                         LOG_ERROR("Could not set DMACC0Config");
1195                         return retval;
1196                 }
1197                 /* Wait finish */
1198                 if (!lpc32xx_tc_ready(nand, 100)) {
1199                         LOG_ERROR("timeout while waiting for "
1200                                 "completion of DMA");
1201                         return ERROR_NAND_OPERATION_FAILED;
1202                 }
1203         } else {
1204                 /* Start xfer of data from iram to flash using DMA */
1205                 retval = lpc32xx_start_slc_dma(nand, foob_size, 1);
1206                 if (ERROR_OK != retval) {
1207                         LOG_ERROR("DMA OOB failed");
1208                         return retval;
1209                 }
1210         }
1211
1212         /* Let NAND start actual writing */
1213         retval = nand_write_finish(nand);
1214         if (ERROR_OK != retval) {
1215                 LOG_ERROR("nand_write_finish failed");
1216                 return retval;
1217         }
1218
1219         return ERROR_OK;
1220 }
1221
1222 static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,
1223         uint8_t *data, uint32_t data_size,
1224         uint8_t *oob, uint32_t oob_size)
1225 {
1226         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1227         struct target *target = nand->target;
1228         int retval = ERROR_OK;
1229
1230         if (target->state != TARGET_HALTED) {
1231                 LOG_ERROR("target must be halted to use LPC32xx "
1232                         "NAND flash controller");
1233                 return ERROR_NAND_OPERATION_FAILED;
1234         }
1235
1236         if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
1237                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
1238                 return ERROR_NAND_OPERATION_FAILED;
1239         } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1240                 if (!data && oob) {
1241                         LOG_ERROR("LPC32xx MLC controller can't write "
1242                                 "OOB data only");
1243                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1244                 }
1245
1246                 if (oob && (oob_size > 24)) {
1247                         LOG_ERROR("LPC32xx MLC controller can't write more "
1248                                 "than 6 bytes for each quarter's OOB data");
1249                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1250                 }
1251
1252                 if (data_size > (uint32_t)nand->page_size) {
1253                         LOG_ERROR("data size exceeds page size");
1254                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1255                 }
1256
1257                 retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
1258                                 oob, oob_size);
1259         } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1260                 struct working_area *pworking_area;
1261                 if (!data && oob) {
1262                         /*
1263                          * if oob only mode is active original method is used
1264                          * as SLC controller hangs during DMA interworking. (?)
1265                          * Anyway the code supports the oob only mode below.
1266                          */
1267                         return nand_write_page_raw(nand, page, data,
1268                                 data_size, oob, oob_size);
1269                 }
1270                 retval = target_alloc_working_area(target,
1271                                 nand->page_size + DATA_OFFS,
1272                                 &pworking_area);
1273                 if (retval != ERROR_OK) {
1274                         LOG_ERROR("Can't allocate working area in "
1275                                 "LPC internal RAM");
1276                         return ERROR_FLASH_OPERATION_FAILED;
1277                 }
1278                 retval = lpc32xx_write_page_slc(nand, pworking_area, page,
1279                                 data, data_size, oob, oob_size);
1280                 target_free_working_area(target, pworking_area);
1281         }
1282
1283         return retval;
1284 }
1285
1286 static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page,
1287         uint8_t *data, uint32_t data_size,
1288         uint8_t *oob, uint32_t oob_size)
1289 {
1290         struct target *target = nand->target;
1291         static uint8_t page_buffer[2048];
1292         static uint8_t oob_buffer[64];
1293         uint32_t page_bytes_done = 0;
1294         uint32_t oob_bytes_done = 0;
1295         uint32_t mlc_isr;
1296         int retval;
1297
1298         if (!data && oob) {
1299                 /* MLC_CMD = Read OOB
1300                  * we can use the READOOB command on both small and large page
1301                  * devices, as the controller translates the 0x50 command to
1302                  * a 0x0 with appropriate positioning of the serial buffer
1303                  * read pointer
1304                  */
1305                 retval = target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
1306         } else {
1307                 /* MLC_CMD = Read0 */
1308                 retval = target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
1309         }
1310         if (ERROR_OK != retval) {
1311                 LOG_ERROR("could not set MLC_CMD");
1312                 return ERROR_NAND_OPERATION_FAILED;
1313         }
1314         if (nand->page_size == 512) {
1315                 /* small page device
1316                  * MLC_ADDR = 0x0 (one column cycle) */
1317                 retval = target_write_u32(target, 0x200b8004, 0x0);
1318                 if (ERROR_OK != retval) {
1319                         LOG_ERROR("could not set MLC_ADDR");
1320                         return ERROR_NAND_OPERATION_FAILED;
1321                 }
1322
1323                 /* MLC_ADDR = row */
1324                 retval = target_write_u32(target, 0x200b8004, page & 0xff);
1325                 if (ERROR_OK != retval) {
1326                         LOG_ERROR("could not set MLC_ADDR");
1327                         return ERROR_NAND_OPERATION_FAILED;
1328                 }
1329                 retval = target_write_u32(target, 0x200b8004,
1330                                 (page >> 8) & 0xff);
1331                 if (ERROR_OK != retval) {
1332                         LOG_ERROR("could not set MLC_ADDR");
1333                         return ERROR_NAND_OPERATION_FAILED;
1334                 }
1335
1336                 if (nand->address_cycles == 4) {
1337                         retval = target_write_u32(target, 0x200b8004,
1338                                         (page >> 16) & 0xff);
1339                         if (ERROR_OK != retval) {
1340                                 LOG_ERROR("could not set MLC_ADDR");
1341                                 return ERROR_NAND_OPERATION_FAILED;
1342                         }
1343                 }
1344         } else {
1345                 /* large page device
1346                  * MLC_ADDR = 0x0 (two column cycles) */
1347                 retval = target_write_u32(target, 0x200b8004, 0x0);
1348                 if (ERROR_OK != retval) {
1349                         LOG_ERROR("could not set MLC_ADDR");
1350                         return ERROR_NAND_OPERATION_FAILED;
1351                 }
1352                 retval = target_write_u32(target, 0x200b8004, 0x0);
1353                 if (ERROR_OK != retval) {
1354                         LOG_ERROR("could not set MLC_ADDR");
1355                         return ERROR_NAND_OPERATION_FAILED;
1356                 }
1357
1358                 /* MLC_ADDR = row */
1359                 retval = target_write_u32(target, 0x200b8004, page & 0xff);
1360                 if (ERROR_OK != retval) {
1361                         LOG_ERROR("could not set MLC_ADDR");
1362                         return ERROR_NAND_OPERATION_FAILED;
1363                 }
1364                 retval = target_write_u32(target, 0x200b8004,
1365                                 (page >> 8) & 0xff);
1366                 if (ERROR_OK != retval) {
1367                         LOG_ERROR("could not set MLC_ADDR");
1368                         return ERROR_NAND_OPERATION_FAILED;
1369                 }
1370
1371                 /* MLC_CMD = Read Start */
1372                 retval = target_write_u32(target, 0x200b8000,
1373                                 NAND_CMD_READSTART);
1374                 if (ERROR_OK != retval) {
1375                         LOG_ERROR("could not set MLC_CMD");
1376                         return ERROR_NAND_OPERATION_FAILED;
1377                 }
1378         }
1379
1380         while (page_bytes_done < (uint32_t)nand->page_size) {
1381                 /* MLC_ECC_AUTO_DEC_REG = dummy */
1382                 retval = target_write_u32(target, 0x200b8014, 0xaa55aa55);
1383                 if (ERROR_OK != retval) {
1384                         LOG_ERROR("could not set MLC_ECC_AUTO_DEC_REG");
1385                         return ERROR_NAND_OPERATION_FAILED;
1386                 }
1387
1388                 if (!lpc32xx_controller_ready(nand, 1000)) {
1389                         LOG_ERROR("timeout while waiting for "
1390                                 "completion of auto decode cycle");
1391                         return ERROR_NAND_OPERATION_FAILED;
1392                 }
1393
1394                 retval = target_read_u32(target, 0x200b8048, &mlc_isr);
1395                 if (ERROR_OK != retval) {
1396                         LOG_ERROR("could not read MLC_ISR");
1397                         return ERROR_NAND_OPERATION_FAILED;
1398                 }
1399
1400                 if (mlc_isr & 0x8) {
1401                         if (mlc_isr & 0x40) {
1402                                 LOG_ERROR("uncorrectable error detected: "
1403                                         "0x%2.2x", (unsigned)mlc_isr);
1404                                 return ERROR_NAND_OPERATION_FAILED;
1405                         }
1406
1407                         LOG_WARNING("%i symbol error detected and corrected",
1408                                 ((int)(((mlc_isr & 0x30) >> 4) + 1)));
1409                 }
1410
1411                 if (data) {
1412                         retval = target_read_memory(target, 0x200a8000, 4, 128,
1413                                         page_buffer + page_bytes_done);
1414                         if (ERROR_OK != retval) {
1415                                 LOG_ERROR("could not read MLC_BUF (data)");
1416                                 return ERROR_NAND_OPERATION_FAILED;
1417                         }
1418                 }
1419
1420                 if (oob) {
1421                         retval = target_read_memory(target, 0x200a8000, 4, 4,
1422                                         oob_buffer + oob_bytes_done);
1423                         if (ERROR_OK != retval) {
1424                                 LOG_ERROR("could not read MLC_BUF (oob)");
1425                                 return ERROR_NAND_OPERATION_FAILED;
1426                         }
1427                 }
1428
1429                 page_bytes_done += 512;
1430                 oob_bytes_done += 16;
1431         }
1432
1433         if (data)
1434                 memcpy(data, page_buffer, data_size);
1435
1436         if (oob)
1437                 memcpy(oob, oob_buffer, oob_size);
1438
1439         return ERROR_OK;
1440 }
1441
1442 static int lpc32xx_read_page_slc(struct nand_device *nand,
1443         struct working_area *pworking_area,
1444         uint32_t page, uint8_t *data,
1445         uint32_t data_size, uint8_t *oob,
1446         uint32_t oob_size)
1447 {
1448         struct target *target = nand->target;
1449         int retval;
1450         uint32_t target_mem_base;
1451
1452         LOG_DEBUG("SLC read page %" PRIx32 " data=%" PRIu32 ", oob=%" PRIu32,
1453                 page, data_size, oob_size);
1454
1455         target_mem_base = pworking_area->address;
1456
1457         /* Make the dma descriptors in local memory */
1458         int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 1);
1459         /* Write them to target.
1460            XXX: Assumes host and target have same byte sex.
1461         */
1462         retval = target_write_memory(target, target_mem_base, 4,
1463                         nll * sizeof(dmac_ll_t) / 4,
1464                         (uint8_t *)dmalist);
1465         if (ERROR_OK != retval) {
1466                 LOG_ERROR("Could not write DMA descriptors to IRAM");
1467                 return retval;
1468         }
1469
1470         retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
1471         if (ERROR_OK != retval) {
1472                 LOG_ERROR("lpc32xx_read_page_slc: NAND_CMD_READ0 failed");
1473                 return retval;
1474         }
1475
1476         /* SLC_CFG =
1477                Force nCE assert,
1478                DMA ECC enabled,
1479                ECC enabled,
1480                DMA burst enabled,
1481                DMA read from SLC,
1482                WIDTH = bus_width
1483         */
1484         retval = target_write_u32(target, 0x20020014, 0x3e);
1485         if (ERROR_OK != retval) {
1486                 LOG_ERROR("lpc32xx_read_page_slc: Could not set SLC_CFG");
1487                 return retval;
1488         }
1489
1490         /* Write first decriptor to DMA controller */
1491         retval = target_write_memory(target, 0x31000100, 4,
1492                         sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist);
1493         if (ERROR_OK != retval) {
1494                 LOG_ERROR("Could not write DMA descriptor to DMAC");
1495                 return retval;
1496         }
1497
1498         /* Start xfer of data from flash to iram using DMA */
1499         int tot_size = nand->page_size;
1500         tot_size += nand->page_size == 2048 ? 64 : 16;
1501         retval = lpc32xx_start_slc_dma(nand, tot_size, 1);
1502         if (ERROR_OK != retval) {
1503                 LOG_ERROR("lpc32xx_read_page_slc: DMA read failed");
1504                 return retval;
1505         }
1506
1507         /* Copy data from iram */
1508         if (data) {
1509                 retval = target_read_memory(target, target_mem_base + DATA_OFFS,
1510                                 4, data_size/4, data);
1511                 if (ERROR_OK != retval) {
1512                         LOG_ERROR("Could not read data from IRAM");
1513                         return retval;
1514                 }
1515         }
1516         if (oob) {
1517                 /* No error correction, just return data as read from flash */
1518                 retval = target_read_memory(target,
1519                                 target_mem_base + SPARE_OFFS, 4,
1520                                 oob_size/4, oob);
1521                 if (ERROR_OK != retval) {
1522                         LOG_ERROR("Could not read OOB from IRAM");
1523                         return retval;
1524                 }
1525                 return ERROR_OK;
1526         }
1527
1528         /* Copy OOB from flash, stored in IRAM */
1529         static uint8_t foob[64];
1530         retval = target_read_memory(target, target_mem_base + SPARE_OFFS,
1531                         4, nand->page_size == 2048 ? 16 : 4, foob);
1532         lpc32xx_dump_oob(foob, nand->page_size == 2048 ? 64 : 16);
1533         if (ERROR_OK != retval) {
1534                 LOG_ERROR("Could not read OOB from IRAM");
1535                 return retval;
1536         }
1537         /* Copy ECC from HW, generated while reading */
1538         int ecc_count = nand->page_size == 2048 ? 8 : 2;
1539         static uint32_t hw_ecc[8];      /* max size */
1540         retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4,
1541                         ecc_count, (uint8_t *)hw_ecc);
1542         if (ERROR_OK != retval) {
1543                 LOG_ERROR("Could not read hw generated ECC from IRAM");
1544                 return retval;
1545         }
1546         static uint8_t ecc[24];
1547         slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
1548         /* Copy ECC from flash using correct layout */
1549         static uint8_t fecc[24];/* max size */
1550         const int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
1551         int i;
1552         for (i = 0; i < ecc_count * 3; i++)
1553                 fecc[i] = foob[layout[i]];
1554         /* Compare ECC and possibly correct data */
1555         for (i = 0; i < ecc_count; i++) {
1556                 retval = nand_correct_data(nand, data + 256*i, &fecc[i * 3],
1557                                 &ecc[i * 3]);
1558                 if (retval > 0)
1559                         LOG_WARNING("error detected and corrected: %" PRIu32 "/%d",
1560                                 page, i);
1561                 if (retval < 0)
1562                         break;
1563         }
1564         if (i == ecc_count)
1565                 retval = ERROR_OK;
1566         else {
1567                 LOG_ERROR("uncorrectable error detected: %" PRIu32 "/%d", page, i);
1568                 retval = ERROR_NAND_OPERATION_FAILED;
1569         }
1570         return retval;
1571 }
1572
1573 static int lpc32xx_read_page(struct nand_device *nand, uint32_t page,
1574         uint8_t *data, uint32_t data_size,
1575         uint8_t *oob, uint32_t oob_size)
1576 {
1577         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1578         struct target *target = nand->target;
1579         int retval = ERROR_OK;
1580
1581         if (target->state != TARGET_HALTED) {
1582                 LOG_ERROR("target must be halted to use LPC32xx "
1583                         "NAND flash controller");
1584                 return ERROR_NAND_OPERATION_FAILED;
1585         }
1586
1587         if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
1588                 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
1589                 return ERROR_NAND_OPERATION_FAILED;
1590         } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1591                 if (data_size > (uint32_t)nand->page_size) {
1592                         LOG_ERROR("data size exceeds page size");
1593                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1594                 }
1595                 retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
1596                                 oob, oob_size);
1597         } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1598                 struct working_area *pworking_area;
1599
1600                 retval = target_alloc_working_area(target,
1601                                 nand->page_size + 0x200,
1602                                 &pworking_area);
1603                 if (retval != ERROR_OK) {
1604                         LOG_ERROR("Can't allocate working area in "
1605                                 "LPC internal RAM");
1606                         return ERROR_FLASH_OPERATION_FAILED;
1607                 }
1608                 retval = lpc32xx_read_page_slc(nand, pworking_area, page,
1609                                 data, data_size, oob, oob_size);
1610                 target_free_working_area(target, pworking_area);
1611         }
1612
1613         return retval;
1614 }
1615
1616 static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
1617 {
1618         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1619         struct target *target = nand->target;
1620         int retval;
1621
1622         if (target->state != TARGET_HALTED) {
1623                 LOG_ERROR("target must be halted to use LPC32xx "
1624                         "NAND flash controller");
1625                 return ERROR_NAND_OPERATION_FAILED;
1626         }
1627
1628         LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
1629
1630         do {
1631                 if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1632                         uint8_t status;
1633
1634                         /* Read MLC_ISR, wait for controller to become ready */
1635                         retval = target_read_u8(target, 0x200b8048, &status);
1636                         if (ERROR_OK != retval) {
1637                                 LOG_ERROR("could not set MLC_STAT");
1638                                 return ERROR_NAND_OPERATION_FAILED;
1639                         }
1640
1641                         if (status & 2) {
1642                                 LOG_DEBUG("lpc32xx_controller_ready count=%d",
1643                                         timeout);
1644                                 return 1;
1645                         }
1646                 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1647                         uint32_t status;
1648
1649                         /* Read SLC_STAT and check READY bit */
1650                         retval = target_read_u32(target, 0x20020018, &status);
1651                         if (ERROR_OK != retval) {
1652                                 LOG_ERROR("could not set SLC_STAT");
1653                                 return ERROR_NAND_OPERATION_FAILED;
1654                         }
1655
1656                         if (status & 1) {
1657                                 LOG_DEBUG("lpc32xx_controller_ready count=%d",
1658                                         timeout);
1659                                 return 1;
1660                         }
1661                 }
1662
1663                 alive_sleep(1);
1664         } while (timeout-- > 0);
1665
1666         return 0;
1667 }
1668
1669 static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
1670 {
1671         struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1672         struct target *target = nand->target;
1673         int retval;
1674
1675         if (target->state != TARGET_HALTED) {
1676                 LOG_ERROR("target must be halted to use LPC32xx "
1677                         "NAND flash controller");
1678                 return ERROR_NAND_OPERATION_FAILED;
1679         }
1680
1681         LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
1682
1683         do {
1684                 if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1685                         uint8_t status = 0x0;
1686
1687                         /* Read MLC_ISR, wait for NAND flash device to
1688                          * become ready */
1689                         retval = target_read_u8(target, 0x200b8048, &status);
1690                         if (ERROR_OK != retval) {
1691                                 LOG_ERROR("could not read MLC_ISR");
1692                                 return ERROR_NAND_OPERATION_FAILED;
1693                         }
1694
1695                         if (status & 1) {
1696                                 LOG_DEBUG("lpc32xx_nand_ready count end=%d",
1697                                         timeout);
1698                                 return 1;
1699                         }
1700                 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1701                         uint32_t status = 0x0;
1702
1703                         /* Read SLC_STAT and check READY bit */
1704                         retval = target_read_u32(target, 0x20020018, &status);
1705                         if (ERROR_OK != retval) {
1706                                 LOG_ERROR("could not read SLC_STAT");
1707                                 return ERROR_NAND_OPERATION_FAILED;
1708                         }
1709
1710                         if (status & 1) {
1711                                 LOG_DEBUG("lpc32xx_nand_ready count end=%d",
1712                                         timeout);
1713                                 return 1;
1714                         }
1715                 }
1716
1717                 alive_sleep(1);
1718         } while (timeout-- > 0);
1719
1720         return 0;
1721 }
1722
1723 static int lpc32xx_tc_ready(struct nand_device *nand, int timeout)
1724 {
1725         struct target *target = nand->target;
1726
1727         LOG_DEBUG("lpc32xx_tc_ready count start=%d", timeout);
1728
1729         do {
1730                 uint32_t status = 0x0;
1731                 int retval;
1732                 /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1733                 retval = target_read_u32(target, 0x2002001c, &status);
1734                 if (ERROR_OK != retval) {
1735                         LOG_ERROR("Could not read SLC_INT_STAT");
1736                         return 0;
1737                 }
1738                 if (status & 2) {
1739                         LOG_DEBUG("lpc32xx_tc_ready count=%d", timeout);
1740                         return 1;
1741                 }
1742
1743                 alive_sleep(1);
1744         } while (timeout-- > 0);
1745
1746         return 0;
1747 }
1748
1749 COMMAND_HANDLER(handle_lpc32xx_select_command)
1750 {
1751         struct lpc32xx_nand_controller *lpc32xx_info = NULL;
1752         char *selected[] = {
1753                 "no", "mlc", "slc"
1754         };
1755
1756         if ((CMD_ARGC < 1) || (CMD_ARGC > 3))
1757                 return ERROR_COMMAND_SYNTAX_ERROR;
1758
1759         unsigned num;
1760         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
1761         struct nand_device *nand = get_nand_device_by_num(num);
1762         if (!nand) {
1763                 command_print(CMD_CTX, "nand device '#%s' is out of bounds",
1764                         CMD_ARGV[0]);
1765                 return ERROR_OK;
1766         }
1767
1768         lpc32xx_info = nand->controller_priv;
1769
1770         if (CMD_ARGC >= 2) {
1771                 if (strcmp(CMD_ARGV[1], "mlc") == 0) {
1772                         lpc32xx_info->selected_controller =
1773                                 LPC32xx_MLC_CONTROLLER;
1774                 } else if (strcmp(CMD_ARGV[1], "slc") == 0) {
1775                         lpc32xx_info->selected_controller =
1776                                 LPC32xx_SLC_CONTROLLER;
1777                 } else
1778                         return ERROR_COMMAND_SYNTAX_ERROR;
1779         }
1780
1781         command_print(CMD_CTX, "%s controller selected",
1782                 selected[lpc32xx_info->selected_controller]);
1783
1784         return ERROR_OK;
1785 }
1786
1787 static const struct command_registration lpc32xx_exec_command_handlers[] = {
1788         {
1789                 .name = "select",
1790                 .handler = handle_lpc32xx_select_command,
1791                 .mode = COMMAND_EXEC,
1792                 .help = "select MLC or SLC controller (default is MLC)",
1793                 .usage = "bank_id ['mlc'|'slc' ]",
1794         },
1795         COMMAND_REGISTRATION_DONE
1796 };
1797 static const struct command_registration lpc32xx_command_handler[] = {
1798         {
1799                 .name = "lpc32xx",
1800                 .mode = COMMAND_ANY,
1801                 .help = "LPC32xx NAND flash controller commands",
1802                 .usage = "",
1803                 .chain = lpc32xx_exec_command_handlers,
1804         },
1805         COMMAND_REGISTRATION_DONE
1806 };
1807
1808 struct nand_flash_controller lpc32xx_nand_controller = {
1809         .name = "lpc32xx",
1810         .commands = lpc32xx_command_handler,
1811         .nand_device_command = lpc32xx_nand_device_command,
1812         .init = lpc32xx_init,
1813         .reset = lpc32xx_reset,
1814         .command = lpc32xx_command,
1815         .address = lpc32xx_address,
1816         .write_data = lpc32xx_write_data,
1817         .read_data = lpc32xx_read_data,
1818         .write_page = lpc32xx_write_page,
1819         .read_page = lpc32xx_read_page,
1820         .nand_ready = lpc32xx_nand_ready,
1821 };