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   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *
   5  *   Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com>                *
   6  *   Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com>            *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "imp.h"
  29 #include "lpc3180.h"
  30 #include <target/target.h>
  31
  32 static int lpc3180_reset(struct nand_device *nand);
  33 static int lpc3180_controller_ready(struct nand_device *nand, int timeout);
  34 static int lpc3180_tc_ready(struct nand_device *nand, int timeout);
  35
  36 #define ECC_OFFS   0x120
  37 #define SPARE_OFFS 0x140
  38 #define DATA_OFFS   0x200
  39
  40 /* nand device lpc3180 <target#> <oscillator_frequency>
  41  */
  42 NAND_DEVICE_COMMAND_HANDLER(lpc3180_nand_device_command)
  43 {
  44         if (CMD_ARGC < 3)
  45                 return ERROR_COMMAND_SYNTAX_ERROR;
  46
  47         uint32_t osc_freq;
  48         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
  49
  50         struct lpc3180_nand_controller *lpc3180_info;
  51         lpc3180_info = malloc(sizeof(struct lpc3180_nand_controller));
  52         nand->controller_priv = lpc3180_info;
  53
  54         lpc3180_info->osc_freq = osc_freq;
  55
  56         if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
  57                 LOG_WARNING(
  58                         "LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i",
  59                         lpc3180_info->osc_freq);
  60         lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
  61         lpc3180_info->sw_write_protection = 0;
  62         lpc3180_info->sw_wp_lower_bound = 0x0;
  63         lpc3180_info->sw_wp_upper_bound = 0x0;
  64
  65         return ERROR_OK;
  66 }
  67
  68 static int lpc3180_pll(int fclkin, uint32_t pll_ctrl)
  69 {
  70         int bypass = (pll_ctrl & 0x8000) >> 15;
  71         int direct = (pll_ctrl & 0x4000) >> 14;
  72         int feedback = (pll_ctrl & 0x2000) >> 13;
  73         int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
  74         int n = ((pll_ctrl & 0x0600) >> 9) + 1;
  75         int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
  76         int lock = (pll_ctrl & 0x1);
  77
  78         if (!lock)
  79                 LOG_WARNING("PLL is not locked");
  80
  81         if (!bypass && direct)  /* direct mode */
  82                 return (m * fclkin) / n;
  83
  84         if (bypass && !direct)  /* bypass mode */
  85                 return fclkin / (2 * p);
  86
  87         if (bypass & direct)    /* direct bypass mode */
  88                 return fclkin;
  89
  90         if (feedback)                   /* integer mode */
  91                 return m * (fclkin / n);
  92         else                                    /* non-integer mode */
  93                 return (m / (2 * p)) * (fclkin / n);
  94 }
  95
  96 static float lpc3180_cycle_time(struct nand_device *nand)
  97 {
  98         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
  99         struct target *target = nand->target;
 100         uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
 101         int sysclk;
 102         int hclk;
 103         int hclk_pll;
 104         float cycle;
 105
 106         /* calculate timings */
 107
 108         /* determine current SYSCLK (13'MHz or main oscillator) */
 109         target_read_u32(target, 0x40004050, &sysclk_ctrl);
 110
 111         if ((sysclk_ctrl & 1) == 0)
 112                 sysclk = lpc3180_info->osc_freq;
 113         else
 114                 sysclk = 13000;
 115
 116         /* determine selected HCLK source */
 117         target_read_u32(target, 0x40004044, &pwr_ctrl);
 118
 119         if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
 120                 hclk = sysclk;
 121         else {
 122                 target_read_u32(target, 0x40004058, &hclkpll_ctrl);
 123                 hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
 124
 125                 target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
 126
 127                 if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
 128                         hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
 129                 else /* HCLK uses HCLK_PLL */
 130                         hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
 131         }
 132
 133         LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
 134
 135         cycle = (1.0 / hclk) * 1000000.0;
 136
 137         return cycle;
 138 }
 139
 140 static int lpc3180_init(struct nand_device *nand)
 141 {
 142         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 143         struct target *target = nand->target;
 144         int bus_width = nand->bus_width ? : 8;
 145         int address_cycles = nand->address_cycles ? : 3;
 146         int page_size = nand->page_size ? : 512;
 147
 148         if (target->state != TARGET_HALTED) {
 149                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 150                 return ERROR_NAND_OPERATION_FAILED;
 151         }
 152
 153         /* sanitize arguments */
 154         if ((bus_width != 8) && (bus_width != 16)) {
 155                 LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
 156                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 157         }
 158
 159         /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
 160          * would support 16 bit, too, so we just warn about this for now
 161          */
 162         if (bus_width == 16)
 163                 LOG_WARNING("LPC3180 only supports 8 bit bus width");
 164
 165         /* inform calling code about selected bus width */
 166         nand->bus_width = bus_width;
 167
 168         if ((address_cycles != 3) && (address_cycles != 4)) {
 169                 LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
 170                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 171         }
 172
 173         if ((page_size != 512) && (page_size != 2048)) {
 174                 LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
 175                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 176         }
 177
 178         /* select MLC controller if none is currently selected */
 179         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
 180                 LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
 181                 lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
 182         }
 183
 184         if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
 185                 uint32_t mlc_icr_value = 0x0;
 186                 float cycle;
 187                 int twp, twh, trp, treh, trhz, trbwb, tcea;
 188
 189                 /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
 190                 target_write_u32(target, 0x400040c8, 0x22);
 191
 192                 /* MLC_CEH = 0x0 (Force nCE assert) */
 193                 target_write_u32(target, 0x200b804c, 0x0);
 194
 195                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 196                 target_write_u32(target, 0x200b8044, 0xa25e);
 197
 198                 /* MLC_ICR = configuration */
 199                 if (lpc3180_info->sw_write_protection)
 200                         mlc_icr_value |= 0x8;
 201                 if (page_size == 2048)
 202                         mlc_icr_value |= 0x4;
 203                 if (address_cycles == 4)
 204                         mlc_icr_value |= 0x2;
 205                 if (bus_width == 16)
 206                         mlc_icr_value |= 0x1;
 207                 target_write_u32(target, 0x200b8030, mlc_icr_value);
 208
 209                 /* calculate NAND controller timings */
 210                 cycle = lpc3180_cycle_time(nand);
 211
 212                 twp = ((40 / cycle) + 1);
 213                 twh = ((20 / cycle) + 1);
 214                 trp = ((30 / cycle) + 1);
 215                 treh = ((15 / cycle) + 1);
 216                 trhz = ((30 / cycle) + 1);
 217                 trbwb = ((100 / cycle) + 1);
 218                 tcea = ((45 / cycle) + 1);
 219
 220                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 221                 target_write_u32(target, 0x200b8044, 0xa25e);
 222
 223                 /* MLC_TIME_REG */
 224                 target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
 225                         ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
 226                         ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
 227
 228                 lpc3180_reset(nand);
 229         } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
 230                 float cycle;
 231                 int r_setup, r_hold, r_width, r_rdy;
 232                 int w_setup, w_hold, w_width, w_rdy;
 233
 234                 /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
 235                 target_write_u32(target, 0x400040c8, 0x05);
 236
 237                 /* after reset set other registers of SLC so reset calling is here at the begining*/
 238                 lpc3180_reset(nand);
 239
 240                 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled,
 241                  *DMA read from SLC, WIDTH = bus_width) */
 242                 target_write_u32(target, 0x20020014, 0x3e | (bus_width == 16) ? 1 : 0);
 243
 244                 /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
 245                 target_write_u32(target, 0x20020020, 0x03);
 246
 247                 /* DMA configuration
 248                  * DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
 249                 target_write_u32(target, 0x400040e8, 0x01);
 250                 /* DMACConfig = DMA enabled*/
 251                 target_write_u32(target, 0x31000030, 0x01);
 252
 253
 254                 /* calculate NAND controller timings */
 255                 cycle = lpc3180_cycle_time(nand);
 256
 257                 r_setup = w_setup = 0;
 258                 r_hold = w_hold = 10 / cycle;
 259                 r_width = 30 / cycle;
 260                 w_width = 40 / cycle;
 261                 r_rdy = w_rdy = 100 / cycle;
 262
 263                 /* SLC_TAC: SLC timing arcs register */
 264                 target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
 265                         ((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) |  ((w_setup & 0xf) << 16) |
 266                         ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
 267
 268         }
 269
 270         return ERROR_OK;
 271 }
 272
 273 static int lpc3180_reset(struct nand_device *nand)
 274 {
 275         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 276         struct target *target = nand->target;
 277
 278         if (target->state != TARGET_HALTED) {
 279                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 280                 return ERROR_NAND_OPERATION_FAILED;
 281         }
 282
 283         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
 284                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 285                 return ERROR_NAND_OPERATION_FAILED;
 286         } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
 287                 /* MLC_CMD = 0xff (reset controller and NAND device) */
 288                 target_write_u32(target, 0x200b8000, 0xff);
 289
 290                 if (!lpc3180_controller_ready(nand, 100)) {
 291                         LOG_ERROR("LPC3180 NAND controller timed out after reset");
 292                         return ERROR_NAND_OPERATION_TIMEOUT;
 293                 }
 294         } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
 295                 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
 296                 target_write_u32(target, 0x20020010, 0x6);
 297
 298                 if (!lpc3180_controller_ready(nand, 100)) {
 299                         LOG_ERROR("LPC3180 NAND controller timed out after reset");
 300                         return ERROR_NAND_OPERATION_TIMEOUT;
 301                 }
 302         }
 303
 304         return ERROR_OK;
 305 }
 306
 307 static int lpc3180_command(struct nand_device *nand, uint8_t command)
 308 {
 309         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 310         struct target *target = nand->target;
 311
 312         if (target->state != TARGET_HALTED) {
 313                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 314                 return ERROR_NAND_OPERATION_FAILED;
 315         }
 316
 317         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
 318                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 319                 return ERROR_NAND_OPERATION_FAILED;
 320         } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
 321                 /* MLC_CMD = command */
 322                 target_write_u32(target, 0x200b8000, command);
 323         } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
 324                 /* SLC_CMD = command */
 325                 target_write_u32(target, 0x20020008, command);
 326         }
 327
 328         return ERROR_OK;
 329 }
 330
 331 static int lpc3180_address(struct nand_device *nand, uint8_t address)
 332 {
 333         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 334         struct target *target = nand->target;
 335
 336         if (target->state != TARGET_HALTED) {
 337                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 338                 return ERROR_NAND_OPERATION_FAILED;
 339         }
 340
 341         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
 342                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 343                 return ERROR_NAND_OPERATION_FAILED;
 344         } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
 345                 /* MLC_ADDR = address */
 346                 target_write_u32(target, 0x200b8004, address);
 347         } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
 348                 /* SLC_ADDR = address */
 349                 target_write_u32(target, 0x20020004, address);
 350         }
 351
 352         return ERROR_OK;
 353 }
 354
 355 static int lpc3180_write_data(struct nand_device *nand, uint16_t data)
 356 {
 357         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 358         struct target *target = nand->target;
 359
 360         if (target->state != TARGET_HALTED) {
 361                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 362                 return ERROR_NAND_OPERATION_FAILED;
 363         }
 364
 365         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
 366                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 367                 return ERROR_NAND_OPERATION_FAILED;
 368         } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
 369                 /* MLC_DATA = data */
 370                 target_write_u32(target, 0x200b0000, data);
 371         } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
 372                 /* SLC_DATA = data */
 373                 target_write_u32(target, 0x20020000, data);
 374         }
 375
 376         return ERROR_OK;
 377 }
 378
 379 static int lpc3180_read_data(struct nand_device *nand, void *data)
 380 {
 381         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 382         struct target *target = nand->target;
 383
 384         if (target->state != TARGET_HALTED) {
 385                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 386                 return ERROR_NAND_OPERATION_FAILED;
 387         }
 388
 389         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
 390                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 391                 return ERROR_NAND_OPERATION_FAILED;
 392         } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
 393                 /* data = MLC_DATA, use sized access */
 394                 if (nand->bus_width == 8) {
 395                         uint8_t *data8 = data;
 396                         target_read_u8(target, 0x200b0000, data8);
 397                 } else if (nand->bus_width == 16) {
 398                         uint16_t *data16 = data;
 399                         target_read_u16(target, 0x200b0000, data16);
 400                 } else {
 401                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 402                         return ERROR_NAND_OPERATION_FAILED;
 403                 }
 404         } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
 405                 uint32_t data32;
 406
 407                 /* data = SLC_DATA, must use 32-bit access */
 408                 target_read_u32(target, 0x20020000, &data32);
 409
 410                 if (nand->bus_width == 8) {
 411                         uint8_t *data8 = data;
 412                         *data8 = data32 & 0xff;
 413                 } else if (nand->bus_width == 16) {
 414                         uint16_t *data16 = data;
 415                         *data16 = data32 & 0xffff;
 416                 } else {
 417                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 418                         return ERROR_NAND_OPERATION_FAILED;
 419                 }
 420         }
 421
 422         return ERROR_OK;
 423 }
 424
 425 static int lpc3180_write_page(struct nand_device *nand,
 426         uint32_t page,
 427         uint8_t *data,
 428         uint32_t data_size,
 429         uint8_t *oob,
 430         uint32_t oob_size)
 431 {
 432         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 433         struct target *target = nand->target;
 434         int retval;
 435         uint8_t status;
 436         uint8_t *page_buffer;
 437
 438         if (target->state != TARGET_HALTED) {
 439                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 440                 return ERROR_NAND_OPERATION_FAILED;
 441         }
 442
 443         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
 444                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 445                 return ERROR_NAND_OPERATION_FAILED;
 446         } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
 447                 uint8_t *oob_buffer;
 448                 int quarter, num_quarters;
 449
 450                 if (!data && oob) {
 451                         LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
 452                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 453                 }
 454
 455                 if (oob && (oob_size > 24)) {
 456                         LOG_ERROR("LPC3180 MLC controller can't write more "
 457                                 "than 6 bytes for each quarter's OOB data");
 458                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 459                 }
 460
 461                 if (data_size > (uint32_t)nand->page_size) {
 462                         LOG_ERROR("data size exceeds page size");
 463                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 464                 }
 465
 466                 /* MLC_CMD = sequential input */
 467                 target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
 468
 469                 page_buffer = malloc(512);
 470                 oob_buffer = malloc(6);
 471
 472                 if (nand->page_size == 512) {
 473                         /* MLC_ADDR = 0x0 (one column cycle) */
 474                         target_write_u32(target, 0x200b8004, 0x0);
 475
 476                         /* MLC_ADDR = row */
 477                         target_write_u32(target, 0x200b8004, page & 0xff);
 478                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 479
 480                         if (nand->address_cycles == 4)
 481                                 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
 482                 } else {
 483                         /* MLC_ADDR = 0x0 (two column cycles) */
 484                         target_write_u32(target, 0x200b8004, 0x0);
 485                         target_write_u32(target, 0x200b8004, 0x0);
 486
 487                         /* MLC_ADDR = row */
 488                         target_write_u32(target, 0x200b8004, page & 0xff);
 489                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 490                 }
 491
 492                 /* when using the MLC controller, we have to treat a large page device
 493                  * as being made out of four quarters, each the size of a small page device
 494                  */
 495                 num_quarters = (nand->page_size == 2048) ? 4 : 1;
 496
 497                 for (quarter = 0; quarter < num_quarters; quarter++) {
 498                         int thisrun_data_size = (data_size > 512) ? 512 : data_size;
 499                         int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
 500
 501                         memset(page_buffer, 0xff, 512);
 502                         if (data) {
 503                                 memcpy(page_buffer, data, thisrun_data_size);
 504                                 data_size -= thisrun_data_size;
 505                                 data += thisrun_data_size;
 506                         }
 507
 508                         memset(oob_buffer, 0xff, 6);
 509                         if (oob) {
 510                                 memcpy(oob_buffer, oob, thisrun_oob_size);
 511                                 oob_size -= thisrun_oob_size;
 512                                 oob += thisrun_oob_size;
 513                         }
 514
 515                         /* write MLC_ECC_ENC_REG to start encode cycle */
 516                         target_write_u32(target, 0x200b8008, 0x0);
 517
 518                         target_write_memory(target, 0x200a8000,
 519                                 4, 128, page_buffer);
 520                         target_write_memory(target, 0x200a8000,
 521                                 1, 6, oob_buffer);
 522
 523                         /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
 524                         target_write_u32(target, 0x200b8010, 0x0);
 525
 526                         if (!lpc3180_controller_ready(nand, 1000)) {
 527                                 LOG_ERROR(
 528                                         "timeout while waiting for completion of auto encode cycle");
 529                                 return ERROR_NAND_OPERATION_FAILED;
 530                         }
 531                 }
 532
 533                 /* MLC_CMD = auto program command */
 534                 target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
 535
 536                 retval = nand_read_status(nand, &status);
 537                 if (retval != ERROR_OK) {
 538                         LOG_ERROR("couldn't read status");
 539                         return ERROR_NAND_OPERATION_FAILED;
 540                 }
 541
 542                 if (status & NAND_STATUS_FAIL) {
 543                         LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
 544                         return ERROR_NAND_OPERATION_FAILED;
 545                 }
 546
 547                 free(page_buffer);
 548                 free(oob_buffer);
 549         } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
 550
 551                 /**********************************************************************
 552                 *     Write both SLC NAND flash page main area and spare area.
 553                 *     Small page -
 554                 *      ------------------------------------------
 555                 *     |    512 bytes main   |   16 bytes spare   |
 556                 *      ------------------------------------------
 557                 *     Large page -
 558                 *      ------------------------------------------
 559                 *     |   2048 bytes main   |   64 bytes spare   |
 560                 *      ------------------------------------------
 561                 *     If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
 562                 *     data is written to the 3rd word of the spare area. The ECC
 563                 *     generated for the 2nd 256-byte data is written to the 4th word
 564                 *     of the spare area. The ECC generated for the 3rd 256-byte data is
 565                 *     written to the 7th word of the spare area. The ECC generated
 566                 *     for the 4th 256-byte data is written to the 8th word of the
 567                 *     spare area and so on.
 568                 *
 569                 **********************************************************************/
 570
 571                 int i = 0, target_mem_base;
 572                 uint8_t *ecc_flash_buffer;
 573                 struct working_area *pworking_area;
 574
 575                 if (lpc3180_info->is_bulk) {
 576
 577                         if (!data && oob) {
 578                                 /*if oob only mode is active original method is used as SLC
 579                                  *controller hangs during DMA interworking. Anyway the code supports
 580                                  *the oob only mode below. */
 581                                 return nand_write_page_raw(nand,
 582                                         page,
 583                                         data,
 584                                         data_size,
 585                                         oob,
 586                                         oob_size);
 587                         }
 588                         retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
 589                         if (ERROR_OK != retval)
 590                                 return retval;
 591
 592                         /* allocate a working area */
 593                         if (target->working_area_size < (uint32_t) nand->page_size + 0x200) {
 594                                 LOG_ERROR("Reserve at least 0x%x physical target working area",
 595                                         nand->page_size + 0x200);
 596                                 return ERROR_FLASH_OPERATION_FAILED;
 597                         }
 598                         if (target->working_area_phys%4) {
 599                                 LOG_ERROR(
 600                                         "Reserve the physical target working area at word boundary");
 601                                 return ERROR_FLASH_OPERATION_FAILED;
 602                         }
 603                         if (target_alloc_working_area(target, target->working_area_size,
 604                                     &pworking_area) != ERROR_OK) {
 605                                 LOG_ERROR("no working area specified, can't read LPC internal flash");
 606                                 return ERROR_FLASH_OPERATION_FAILED;
 607                         }
 608                         target_mem_base = target->working_area_phys;
 609
 610                         if (nand->page_size == 2048)
 611                                 page_buffer = malloc(2048);
 612                         else
 613                                 page_buffer = malloc(512);
 614
 615                         ecc_flash_buffer = malloc(64);
 616
 617                         /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst
 618                          *enabled, DMA write to SLC, WIDTH = bus_width) */
 619                         target_write_u32(target, 0x20020014, 0x3c);
 620
 621                         if (data && !oob) {
 622                                 /* set DMA LLI-s in target memory and in DMA*/
 623                                 for (i = 0; i < nand->page_size/0x100; i++) {
 624
 625                                         int tmp;
 626                                         /* -------LLI for 256 byte block---------
 627                                          * DMACC0SrcAddr = SRAM */
 628                                         target_write_u32(target,
 629                                                 target_mem_base+0+i*32,
 630                                                 target_mem_base+DATA_OFFS+i*256);
 631                                         if (i == 0)
 632                                                 target_write_u32(target,
 633                                                         0x31000100,
 634                                                         target_mem_base+DATA_OFFS);
 635                                         /* DMACCxDestAddr = SLC_DMA_DATA */
 636                                         target_write_u32(target, target_mem_base+4+i*32, 0x20020038);
 637                                         if (i == 0)
 638                                                 target_write_u32(target, 0x31000104, 0x20020038);
 639                                         /* DMACCxLLI = next element */
 640                                         tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
 641                                         target_write_u32(target, target_mem_base+8+i*32, tmp);
 642                                         if (i == 0)
 643                                                 target_write_u32(target, 0x31000108, tmp);
 644                                         /* DMACCxControl =  TransferSize =64, Source burst size =16,
 645                                          * Destination burst size = 16, Source transfer width = 32 bit,
 646                                          * Destination transfer width = 32 bit, Source AHB master select = M0,
 647                                          * Destination AHB master select = M0, Source increment = 1,
 648                                          * Destination increment = 0, Terminal count interrupt enable bit = 0*/
 649                                         target_write_u32(target,
 650                                                 target_mem_base+12+i*32,
 651                                                 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
 652                                                 0<<27 | 0<<31);
 653                                         if (i == 0)
 654                                                 target_write_u32(target,
 655                                                         0x3100010c,
 656                                                         0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
 657                                                         0<<27 | 0<<31);
 658
 659                                         /* -------LLI for 3 byte ECC---------
 660                                          * DMACC0SrcAddr = SLC_ECC*/
 661                                         target_write_u32(target, target_mem_base+16+i*32, 0x20020034);
 662                                         /* DMACCxDestAddr = SRAM */
 663                                         target_write_u32(target,
 664                                                 target_mem_base+20+i*32,
 665                                                 target_mem_base+SPARE_OFFS+8+16*(i>>1)+(i%2)*4);
 666                                         /* DMACCxLLI = next element */
 667                                         tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
 668                                         target_write_u32(target, target_mem_base+24+i*32, tmp);
 669                                         /* DMACCxControl =  TransferSize =1, Source burst size =4,
 670                                          * Destination burst size = 4, Source transfer width = 32 bit,
 671                                          * Destination transfer width = 32 bit, Source AHB master select = M0,
 672                                          * Destination AHB master select = M0, Source increment = 0,
 673                                          * Destination increment = 1, Terminal count interrupt enable bit = 0*/
 674                                         target_write_u32(target,
 675                                                 target_mem_base+28+i*32,
 676                                                 0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
 677                                                 31);
 678                                 }
 679                         } else if (data && oob) {
 680                                 /* -------LLI for 512 or 2048 bytes page---------
 681                                  * DMACC0SrcAddr = SRAM */
 682                                 target_write_u32(target, target_mem_base, target_mem_base+DATA_OFFS);
 683                                 target_write_u32(target, 0x31000100, target_mem_base+DATA_OFFS);
 684                                 /* DMACCxDestAddr = SLC_DMA_DATA */
 685                                 target_write_u32(target, target_mem_base+4, 0x20020038);
 686                                 target_write_u32(target, 0x31000104, 0x20020038);
 687                                 /* DMACCxLLI = next element */
 688                                 target_write_u32(target,
 689                                         target_mem_base+8,
 690                                         (target_mem_base+32)&0xfffffffc);
 691                                 target_write_u32(target, 0x31000108,
 692                                         (target_mem_base+32)&0xfffffffc);
 693                                 /* DMACCxControl =  TransferSize =512 or 128, Source burst size =16,
 694                                  * Destination burst size = 16, Source transfer width = 32 bit,
 695                                  * Destination transfer width = 32 bit, Source AHB master select = M0,
 696                                  * Destination AHB master select = M0, Source increment = 1,
 697                                  * Destination increment = 0, Terminal count interrupt enable bit = 0*/
 698                                 target_write_u32(target,
 699                                         target_mem_base+12,
 700                                         (nand->page_size ==
 701                                  2048 ? 512 : 128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 |
 702                                  1<<26 | 0<<27 | 0<<31);
 703                                 target_write_u32(target,
 704                                         0x3100010c,
 705                                         (nand->page_size ==
 706                                  2048 ? 512 : 128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 |
 707                                  1<<26 | 0<<27 | 0<<31);
 708                                 i = 1;
 709                         } else if (!data && oob)
 710                                 i = 0;
 711
 712                         /* -------LLI for spare area---------
 713                          * DMACC0SrcAddr = SRAM*/
 714                         target_write_u32(target, target_mem_base+0+i*32, target_mem_base+SPARE_OFFS);
 715                         if (i == 0)
 716                                 target_write_u32(target, 0x31000100, target_mem_base+SPARE_OFFS);
 717                         /* DMACCxDestAddr = SLC_DMA_DATA */
 718                         target_write_u32(target, target_mem_base+4+i*32, 0x20020038);
 719                         if (i == 0)
 720                                 target_write_u32(target, 0x31000104, 0x20020038);
 721                         /* DMACCxLLI = next element = NULL */
 722                         target_write_u32(target, target_mem_base+8+i*32, 0);
 723                         if (i == 0)
 724                                 target_write_u32(target, 0x31000108, 0);
 725                         /* DMACCxControl =  TransferSize =16 for large page or 4 for small page,
 726                          * Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
 727                          * Destination transfer width = 32 bit, Source AHB master select = M0,
 728                          * Destination AHB master select = M0, Source increment = 1,
 729                          * Destination increment = 0, Terminal count interrupt enable bit = 0*/
 730                         target_write_u32(target,
 731                                 target_mem_base+12+i*32,
 732                                 (nand->page_size ==
 733                          2048 ? 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
 734                          0<<27 | 0<<31);
 735                         if (i == 0)
 736                                 target_write_u32(target, 0x3100010c,
 737                                         (nand->page_size == 2048 ?
 738                                         0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 |
 739                                         0<<25 | 1<<26 | 0<<27 | 0<<31);
 740
 741                         memset(ecc_flash_buffer, 0xff, 64);
 742                         if (oob)
 743                                 memcpy(ecc_flash_buffer, oob, oob_size);
 744                         target_write_memory(target,
 745                                 target_mem_base+SPARE_OFFS,
 746                                 4,
 747                                 16,
 748                                 ecc_flash_buffer);
 749
 750                         if (data) {
 751                                 memset(page_buffer, 0xff, nand->page_size == 2048 ? 2048 : 512);
 752                                 memcpy(page_buffer, data, data_size);
 753                                 target_write_memory(target,
 754                                         target_mem_base+DATA_OFFS,
 755                                         4,
 756                                         nand->page_size == 2048 ? 512 : 128,
 757                                         page_buffer);
 758                         }
 759
 760                         free(page_buffer);
 761                         free(ecc_flash_buffer);
 762
 763                         /* Enable DMA after channel set up !
 764                             LLI only works when DMA is the flow controller!
 765                         */
 766                         /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC),
 767                          *FlowCntrl = 2 (Pher -> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
 768                         target_write_u32(target,
 769                                 0x31000110,
 770                                 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
 771
 772                         /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
 773                         target_write_u32(target, 0x20020010, 0x3);
 774
 775                         /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
 776                         target_write_u32(target, 0x20020028, 2);
 777
 778                         /* SLC_TC */
 779                         if (!data && oob)
 780                                 target_write_u32(target, 0x20020030,
 781                                         (nand->page_size == 2048 ? 0x10 : 0x04));
 782                         else
 783                                 target_write_u32(target, 0x20020030,
 784                                         (nand->page_size == 2048 ? 0x840 : 0x210));
 785
 786                         nand_write_finish(nand);
 787
 788                         if (!lpc3180_tc_ready(nand, 1000)) {
 789                                 LOG_ERROR("timeout while waiting for completion of DMA");
 790                                 return ERROR_NAND_OPERATION_FAILED;
 791                         }
 792
 793                         target_free_working_area(target, pworking_area);
 794
 795                         LOG_INFO("Page =  0x%" PRIx32 " was written.", page);
 796
 797                 } else
 798                         return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
 799         }
 800
 801         return ERROR_OK;
 802 }
 803
 804 static int lpc3180_read_page(struct nand_device *nand,
 805         uint32_t page,
 806         uint8_t *data,
 807         uint32_t data_size,
 808         uint8_t *oob,
 809         uint32_t oob_size)
 810 {
 811         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 812         struct target *target = nand->target;
 813         uint8_t *page_buffer;
 814
 815         if (target->state != TARGET_HALTED) {
 816                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 817                 return ERROR_NAND_OPERATION_FAILED;
 818         }
 819
 820         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
 821                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 822                 return ERROR_NAND_OPERATION_FAILED;
 823         } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
 824                 uint8_t *oob_buffer;
 825                 uint32_t page_bytes_done = 0;
 826                 uint32_t oob_bytes_done = 0;
 827                 uint32_t mlc_isr;
 828
 829 #if 0
 830                 if (oob && (oob_size > 6)) {
 831                         LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
 832                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 833                 }
 834 #endif
 835
 836                 if (data_size > (uint32_t)nand->page_size) {
 837                         LOG_ERROR("data size exceeds page size");
 838                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 839                 }
 840
 841                 if (nand->page_size == 2048) {
 842                         page_buffer = malloc(2048);
 843                         oob_buffer = malloc(64);
 844                 } else {
 845                         page_buffer = malloc(512);
 846                         oob_buffer = malloc(16);
 847                 }
 848
 849                 if (!data && oob) {
 850                         /* MLC_CMD = Read OOB
 851                          * we can use the READOOB command on both small and large page devices,
 852                          * as the controller translates the 0x50 command to a 0x0 with appropriate
 853                          * positioning of the serial buffer read pointer
 854                          */
 855                         target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
 856                 } else {
 857                         /* MLC_CMD = Read0 */
 858                         target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
 859                 }
 860
 861                 if (nand->page_size == 512) {
 862                         /* small page device
 863                          * MLC_ADDR = 0x0 (one column cycle) */
 864                         target_write_u32(target, 0x200b8004, 0x0);
 865
 866                         /* MLC_ADDR = row */
 867                         target_write_u32(target, 0x200b8004, page & 0xff);
 868                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 869
 870                         if (nand->address_cycles == 4)
 871                                 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
 872                 } else {
 873                         /* large page device
 874                          * MLC_ADDR = 0x0 (two column cycles) */
 875                         target_write_u32(target, 0x200b8004, 0x0);
 876                         target_write_u32(target, 0x200b8004, 0x0);
 877
 878                         /* MLC_ADDR = row */
 879                         target_write_u32(target, 0x200b8004, page & 0xff);
 880                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 881
 882                         /* MLC_CMD = Read Start */
 883                         target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
 884                 }
 885
 886                 while (page_bytes_done < (uint32_t)nand->page_size) {
 887                         /* MLC_ECC_AUTO_DEC_REG = dummy */
 888                         target_write_u32(target, 0x200b8014, 0xaa55aa55);
 889
 890                         if (!lpc3180_controller_ready(nand, 1000)) {
 891                                 LOG_ERROR(
 892                                         "timeout while waiting for completion of auto decode cycle");
 893                                 return ERROR_NAND_OPERATION_FAILED;
 894                         }
 895
 896                         target_read_u32(target, 0x200b8048, &mlc_isr);
 897
 898                         if (mlc_isr & 0x8) {
 899                                 if (mlc_isr & 0x40) {
 900                                         LOG_ERROR("uncorrectable error detected: 0x%2.2x",
 901                                                 (unsigned)mlc_isr);
 902                                         return ERROR_NAND_OPERATION_FAILED;
 903                                 }
 904
 905                                 LOG_WARNING("%i symbol error detected and corrected",
 906                                         ((int)(((mlc_isr & 0x30) >> 4) + 1)));
 907                         }
 908
 909                         if (data)
 910                                 target_read_memory(target,
 911                                         0x200a8000,
 912                                         4,
 913                                         128,
 914                                         page_buffer + page_bytes_done);
 915
 916                         if (oob)
 917                                 target_read_memory(target,
 918                                         0x200a8000,
 919                                         4,
 920                                         4,
 921                                         oob_buffer + oob_bytes_done);
 922
 923                         page_bytes_done += 512;
 924                         oob_bytes_done += 16;
 925                 }
 926
 927                 if (data)
 928                         memcpy(data, page_buffer, data_size);
 929
 930                 if (oob)
 931                         memcpy(oob, oob_buffer, oob_size);
 932
 933                 free(page_buffer);
 934                 free(oob_buffer);
 935         } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
 936
 937                 /**********************************************************************
 938                 *     Read both SLC NAND flash page main area and spare area.
 939                 *     Small page -
 940                 *      ------------------------------------------
 941                 *     |    512 bytes main   |   16 bytes spare   |
 942                 *      ------------------------------------------
 943                 *     Large page -
 944                 *      ------------------------------------------
 945                 *     |   2048 bytes main   |   64 bytes spare   |
 946                 *      ------------------------------------------
 947                 *     If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
 948                 *     data is compared with the 3rd word of the spare area. The ECC
 949                 *     generated for the 2nd 256-byte data is compared with the 4th word
 950                 *     of the spare area. The ECC generated for the 3rd 256-byte data is
 951                 *     compared with the 7th word of the spare area. The ECC generated
 952                 *     for the 4th 256-byte data is compared with the 8th word of the
 953                 *     spare area and so on.
 954                 *
 955                 **********************************************************************/
 956
 957                 int retval, i, target_mem_base;
 958                 uint8_t *ecc_hw_buffer;
 959                 uint8_t *ecc_flash_buffer;
 960                 struct working_area *pworking_area;
 961
 962                 if (lpc3180_info->is_bulk) {
 963
 964                         /* read always the data and also oob areas*/
 965
 966                         retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
 967                         if (ERROR_OK != retval)
 968                                 return retval;
 969
 970                         /* allocate a working area */
 971                         if (target->working_area_size < (uint32_t) nand->page_size + 0x200) {
 972                                 LOG_ERROR("Reserve at least 0x%x physical target working area",
 973                                         nand->page_size + 0x200);
 974                                 return ERROR_FLASH_OPERATION_FAILED;
 975                         }
 976                         if (target->working_area_phys%4) {
 977                                 LOG_ERROR(
 978                                         "Reserve the physical target working area at word boundary");
 979                                 return ERROR_FLASH_OPERATION_FAILED;
 980                         }
 981                         if (target_alloc_working_area(target, target->working_area_size,
 982                                     &pworking_area) != ERROR_OK) {
 983                                 LOG_ERROR("no working area specified, can't read LPC internal flash");
 984                                 return ERROR_FLASH_OPERATION_FAILED;
 985                         }
 986                         target_mem_base = target->working_area_phys;
 987
 988                         if (nand->page_size == 2048)
 989                                 page_buffer = malloc(2048);
 990                         else
 991                                 page_buffer = malloc(512);
 992
 993                         ecc_hw_buffer = malloc(32);
 994                         ecc_flash_buffer = malloc(64);
 995
 996                         /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst
 997                          *enabled, DMA read from SLC, WIDTH = bus_width) */
 998                         target_write_u32(target, 0x20020014, 0x3e);
 999
1000                         /* set DMA LLI-s in target memory and in DMA*/
1001                         for (i = 0; i < nand->page_size/0x100; i++) {
1002                                 int tmp;
1003                                 /* -------LLI for 256 byte block---------
1004                                  * DMACC0SrcAddr = SLC_DMA_DATA*/
1005                                 target_write_u32(target, target_mem_base+0+i*32, 0x20020038);
1006                                 if (i == 0)
1007                                         target_write_u32(target, 0x31000100, 0x20020038);
1008                                 /* DMACCxDestAddr = SRAM */
1009                                 target_write_u32(target,
1010                                         target_mem_base+4+i*32,
1011                                         target_mem_base+DATA_OFFS+i*256);
1012                                 if (i == 0)
1013                                         target_write_u32(target,
1014                                                 0x31000104,
1015                                                 target_mem_base+DATA_OFFS);
1016                                 /* DMACCxLLI = next element */
1017                                 tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
1018                                 target_write_u32(target, target_mem_base+8+i*32, tmp);
1019                                 if (i == 0)
1020                                         target_write_u32(target, 0x31000108, tmp);
1021                                 /* DMACCxControl =  TransferSize =64, Source burst size =16,
1022                                  * Destination burst size = 16, Source transfer width = 32 bit,
1023                                  * Destination transfer width = 32 bit, Source AHB master select = M0,
1024                                  * Destination AHB master select = M0, Source increment = 0,
1025                                  * Destination increment = 1, Terminal count interrupt enable bit = 0*/
1026                                 target_write_u32(target,
1027                                         target_mem_base+12+i*32,
1028                                         0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
1029                                         31);
1030                                 if (i == 0)
1031                                         target_write_u32(target,
1032                                                 0x3100010c,
1033                                                 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
1034                                                 31);
1035
1036                                 /* -------LLI for 3 byte ECC---------
1037                                  * DMACC0SrcAddr = SLC_ECC*/
1038                                 target_write_u32(target, target_mem_base+16+i*32, 0x20020034);
1039                                 /* DMACCxDestAddr = SRAM */
1040                                 target_write_u32(target,
1041                                         target_mem_base+20+i*32,
1042                                         target_mem_base+ECC_OFFS+i*4);
1043                                 /* DMACCxLLI = next element */
1044                                 tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
1045                                 target_write_u32(target, target_mem_base+24+i*32, tmp);
1046                                 /* DMACCxControl =  TransferSize =1, Source burst size =4,
1047                                  * Destination burst size = 4, Source transfer width = 32 bit,
1048                                  * Destination transfer width = 32 bit, Source AHB master select = M0,
1049                                  * Destination AHB master select = M0, Source increment = 0,
1050                                  * Destination increment = 1, Terminal count interrupt enable bit = 0*/
1051                                 target_write_u32(target,
1052                                         target_mem_base+28+i*32,
1053                                         0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
1054                                         31);
1055                         }
1056
1057                         /* -------LLI for spare area---------
1058                          * DMACC0SrcAddr = SLC_DMA_DATA*/
1059                         target_write_u32(target, target_mem_base+0+i*32, 0x20020038);
1060                         /* DMACCxDestAddr = SRAM */
1061                         target_write_u32(target, target_mem_base+4+i*32, target_mem_base+SPARE_OFFS);
1062                         /* DMACCxLLI = next element = NULL */
1063                         target_write_u32(target, target_mem_base+8+i*32, 0);
1064                         /* DMACCxControl =  TransferSize =16 for large page or 4 for small page,
1065                          * Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
1066                          * Destination transfer width = 32 bit, Source AHB master select = M0,
1067                          * Destination AHB master select = M0, Source increment = 0,
1068                          * Destination increment = 1, Terminal count interrupt enable bit = 0*/
1069                         target_write_u32(target,
1070                                 target_mem_base + 12 + i * 32,
1071                                 (nand->page_size == 2048 ? 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 |
1072                          0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<31);
1073
1074                         /* Enable DMA after channel set up !
1075                             LLI only works when DMA is the flow controller!
1076                         */
1077                         /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC),
1078                          *FlowCntrl = 2 (Pher-> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
1079                         target_write_u32(target,
1080                                 0x31000110,
1081                                 1 | 1<<1 | 1<<6 |  2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
1082
1083                         /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
1084                         target_write_u32(target, 0x20020010, 0x3);
1085
1086                         /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
1087                         target_write_u32(target, 0x20020028, 2);
1088
1089                         /* SLC_TC */
1090                         target_write_u32(target, 0x20020030,
1091                                 (nand->page_size == 2048 ? 0x840 : 0x210));
1092
1093                         if (!lpc3180_tc_ready(nand, 1000)) {
1094                                 LOG_ERROR("timeout while waiting for completion of DMA");
1095                                 free(page_buffer);
1096                                 free(ecc_hw_buffer);
1097                                 free(ecc_flash_buffer);
1098                                 target_free_working_area(target, pworking_area);
1099                                 return ERROR_NAND_OPERATION_FAILED;
1100                         }
1101
1102                         if (data) {
1103                                 target_read_memory(target,
1104                                         target_mem_base+DATA_OFFS,
1105                                         4,
1106                                         nand->page_size == 2048 ? 512 : 128,
1107                                         page_buffer);
1108                                 memcpy(data, page_buffer, data_size);
1109
1110                                 LOG_INFO("Page =  0x%" PRIx32 " was read.", page);
1111
1112                                 /* check hw generated ECC for each 256 bytes block with the saved
1113                                  *ECC in flash spare area*/
1114                                 int idx = nand->page_size/0x200;
1115                                 target_read_memory(target,
1116                                         target_mem_base+SPARE_OFFS,
1117                                         4,
1118                                         16,
1119                                         ecc_flash_buffer);
1120                                 target_read_memory(target,
1121                                         target_mem_base+ECC_OFFS,
1122                                         4,
1123                                         8,
1124                                         ecc_hw_buffer);
1125                                 for (i = 0; i < idx; i++) {
1126                                         if ((0x00ffffff & *(uint32_t *)(void *)(ecc_hw_buffer+i*8)) !=
1127                                                         (0x00ffffff & *(uint32_t *)(void *)(ecc_flash_buffer+8+i*16)))
1128                                                 LOG_WARNING(
1129                                                         "ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,
1130                                                         i * 2 + 1, page);
1131                                         if ((0x00ffffff & *(uint32_t *)(void *)(ecc_hw_buffer+4+i*8)) !=
1132                                                         (0x00ffffff & *(uint32_t *)(void *)(ecc_flash_buffer+12+i*16)))
1133                                                 LOG_WARNING(
1134                                                         "ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,
1135                                                         i * 2 + 2, page);
1136                                 }
1137                         }
1138
1139                         if (oob)
1140                                 memcpy(oob, ecc_flash_buffer, oob_size);
1141
1142                         free(page_buffer);
1143                         free(ecc_hw_buffer);
1144                         free(ecc_flash_buffer);
1145
1146                         target_free_working_area(target, pworking_area);
1147
1148                 } else
1149                         return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
1150         }
1151
1152         return ERROR_OK;
1153 }
1154
1155 static int lpc3180_controller_ready(struct nand_device *nand, int timeout)
1156 {
1157         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1158         struct target *target = nand->target;
1159
1160         if (target->state != TARGET_HALTED) {
1161                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1162                 return ERROR_NAND_OPERATION_FAILED;
1163         }
1164
1165         LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout);
1166
1167         do {
1168                 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
1169                         uint8_t status;
1170
1171                         /* Read MLC_ISR, wait for controller to become ready */
1172                         target_read_u8(target, 0x200b8048, &status);
1173
1174                         if (status & 2) {
1175                                 LOG_DEBUG("lpc3180_controller_ready count=%d",
1176                                         timeout);
1177                                 return 1;
1178                         }
1179                 } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
1180                         uint32_t status;
1181
1182                         /* Read SLC_STAT and check READY bit */
1183                         target_read_u32(target, 0x20020018, &status);
1184
1185                         if (status & 1) {
1186                                 LOG_DEBUG("lpc3180_controller_ready count=%d",
1187                                         timeout);
1188                                 return 1;
1189                         }
1190                 }
1191
1192                 alive_sleep(1);
1193         } while (timeout-- > 0);
1194
1195         return 0;
1196 }
1197
1198 static int lpc3180_nand_ready(struct nand_device *nand, int timeout)
1199 {
1200         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1201         struct target *target = nand->target;
1202
1203         if (target->state != TARGET_HALTED) {
1204                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1205                 return ERROR_NAND_OPERATION_FAILED;
1206         }
1207
1208         LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout);
1209
1210         do {
1211                 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
1212                         uint8_t status = 0x0;
1213
1214                         /* Read MLC_ISR, wait for NAND flash device to become ready */
1215                         target_read_u8(target, 0x200b8048, &status);
1216
1217                         if (status & 1) {
1218                                 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1219                                         timeout);
1220                                 return 1;
1221                         }
1222                 } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
1223                         uint32_t status = 0x0;
1224
1225                         /* Read SLC_STAT and check READY bit */
1226                         target_read_u32(target, 0x20020018, &status);
1227
1228                         if (status & 1) {
1229                                 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1230                                         timeout);
1231                                 return 1;
1232                         }
1233                 }
1234
1235                 alive_sleep(1);
1236         } while (timeout-- > 0);
1237
1238         return 0;
1239 }
1240
1241 static int lpc3180_tc_ready(struct nand_device *nand, int timeout)
1242 {
1243         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1244         struct target *target = nand->target;
1245
1246         if (target->state != TARGET_HALTED) {
1247                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1248                 return ERROR_NAND_OPERATION_FAILED;
1249         }
1250
1251         LOG_DEBUG("lpc3180_tc_ready count start=%d",
1252                 timeout);
1253
1254         do {
1255                 if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
1256                         uint32_t status = 0x0;
1257                         /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1258                         target_read_u32(target, 0x2002001c, &status);
1259
1260                         if (status & 2) {
1261                                 LOG_DEBUG("lpc3180_tc_ready count=%d",
1262                                         timeout);
1263                                 return 1;
1264                         }
1265                 }
1266
1267                 alive_sleep(1);
1268         } while (timeout-- > 0);
1269
1270         return 0;
1271 }
1272
1273 COMMAND_HANDLER(handle_lpc3180_select_command)
1274 {
1275         struct lpc3180_nand_controller *lpc3180_info = NULL;
1276         char *selected[] = {
1277                 "no", "mlc", "slc"
1278         };
1279
1280         if ((CMD_ARGC < 1) || (CMD_ARGC > 3))
1281                 return ERROR_COMMAND_SYNTAX_ERROR;
1282
1283         unsigned num;
1284         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
1285         struct nand_device *nand = get_nand_device_by_num(num);
1286         if (!nand) {
1287                 command_print(CMD_CTX, "nand device '#%s' is out of bounds", CMD_ARGV[0]);
1288                 return ERROR_OK;
1289         }
1290
1291         lpc3180_info = nand->controller_priv;
1292
1293         if (CMD_ARGC >= 2) {
1294                 if (strcmp(CMD_ARGV[1], "mlc") == 0)
1295                         lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
1296                 else if (strcmp(CMD_ARGV[1], "slc") == 0) {
1297                         lpc3180_info->selected_controller = LPC3180_SLC_CONTROLLER;
1298                         if (CMD_ARGC == 3 && strcmp(CMD_ARGV[2], "bulk") == 0)
1299                                 lpc3180_info->is_bulk = 1;
1300                         else
1301                                 lpc3180_info->is_bulk = 0;
1302                 } else
1303                         return ERROR_COMMAND_SYNTAX_ERROR;
1304         }
1305
1306         if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
1307                 command_print(CMD_CTX, "%s controller selected",
1308                         selected[lpc3180_info->selected_controller]);
1309         else
1310                 command_print(CMD_CTX,
1311                         lpc3180_info->is_bulk ? "%s controller selected bulk mode is available" :
1312                         "%s controller selected bulk mode is not available",
1313                         selected[lpc3180_info->selected_controller]);
1314
1315         return ERROR_OK;
1316 }
1317
1318 static const struct command_registration lpc3180_exec_command_handlers[] = {
1319         {
1320                 .name = "select",
1321                 .handler = handle_lpc3180_select_command,
1322                 .mode = COMMAND_EXEC,
1323                 .help =
1324                         "select MLC or SLC controller (default is MLC), SLC can be set to bulk mode",
1325                 .usage = "bank_id ['mlc'|'slc' ['bulk'] ]",
1326         },
1327         COMMAND_REGISTRATION_DONE
1328 };
1329 static const struct command_registration lpc3180_command_handler[] = {
1330         {
1331                 .name = "lpc3180",
1332                 .mode = COMMAND_ANY,
1333                 .help = "LPC3180 NAND flash controller commands",
1334                 .usage = "",
1335                 .chain = lpc3180_exec_command_handlers,
1336         },
1337         COMMAND_REGISTRATION_DONE
1338 };
1339
1340 struct nand_flash_controller lpc3180_nand_controller = {
1341         .name = "lpc3180",
1342         .commands = lpc3180_command_handler,
1343         .nand_device_command = lpc3180_nand_device_command,
1344         .init = lpc3180_init,
1345         .reset = lpc3180_reset,
1346         .command = lpc3180_command,
1347         .address = lpc3180_address,
1348         .write_data = lpc3180_write_data,
1349         .read_data = lpc3180_read_data,
1350         .write_page = lpc3180_write_page,
1351         .read_page = lpc3180_read_page,
1352         .nand_ready = lpc3180_nand_ready,
1353 };