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   1 /***************************************************************************
   2  *   Copyright (C) 2009 by David Brownell                                  *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19
  20 /*
  21  * DaVinci family NAND controller support for OpenOCD.
  22  *
  23  * This driver uses hardware ECC (1-bit or 4-bit) unless
  24  * the chip is accessed in "raw" mode.
  25  */
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "imp.h"
  32 #include "arm_io.h"
  33 #include <target/target.h>
  34
  35 enum ecc {
  36         HWECC1,         /* all controllers support 1-bit ECC */
  37         HWECC4,         /* newer chips also have 4-bit ECC hardware */
  38         HWECC4_INFIX,   /* avoid this layout, except maybe for boot code */
  39 };
  40
  41 struct davinci_nand {
  42         uint8_t         chipsel;        /* chipselect 0..3 == CS2..CS5 */
  43         uint8_t         eccmode;
  44
  45         /* Async EMIF controller base */
  46         uint32_t                aemif;
  47
  48         /* NAND chip addresses */
  49         uint32_t                data;           /* without CLE or ALE */
  50         uint32_t                cmd;            /* with CLE */
  51         uint32_t                addr;           /* with ALE */
  52
  53         /* write acceleration */
  54         struct arm_nand_data    io;
  55
  56         /* page i/o for the relevant flavor of hardware ECC */
  57         int (*read_page)(struct nand_device *nand, uint32_t page,
  58                         uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
  59         int (*write_page)(struct nand_device *nand, uint32_t page,
  60                         uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
  61 };
  62
  63 #define NANDFCR         0x60            /* flash control register */
  64 #define NANDFSR         0x64            /* flash status register */
  65 #define NANDFECC        0x70            /* 1-bit ECC data, CS0, 1st of 4 */
  66 #define NAND4BITECCLOAD 0xbc            /* 4-bit ECC, load saved values */
  67 #define NAND4BITECC     0xc0            /* 4-bit ECC data, 1st of 4 */
  68 #define NANDERRADDR     0xd0            /* 4-bit ECC err addr, 1st of 2 */
  69 #define NANDERRVAL      0xd8            /* 4-bit ECC err value, 1st of 2 */
  70
  71 static int halted(struct target *target, const char *label)
  72 {
  73         if (target->state == TARGET_HALTED)
  74                 return true;
  75
  76         LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
  77         return false;
  78 }
  79
  80 static int davinci_init(struct nand_device *nand)
  81 {
  82         struct davinci_nand *info = nand->controller_priv;
  83         struct target *target = nand->target;
  84         uint32_t nandfcr;
  85
  86         if (!halted(target, "init"))
  87                 return ERROR_NAND_OPERATION_FAILED;
  88
  89         /* We require something else to have configured AEMIF to talk
  90          * to NAND chip in this range (including timings and width).
  91          */
  92         target_read_u32(target, info->aemif + NANDFCR, &nandfcr);
  93         if (!(nandfcr & (1 << info->chipsel))) {
  94                 LOG_ERROR("chip address %08" PRIx32 " not NAND-enabled?", info->data);
  95                 return ERROR_NAND_OPERATION_FAILED;
  96         }
  97
  98         /* REVISIT verify:  AxCR must be in 8-bit mode, since that's all we
  99          * tested.  16 bit support should work too; but not with 4-bit ECC.
 100          */
 101
 102         return ERROR_OK;
 103 }
 104
 105 static int davinci_reset(struct nand_device *nand)
 106 {
 107         return ERROR_OK;
 108 }
 109
 110 static int davinci_nand_ready(struct nand_device *nand, int timeout)
 111 {
 112         struct davinci_nand *info = nand->controller_priv;
 113         struct target *target = nand->target;
 114         uint32_t nandfsr;
 115
 116         /* NOTE: return code is zero/error, else success; not ERROR_* */
 117
 118         if (!halted(target, "ready"))
 119                 return 0;
 120
 121         do {
 122                 target_read_u32(target, info->aemif + NANDFSR, &nandfsr);
 123
 124                 if (nandfsr & 0x01)
 125                         return 1;
 126
 127                 alive_sleep(1);
 128         } while (timeout-- > 0);
 129
 130         return 0;
 131 }
 132
 133 static int davinci_command(struct nand_device *nand, uint8_t command)
 134 {
 135         struct davinci_nand *info = nand->controller_priv;
 136         struct target *target = nand->target;
 137
 138         if (!halted(target, "command"))
 139                 return ERROR_NAND_OPERATION_FAILED;
 140
 141         target_write_u8(target, info->cmd, command);
 142         return ERROR_OK;
 143 }
 144
 145 static int davinci_address(struct nand_device *nand, uint8_t address)
 146 {
 147         struct davinci_nand *info = nand->controller_priv;
 148         struct target *target = nand->target;
 149
 150         if (!halted(target, "address"))
 151                 return ERROR_NAND_OPERATION_FAILED;
 152
 153         target_write_u8(target, info->addr, address);
 154         return ERROR_OK;
 155 }
 156
 157 static int davinci_write_data(struct nand_device *nand, uint16_t data)
 158 {
 159         struct davinci_nand *info = nand->controller_priv;
 160         struct target *target = nand->target;
 161
 162         if (!halted(target, "write_data"))
 163                 return ERROR_NAND_OPERATION_FAILED;
 164
 165         target_write_u8(target, info->data, data);
 166         return ERROR_OK;
 167 }
 168
 169 static int davinci_read_data(struct nand_device *nand, void *data)
 170 {
 171         struct davinci_nand *info = nand->controller_priv;
 172         struct target *target = nand->target;
 173
 174         if (!halted(target, "read_data"))
 175                 return ERROR_NAND_OPERATION_FAILED;
 176
 177         target_read_u8(target, info->data, data);
 178         return ERROR_OK;
 179 }
 180
 181 /* REVISIT a bit of native code should let block reads be MUCH faster */
 182
 183 static int davinci_read_block_data(struct nand_device *nand,
 184                 uint8_t *data, int data_size)
 185 {
 186         struct davinci_nand *info = nand->controller_priv;
 187         struct target *target = nand->target;
 188         uint32_t nfdata = info->data;
 189         uint32_t tmp;
 190
 191         if (!halted(target, "read_block"))
 192                 return ERROR_NAND_OPERATION_FAILED;
 193
 194         while (data_size >= 4) {
 195                 target_read_u32(target, nfdata, &tmp);
 196
 197                 data[0] = tmp;
 198                 data[1] = tmp >> 8;
 199                 data[2] = tmp >> 16;
 200                 data[3] = tmp >> 24;
 201
 202                 data_size -= 4;
 203                 data += 4;
 204         }
 205
 206         while (data_size > 0) {
 207                 target_read_u8(target, nfdata, data);
 208
 209                 data_size -= 1;
 210                 data += 1;
 211         }
 212
 213         return ERROR_OK;
 214 }
 215
 216 static int davinci_write_block_data(struct nand_device *nand,
 217                 uint8_t *data, int data_size)
 218 {
 219         struct davinci_nand *info = nand->controller_priv;
 220         struct target *target = nand->target;
 221         uint32_t nfdata = info->data;
 222         uint32_t tmp;
 223         int status;
 224
 225         if (!halted(target, "write_block"))
 226                 return ERROR_NAND_OPERATION_FAILED;
 227
 228         /* try the fast way first */
 229         status = arm_nandwrite(&info->io, data, data_size);
 230         if (status != ERROR_NAND_NO_BUFFER)
 231                 return status;
 232
 233         /* else do it slowly */
 234         while (data_size >= 4) {
 235                 tmp = le_to_h_u32(data);
 236                 target_write_u32(target, nfdata, tmp);
 237
 238                 data_size -= 4;
 239                 data += 4;
 240         }
 241
 242         while (data_size > 0) {
 243                 target_write_u8(target, nfdata, *data);
 244
 245                 data_size -= 1;
 246                 data += 1;
 247         }
 248
 249         return ERROR_OK;
 250 }
 251
 252 static int davinci_write_page(struct nand_device *nand, uint32_t page,
 253                 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 254 {
 255         struct davinci_nand *info = nand->controller_priv;
 256         uint8_t *ooballoc = NULL;
 257         int status;
 258
 259         if (!nand->device)
 260                 return ERROR_NAND_DEVICE_NOT_PROBED;
 261         if (!halted(nand->target, "write_page"))
 262                 return ERROR_NAND_OPERATION_FAILED;
 263
 264         /* Always write both data and OOB ... we are not "raw" I/O! */
 265         if (!data) {
 266                 LOG_ERROR("Missing NAND data; try 'nand raw_access enable'");
 267                 return ERROR_NAND_OPERATION_FAILED;
 268         }
 269
 270         /* If we're not given OOB, write 0xff where we don't write ECC codes. */
 271         switch (nand->page_size) {
 272         case 512:
 273                 oob_size = 16;
 274                 break;
 275         case 2048:
 276                 oob_size = 64;
 277                 break;
 278         case 4096:
 279                 oob_size = 128;
 280                 break;
 281         default:
 282                 return ERROR_NAND_OPERATION_FAILED;
 283         }
 284         if (!oob) {
 285                 ooballoc = malloc(oob_size);
 286                 if (!ooballoc)
 287                         return ERROR_NAND_OPERATION_FAILED;
 288                 oob = ooballoc;
 289                 memset(oob, 0x0ff, oob_size);
 290         }
 291
 292         /* REVISIT avoid wasting SRAM:  unless nand->use_raw is set,
 293          * use 512 byte chunks.  Read side support will often want
 294          * to include oob_size ...
 295          */
 296         info->io.chunk_size = nand->page_size;
 297
 298         status = info->write_page(nand, page, data, data_size, oob, oob_size);
 299         free(ooballoc);
 300         return status;
 301 }
 302
 303 static int davinci_read_page(struct nand_device *nand, uint32_t page,
 304                 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 305 {
 306         struct davinci_nand *info = nand->controller_priv;
 307
 308         if (!nand->device)
 309                 return ERROR_NAND_DEVICE_NOT_PROBED;
 310         if (!halted(nand->target, "read_page"))
 311                 return ERROR_NAND_OPERATION_FAILED;
 312
 313         return info->read_page(nand, page, data, data_size, oob, oob_size);
 314 }
 315
 316 static void davinci_write_pagecmd(struct nand_device *nand, uint8_t cmd, uint32_t page)
 317 {
 318         struct davinci_nand *info = nand->controller_priv;
 319         struct target *target = nand->target;
 320         int page3 = nand->address_cycles - (nand->page_size == 512);
 321
 322         /* write command ({page,otp}x{read,program} */
 323         target_write_u8(target, info->cmd, cmd);
 324
 325         /* column address (beginning-of-page) */
 326         target_write_u8(target, info->addr, 0);
 327         if (nand->page_size > 512)
 328                 target_write_u8(target, info->addr, 0);
 329
 330         /* page address */
 331         target_write_u8(target, info->addr, page);
 332         target_write_u8(target, info->addr, page >> 8);
 333         if (page3)
 334                 target_write_u8(target, info->addr, page >> 16);
 335         if (page3 == 2)
 336                 target_write_u8(target, info->addr, page >> 24);
 337 }
 338
 339 static int davinci_seek_column(struct nand_device *nand, uint16_t column)
 340 {
 341         struct davinci_nand *info = nand->controller_priv;
 342         struct target *target = nand->target;
 343
 344         /* Random read, we must have issued a page read already */
 345         target_write_u8(target, info->cmd, NAND_CMD_RNDOUT);
 346
 347         target_write_u8(target, info->addr, column);
 348
 349         if (nand->page_size > 512) {
 350                 target_write_u8(target, info->addr, column >> 8);
 351                 target_write_u8(target, info->cmd, NAND_CMD_RNDOUTSTART);
 352         }
 353
 354         if (!davinci_nand_ready(nand, 100))
 355                 return ERROR_NAND_OPERATION_TIMEOUT;
 356
 357         return ERROR_OK;
 358 }
 359
 360 static int davinci_writepage_tail(struct nand_device *nand,
 361                 uint8_t *oob, uint32_t oob_size)
 362 {
 363         struct davinci_nand *info = nand->controller_priv;
 364         struct target *target = nand->target;
 365         uint8_t status;
 366
 367         if (oob_size)
 368                 davinci_write_block_data(nand, oob, oob_size);
 369
 370         /* non-cachemode page program */
 371         target_write_u8(target, info->cmd, NAND_CMD_PAGEPROG);
 372
 373         if (!davinci_nand_ready(nand, 100))
 374                 return ERROR_NAND_OPERATION_TIMEOUT;
 375
 376         if (nand_read_status(nand, &status) != ERROR_OK) {
 377                 LOG_ERROR("couldn't read status");
 378                 return ERROR_NAND_OPERATION_FAILED;
 379         }
 380
 381         if (status & NAND_STATUS_FAIL) {
 382                 LOG_ERROR("write operation failed, status: 0x%02x", status);
 383                 return ERROR_NAND_OPERATION_FAILED;
 384         }
 385
 386         return ERROR_OK;
 387 }
 388
 389 /*
 390  * All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
 391  */
 392 static int davinci_write_page_ecc1(struct nand_device *nand, uint32_t page,
 393                 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 394 {
 395         unsigned oob_offset;
 396         struct davinci_nand *info = nand->controller_priv;
 397         struct target *target = nand->target;
 398         const uint32_t fcr_addr = info->aemif + NANDFCR;
 399         const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel);
 400         uint32_t fcr, ecc1;
 401
 402         /* Write contiguous ECC bytes starting at specified offset.
 403          * NOTE: Linux reserves twice as many bytes as we need; and
 404          * for 16-bit OOB, those extra bytes are discontiguous.
 405          */
 406         switch (nand->page_size) {
 407         case 512:
 408                 oob_offset = 0;
 409                 break;
 410         case 2048:
 411                 oob_offset = 40;
 412                 break;
 413         default:
 414                 oob_offset = 80;
 415                 break;
 416         }
 417
 418         davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
 419
 420         /* scrub any old ECC state */
 421         target_read_u32(target, ecc1_addr, &ecc1);
 422
 423         target_read_u32(target, fcr_addr, &fcr);
 424         fcr |= 1 << (8 + info->chipsel);
 425
 426         do {
 427                 /* set "start csX 1bit ecc" bit */
 428                 target_write_u32(target, fcr_addr, fcr);
 429
 430                 /* write 512 bytes */
 431                 davinci_write_block_data(nand, data, 512);
 432                 data += 512;
 433                 data_size -= 512;
 434
 435                 /* read the ecc, pack to 3 bytes, and invert so the ecc
 436                  * in an erased block is correct
 437                  */
 438                 target_read_u32(target, ecc1_addr, &ecc1);
 439                 ecc1 = (ecc1 & 0x0fff) | ((ecc1 & 0x0fff0000) >> 4);
 440                 ecc1 = ~ecc1;
 441
 442                 /* save correct ECC code into oob data */
 443                 oob[oob_offset++] = (uint8_t)(ecc1);
 444                 oob[oob_offset++] = (uint8_t)(ecc1 >> 8);
 445                 oob[oob_offset++] = (uint8_t)(ecc1 >> 16);
 446
 447         } while (data_size);
 448
 449         /* write OOB into spare area */
 450         return davinci_writepage_tail(nand, oob, oob_size);
 451 }
 452
 453 /*
 454  * Preferred "new style" ECC layout for use with 4-bit ECC.  This somewhat
 455  * slows down large page reads done with error correction (since the OOB
 456  * is read first, so its ECC data can be used incrementally), but the
 457  * manufacturer bad block markers are safe.  Contrast:  old "infix" style.
 458  */
 459 static int davinci_write_page_ecc4(struct nand_device *nand, uint32_t page,
 460                 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 461 {
 462         static const uint8_t ecc512[] = {
 463                 0, 1, 2, 3, 4, /* 5== mfr badblock */
 464                 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
 465         };
 466         static const uint8_t ecc2048[] = {
 467                 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
 468                 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
 469                 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
 470                 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
 471         };
 472         static const uint8_t ecc4096[] = {
 473                  48,  49,  50,  51,  52,  53,  54,  55,  56,  57,
 474                  58,  59,  60,  61,  62,  63,  64,  65,  66,  67,
 475                  68,  69,  70,  71,  72,  73,  74,  75,  76,  77,
 476                  78,  79,  80,  81,  82,  83,  84,  85,  86,  87,
 477                  88,  89,  90,  91,  92,  93,  94,  95,  96,  97,
 478                  98,  99, 100, 101, 102, 103, 104, 105, 106, 107,
 479                 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
 480                 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
 481         };
 482
 483         struct davinci_nand *info = nand->controller_priv;
 484         const uint8_t *l;
 485         struct target *target = nand->target;
 486         const uint32_t fcr_addr = info->aemif + NANDFCR;
 487         const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
 488         uint32_t fcr, ecc4;
 489
 490         /* Use the same ECC layout Linux uses.  For small page chips
 491          * it's a bit cramped.
 492          *
 493          * NOTE:  at this writing, 4KB pages have issues in Linux
 494          * because they need more than 64 bytes of ECC data, which
 495          * the standard ECC logic can't handle.
 496          */
 497         switch (nand->page_size) {
 498         case 512:
 499                 l = ecc512;
 500                 break;
 501         case 2048:
 502                 l = ecc2048;
 503                 break;
 504         default:
 505                 l = ecc4096;
 506                 break;
 507         }
 508
 509         davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
 510
 511         /* scrub any old ECC state */
 512         target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
 513
 514         target_read_u32(target, fcr_addr, &fcr);
 515         fcr &= ~(0x03 << 4);
 516         fcr |= (1 << 12) | (info->chipsel << 4);
 517
 518         do {
 519                 uint32_t raw_ecc[4], *p;
 520                 int i;
 521
 522                 /* start 4bit ecc on csX */
 523                 target_write_u32(target, fcr_addr, fcr);
 524
 525                 /* write 512 bytes */
 526                 davinci_write_block_data(nand, data, 512);
 527                 data += 512;
 528                 data_size -= 512;
 529
 530                 /* read the ecc, then save it into 10 bytes in the oob */
 531                 for (i = 0; i < 4; i++) {
 532                         target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
 533                         raw_ecc[i] &= 0x03ff03ff;
 534                 }
 535                 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
 536                         oob[*l++] =   p[0]        & 0xff;
 537                         oob[*l++] = ((p[0] >>  8) & 0x03) | ((p[0] >> 14) & 0xfc);
 538                         oob[*l++] = ((p[0] >> 22) & 0x0f) | ((p[1] <<  4) & 0xf0);
 539                         oob[*l++] = ((p[1] >>  4) & 0x3f) | ((p[1] >> 10) & 0xc0);
 540                         oob[*l++] =  (p[1] >> 18) & 0xff;
 541                 }
 542
 543         } while (data_size);
 544
 545         /* write OOB into spare area */
 546         return davinci_writepage_tail(nand, oob, oob_size);
 547 }
 548
 549 /*
 550  * "Infix" OOB ... like Linux ECC_HW_SYNDROME.  Avoided because it trashes
 551  * manufacturer bad block markers, except on small page chips.  Once you
 552  * write to a page using this scheme, you need specialized code to update
 553  * it (code which ignores now-invalid bad block markers).
 554  *
 555  * This is needed *only* to support older firmware.  Older ROM Boot Loaders
 556  * need it to read their second stage loader (UBL) into SRAM, but from then
 557  * on the whole system can use the cleaner non-infix layouts.  Systems with
 558  * older second stage loaders (ABL/U-Boot, etc) or other system software
 559  * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
 560  */
 561 static int davinci_write_page_ecc4infix(struct nand_device *nand, uint32_t page,
 562                 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 563 {
 564         struct davinci_nand *info = nand->controller_priv;
 565         struct target *target = nand->target;
 566         const uint32_t fcr_addr = info->aemif + NANDFCR;
 567         const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
 568         uint32_t fcr, ecc4;
 569
 570         davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
 571
 572         /* scrub any old ECC state */
 573         target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
 574
 575         target_read_u32(target, fcr_addr, &fcr);
 576         fcr &= ~(0x03 << 4);
 577         fcr |= (1 << 12) | (info->chipsel << 4);
 578
 579         do {
 580                 uint32_t raw_ecc[4], *p;
 581                 uint8_t *l;
 582                 int i;
 583
 584                 /* start 4bit ecc on csX */
 585                 target_write_u32(target, fcr_addr, fcr);
 586
 587                 /* write 512 bytes */
 588                 davinci_write_block_data(nand, data, 512);
 589                 data += 512;
 590                 data_size -= 512;
 591
 592                 /* read the ecc */
 593                 for (i = 0; i < 4; i++) {
 594                         target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
 595                         raw_ecc[i] &= 0x03ff03ff;
 596                 }
 597
 598                 /* skip 6 bytes of prepad, then pack 10 packed ecc bytes */
 599                 for (i = 0, l = oob + 6, p = raw_ecc; i < 2; i++, p += 2) {
 600                         *l++ =   p[0]        & 0xff;
 601                         *l++ = ((p[0] >>  8) & 0x03) | ((p[0] >> 14) & 0xfc);
 602                         *l++ = ((p[0] >> 22) & 0x0f) | ((p[1] <<  4) & 0xf0);
 603                         *l++ = ((p[1] >>  4) & 0x3f) | ((p[1] >> 10) & 0xc0);
 604                         *l++ =  (p[1] >> 18) & 0xff;
 605                 }
 606
 607                 /* write this "out-of-band" data -- infix */
 608                 davinci_write_block_data(nand, oob, 16);
 609                 oob += 16;
 610                 oob_size -= 16;
 611
 612         } while (data_size);
 613
 614         /* the last data and OOB writes included the spare area */
 615         return davinci_writepage_tail(nand, NULL, 0);
 616 }
 617
 618 static int davinci_read_page_ecc4infix(struct nand_device *nand, uint32_t page,
 619                 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 620 {
 621         int read_size;
 622         int want_col, at_col;
 623         int ret;
 624
 625         davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
 626
 627         /* large page devices need a start command */
 628         if (nand->page_size > 512)
 629                 davinci_command(nand, NAND_CMD_READSTART);
 630
 631         if (!davinci_nand_ready(nand, 100))
 632                 return ERROR_NAND_OPERATION_TIMEOUT;
 633
 634         /* NOTE:  not bothering to compute and use ECC data for now */
 635
 636         want_col = 0;
 637         at_col = 0;
 638         while ((data && data_size) || (oob && oob_size)) {
 639
 640                 if (data && data_size) {
 641                         if (want_col != at_col) {
 642                                 /* Reads are slow, so seek past them when we can */
 643                                 ret  = davinci_seek_column(nand, want_col);
 644                                 if (ret != ERROR_OK)
 645                                         return ret;
 646                                 at_col = want_col;
 647                         }
 648                         /* read 512 bytes or data_size, whichever is smaller*/
 649                         read_size = data_size > 512 ? 512 : data_size;
 650                         davinci_read_block_data(nand, data, read_size);
 651                         data += read_size;
 652                         data_size -= read_size;
 653                         at_col += read_size;
 654                 }
 655                 want_col += 512;
 656
 657                 if (oob && oob_size) {
 658                         if (want_col != at_col) {
 659                                 ret  = davinci_seek_column(nand, want_col);
 660                                 if (ret != ERROR_OK)
 661                                         return ret;
 662                                 at_col = want_col;
 663                         }
 664                         /* read this "out-of-band" data -- infix */
 665                         read_size = oob_size > 16 ? 16 : oob_size;
 666                         davinci_read_block_data(nand, oob, read_size);
 667                         oob += read_size;
 668                         oob_size -= read_size;
 669                         at_col += read_size;
 670                 }
 671                 want_col += 16;
 672         }
 673         return ERROR_OK;
 674 }
 675
 676 NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command)
 677 {
 678         struct davinci_nand *info;
 679         unsigned long chip, aemif;
 680         enum ecc eccmode;
 681         int chipsel;
 682
 683         /* arguments:
 684          *  - "davinci"
 685          *  - target
 686          *  - nand chip address
 687          *  - ecc mode
 688          *  - aemif address
 689          * Plus someday, optionally, ALE and CLE masks.
 690          */
 691         if (CMD_ARGC < 5) {
 692                 LOG_ERROR("parameters: %s target "
 693                                 "chip_addr hwecc_mode aemif_addr",
 694                                 CMD_ARGV[0]);
 695                 goto fail;
 696         }
 697
 698         COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
 699         if (chip == 0) {
 700                 LOG_ERROR("Invalid NAND chip address %s", CMD_ARGV[2]);
 701                 goto fail;
 702         }
 703
 704         if (strcmp(CMD_ARGV[3], "hwecc1") == 0)
 705                 eccmode = HWECC1;
 706         else if (strcmp(CMD_ARGV[3], "hwecc4") == 0)
 707                 eccmode = HWECC4;
 708         else if (strcmp(CMD_ARGV[3], "hwecc4_infix") == 0)
 709                 eccmode = HWECC4_INFIX;
 710         else {
 711                 LOG_ERROR("Invalid ecc mode %s", CMD_ARGV[3]);
 712                 goto fail;
 713         }
 714
 715         COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[4], aemif);
 716         if (aemif == 0) {
 717                 LOG_ERROR("Invalid AEMIF controller address %s", CMD_ARGV[4]);
 718                 goto fail;
 719         }
 720
 721         /* REVISIT what we'd *like* to do is look up valid ranges using
 722          * target-specific declarations, and not even need to pass the
 723          * AEMIF controller address.
 724          */
 725         if (aemif == 0x01e00000                 /* dm6446, dm357 */
 726                         || aemif == 0x01e10000  /* dm335, dm355 */
 727                         || aemif == 0x01d10000  /* dm365 */
 728                         ) {
 729                 if (chip < 0x02000000 || chip >= 0x0a000000) {
 730                         LOG_ERROR("NAND address %08lx out of range?", chip);
 731                         goto fail;
 732                 }
 733                 chipsel = (chip - 0x02000000) >> 25;
 734         } else {
 735                 LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif);
 736                 goto fail;
 737         }
 738
 739         info = calloc(1, sizeof *info);
 740         if (info == NULL)
 741                 goto fail;
 742
 743         info->eccmode = eccmode;
 744         info->chipsel = chipsel;
 745         info->aemif = aemif;
 746         info->data = chip;
 747         info->cmd = chip | 0x10;
 748         info->addr = chip | 0x08;
 749
 750         nand->controller_priv = info;
 751
 752         info->io.target = nand->target;
 753         info->io.data = info->data;
 754         info->io.op = ARM_NAND_NONE;
 755
 756         /* NOTE:  for now we don't do any error correction on read.
 757          * Nothing else in OpenOCD currently corrects read errors,
 758          * and in any case it's *writing* that we care most about.
 759          */
 760         info->read_page = nand_read_page_raw;
 761
 762         switch (eccmode) {
 763         case HWECC1:
 764                 /* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
 765                 info->write_page = davinci_write_page_ecc1;
 766                 break;
 767         case HWECC4:
 768                 /* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
 769                 info->write_page = davinci_write_page_ecc4;
 770                 break;
 771         case HWECC4_INFIX:
 772                 /* Same 4-bit ECC HW, with problematic page/ecc layout */
 773                 info->read_page = davinci_read_page_ecc4infix;
 774                 info->write_page = davinci_write_page_ecc4infix;
 775                 break;
 776         }
 777
 778         return ERROR_OK;
 779
 780 fail:
 781         return ERROR_NAND_OPERATION_FAILED;
 782 }
 783
 784 struct nand_flash_controller davinci_nand_controller = {
 785         .name                   = "davinci",
 786         .nand_device_command    = davinci_nand_device_command,
 787         .init                   = davinci_init,
 788         .reset                  = davinci_reset,
 789         .command                = davinci_command,
 790         .address                = davinci_address,
 791         .write_data             = davinci_write_data,
 792         .read_data              = davinci_read_data,
 793         .write_page             = davinci_write_page,
 794         .read_page              = davinci_read_page,
 795         .write_block_data       = davinci_write_block_data,
 796         .read_block_data        = davinci_read_block_data,
 797         .nand_ready             = davinci_nand_ready,
 798 };